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| features ? high performance, low power 32-bit atmel ? avr ? mic rocontroller ? co m pa c t si ngle-c yc l e ris c in st r u ct io n se t i n clud i n g dsp i n stru cti o n set ? read-modify- w rite instruction s an d atom ic bit manipulation ? perform ing 1.49 dmips / mhz up to 91 d m ips runnin g at 66 mh z fr om flash (1 wait-state) up to 49 dm ips running at 33 mhz fr om flash (0 wait-state) ? memory p rotectio n unit ? multi-hierarchy bu s system ? high-performanc e data transfers on separat e buses fo r increased performance ? 15 peripheral dma ch annels improves speed for peripheral communication ? internal hi gh-speed flash ? 512k by tes, 256k bytes, 1 28k bytes versions ? s ingle cycle acces s up to 33 mhz ? p refetc h buff er optimizing instru ction execution at maximu m speed ? 4m s pa ge pr ogramming time and 8 m s full-chip era se time ? 100,0 00 write cycles , 15-yea r data rete ntion capability ? f las h security lo c ks and user defined configuratio n area ? internal hi gh-speed sram , single-cycl e acces s at full speed ? 64k byte s (512kb and 256kb flas h), 32k byte s (128kb flash) ? external m emory interfa ce on at32u c3a0 derivatives ? s dram / sram compati ble memory bus (16-bit da ta and 24-bit address buses) ? interrupt cont roller ? autov ectored lo w latency interrupt serv ice wi th programmab le priority ? system functions ? pow er and cloc k manage r includin g internal rc clo c k and one 32khz oscillator ? two multipurpose oscillato r s and two phase-lock-loo p (pll ) allowing independ ant cpu frequenc y fr om usb frequency ? w atch do g t imer, real- tim e clock ti m er ? univer sal se rial bus (usb) ? dev ice 2.0 full sp eed and on-the-go (otg) low sp eed an d fu ll speed ? flexibl e end-poin t configuratio n an d management with dedica ted dma channels ? on-chip transceivers incl uding pull-ups ? ethe rn e t m ac 10 /100 mbp s i nt erfa ce ? 802.3 ethernet m e dia acce ss controller ? support s media independent interfac e (mii) and reduc e d mii (rmii) ? one three-channel 16- bit timer/counte r (tc) ? three external cloc k inputs, pwm, captur e and various counting capabilities ? one 7-channel 16-bit pulse width modulation controller (pwm) ? four universa l synchronous/asynchronous receiver/transmitters (usart) ? independant baudrate generator, suppor t for sp i, ir da and iso 7816 inter fac es ? s upport fo r hardwa re ha ndshak i ng, rs485 interface s and mode m line ? tw o master/slave serial pe ripheral interfa ces (spi) with chip select signals ? on e synchronou s serial protocol controller ? s upport s i2s an d generic frame-ba sed protocols ? one maste r/slave tw o-wire interfa ce (twi ), 4 00kbit/s i2c-compati b le ? one 8- chan nel 10 -bit analog-t o-digital converter ? 16-bit stereo au dio bitstream ? sampl e r a t e u p to 50 k hz 32-bit atmel avr microcontroller at32uc3a0512 at32uc3a0256 at32uc3a0128 at32uc3a1512 at32uc3a1256 at32uc3a1128 32058k- avr32-01/12
2 at32uc3a ? on-chip de bu g syst em (jta g interface) ? nex us class 2+ , runtime contro l, non-intrusive data and p rogram trace ? 100-pi n tq fp (69 gp i o pi ns), 144-pi n lq fp (109 gp io pins) , 144 bga (109 gpi o pi ns) ? 5v input tolerant i/os ? single 3.3v po wer suppl y or dual 1.8v -3 .3 v po wer supp ly 32058k avr32-01/12 3 at32uc3a 1. desc ri pti on th e at32 uc3a is a comple te system-on-chi p microcontroller base d on the avr32 uc ris c processor run n ing at frequencies up to 66 mhz. avr3 2 uc is a high-p erfor mance 32-bi t risc mic ropro cess o r core , desi g n e d fo r c o st-s ensitiv e embedded applications, with particular empha- sis on low power consumption, high code de nsity an d high performance. th e processor implemen ts a memo ry protection unit (mpu) and a fast and flexible interrupt con- tro lle r fo r s uppo rtin g moder n op era ti n g syste ms an d re al -time op era tin g syst ems . highe r computation capabilitie s ar e achievable using a rich set of d sp instructions. th e at32uc3 a incorporates on -chip flash an d sra m memories fo r se cure and fa st access. for a pplications requiring additional mem ory, an ext ernal memory interf ace is provided on at32uc3a 0 derivatives. th e peripher al direct memory acce ss controll er (pdca ) enables data transfer s between periph- er als and memori es without pr ocessor involve m e n t . p dc a drastically re duces processing overhead whe n transferr ing continuou s an d larg e dat a str eams b etwee n modules withi n the mcu. th e powermanage r improves design flexibility an d security: the on-c h ip brown-out detector monitors the po wer supply, the cpu runs from t he on-chip rc oscillator or from one of external oscillator sources, a real-time clock and its assoc iated timer ke eps track of the time. the time r/count er includes three id entical 16-bit timer/counter ch annels. each chann el can be independently programmed t o perfor m fre quency measurement, event counting, int erval mea- su rem ent , pu lse ge nera tion , delay ti ming an d pulse widt h mod ulati on. the pwm modules provides seven independ ent channels wi th many configura tion options includin g polarity , edg e alignmen t an d waveform non overla p control. one pwm channe l can trigger adc c onversion s fo r more accurate close lo op control implementations. th e at32uc3a also f eatures many communicati on interfaces fo r communication intensive applications . in addition to standar d seri al interfac es like uart, spi o r twi, othe r interfaces like flexible synchron ous seri al controller, usb a nd ethernet mac a r e available. th e synchronou s seri al controlle r provides ea sy access to serial communicat ion prot ocols and audio standar ds like i2s. the full -s peed usb 2. 0 device interf ace supports several usb classes at the same time thanks t o th e rich end-point configuration. t he on -the- go ( o tg) host inte rf ace allows device like a usb fl as h di sk or a usb p rinter t o be dire ctly connected to th e processor. the media-independen t interface (mii) an d reduced mi i (rmii) 10/1 00 ethernet ma c module provides on-chi p solutions fo r network-connected devices. at32uc3a integrates a class 2+ nex u s 2.0 on -chip de bug (ocd) syste m, with non-intrusive real-time trace, full-spee d read/write memory access i n a ddition to basic runtim e control. 32058k avr32-01/12 4 at32uc3a 2. configuration summa ry the table belo w list s a ll a t32uc 3a memory an d p ackag e c o nfigu rati ons: 3. abbreviations ? gclk: powe r manager gener ic clock ? gpio: gener al purpose input/output ? h sb: high speed bus ? mpu: memory protecti on unit ? ocd : on ch ip debug ? pb: peripher al bus ? pdca: peripher al direct memory access c ontroller (pdc) vers ion a ? usbb : us b on-the-go controller ve rsion b de vice flash sram ext. bus inte rf a ce ethernet m ac p a ck a ge at3 2uc3a05 12 5 12 kbytes 64 k bytes yes yes 1 44 pi n lqfp 1 44 pin bga at3 2uc3a02 56 2 56 kbytes 64 k bytes yes yes 1 44 pi n lqfp 1 44 pin bga at3 2uc3a01 28 1 28 kbytes 32 k bytes yes yes 1 44 pi n lqfp 1 44 pin bga at3 2uc3a15 12 512 k bytes 6 4 k b y t es no y es 10 0 pi n tqfp at3 2uc3a12 56 256 k bytes 6 4 k b y t es no y es 10 0 pi n tqfp at3 2uc3a11 28 128 k bytes 3 2 k b y t es no y es 10 0 pi n tqfp 32058k avr32-01/12 5 at32uc3a 4. blockdiagram figur e 4-1. blockdiagram uc cpu nexus class 2+ ocd in str in terface data in terface timer/counter interrupt controller real time counter peripheral dma controller 512 kb fla sh hsb-pb br idge b hsb -pb bridg e a memory interf ace s m m m m m s s s s s m external interrupt controller high speed bus matrix fast gpio genera l purp ose ios 6 4 kb sram general pu rpose ios pa pb pc px a[2..0] b[2..0] clk[2..0] extint[7..0] kps [7.. 0] nmi_n gc lk[3..0] xin32 xout32 xin0 xout0 pa pb pc px rese t_n external bus int erface (sdram & stati c memo ry controller) cas ras sda10 sdck sdcke sdcs0 sdwe ncs [3..0] nrd nw ait nwe0 data[15..0] usb in terface dma id vbof vbus d- d+ ethernet mac dma 32 khz osc 1 15 khz rco sc osc0 p ll0 pulse width modulation controller serial peripheral interface 0/1 tw o-w ire in terface p dc pdc p dc miso, mosi npcs [3 ..1] pw m [ 6.. 0] scl sda usart1 pdc rxd txd clk rts, cts ds r, dtr, dc d , ri usart0 usart2 usart3 p dc rxd txd clk rts, cts synchronous serial controller pdc tx_ cloc k, t x_fr ame_ sy nc rx_data tx_ d ata rx_ cl ock , rx_f ram e_sy nc analog to digital co nver ter pdc ad [7..0] advref watchdog timer xin1 xout1 osc1 p ll1 sck jtag in terface mcko mdo [ 5..0] mseo [1..0] evti_n evto_n tck tdo tdi tms power manager reset controller addr [23..0] sleep controller clock controller clock generator col, crs, rxd[3..0], rx _clk, rx_dv, rx_er mdc, txd[3..0], tx_clk, tx_en, tx_er, speed mdio flash controller configuratio n register s bus memo ry protection unit pb pb hsb hs b nwe1 nwe3 p ba p bb npcs0 local bus in terface audio bitstream dac pdc data [1.. 0] datan[ 1 ..0] 32058k avr32-01/12 6 at32uc3a 4.1 pr ocessor and architecture 4.1.1 a vr32 uc cpu ? 32-bit load/store av r32a risc architecture. ? 15 general-purp ose 32 -bit registers. ? 32- bit stack pointer, prog ram coun ter an d li nk regi ster reside in regist er file. ? fully orthogonal instructio n set. ? privilege d and unprivileged mode s enabling efficient and s ecure oper ating systems. ? innovativ e instru ction set together with variable instruction length ens ur i ng industry le ading code density. ? dsp ex tention with saturating arithmetic , and a wide variet y of mult ipl y instru ctio ns. ? 3 st ag e pipeline allo ws one instruction per clock cycle for most instructions. ? byte, half-word, word an d double word memory access. ? m ultiple interrupt priority levels. ? mpu a llows fo r operating system s with m emor y protection. 4.1.2 deb ug and test system ? ieee1149 .1 compliant jtag an d boundary scan ? direct me mory acces s an d p r og rammi ng ca pabilities through jtag interface ? extensive on-chip de bu g features in complian c e with ieee-isto 5001-2003 (nex us 2.0) class 2+ ? lo w- c ost nano tr ac e suppo rt ed. ? auxiliary port fo r high-spe ed tra ce information ? hardw are support fo r 6 prog ram an d 2 d ata breakpoints ? unlimited nu mber of software brea kpoints supported ? adva nced pr ogram, data, ownership , and watchpoi nt trace supported 4.1. 3 p eripheral dma contro ller ? transfer s fr om/to peripheral to/fro m any memory spac e without interventio n of the p rocess o r. ? next pointe r support, forb ids strong real -time constraints on buffe r management. ? fifteen c hann e ls ? two fo r eac h usart ? two fo r each serial synchronou s controller ? two fo r eac h serial peripher al interface ? one for each adc ? two fo r eac h twi interface 4.1.4 b us system ? hi g h spe ed b u s (h sb) m atrix wi th 6 master s and 6 slav es handled ? handles requests fr om the cpu data fetch, cpu instr uction fetch, pdca , usbb, ethernet controller , cpu sab, an d to inte rnal flas h, internal sram, peripher al bus a, peripheral bus b, ebi. ? ro un d -rob in arbi tratio n (th ree mod e s sup p o rte d : n o de faul t m aster, las t accessed default master, fixe d default master) ? bur st brea king with slot cycle limit ? o n e a dd re s s d ecode r pro vi ded pe r master 32058k avr32-01/12 7 at32uc3a ? peripheral bus a able to r un on at d ivided bu s sp ee ds compa r ed to the h i gh spe ed bus figure 4-1 gives an overview of th e bu s system . all modules connected to the same bus use the same clock, bu t th e clock t o eac h modu le ca n be individua lly sh ut off by the power manager. the figure identifies t he numbe r of mast er and slave in terfaces of ea ch modu le connected to the high speed bus, and which dma con troller is co nnected to which p eripheral. 32058k avr32-01/12 8 at32uc3a 5. signals description th e following tabl e gives deta ils on th e signal name classifi ed by peripheral th e signa ls are multip lexed with gpio pins as d escribe d in ?peripheral multiple x ing on i/o lines? o n pag e 45. tabl e 5-1. sig n al d e scriptio n l i st sign al name function type ac ti ve level comments power vddpll powe r supply f or pll power i n put 1 . 6 5 v t o 1 .9 5 v vddcore core pow er supply power i n put 1 . 6 5 v t o 1 .9 5 v vddio i/o power supply power i n put 3 . 0 v to 3 . 6v vddana analog power supply power i n put 3 . 0 v to 3.6v v d d in vol t ag e reg ulat or inpu t s u p p ly power i n put 3 . 0 v to 3.6v vddout volta ge reg ulator output power output 1 . 6 5 v t o 1 .9 5 v gndana ana log ground ground gnd gr o und g r o und cloc ks, oscillator s, and pll?s xin0 , xin1 , xin32 crystal 0, 1, 32 input analog xout0, xout 1, xout32 crysta l 0, 1, 32 output analog jtag tck t est clock input tdi test data in input tdo t est data out output tms t est mode select input au xiliar y p or t - a ux mcko tr ace data output clo ck output mdo0 - mdo5 tr ace data output output 32058k avr32-01/12 9 at32uc3a mseo0 - mseo1 trace frame control output evti_n event in output l ow evto_n event out output low power manager - pm gclk0 - g clk3 gener ic clock pins output reset_n r eset pin input low real time c oun ter - rtc r tc _c l oc k rtc clo ck o u t p ut watchdog timer - wdt wdtext external watch dog pin output external interru p t con tro ller - eic extint0 - extint7 exter nal interr upt pins input k ps0 - kps7 ke ypad scan pins output nmi_n non-maskabl e interrupt pin input low ethernet m a c - macb col collisi on detect input crs carr ier sense an d data valid input mdc man ageme n t data clock output mdio managemen t data input/output i/o rxd0 - rxd3 receiv e data input rx_clk receiv e clock input rx_dv receiv e data valid input rx_er receive coding error input speed speed txd0 - txd3 tr an sm it data outp ut tx_clk transmit clock or re fe rence clock output tx_en transmi t enable output tx_er transmi t cod ing error output tabl e 5-1. sig n al d e sc riptio n l i st sign al name function type ac ti ve level comments 32058k avr32-01/12 10 at32uc3a external bu s interf ace - hebi ad dr0 - addr23 addr ess bus output cas co lumn signal output low data0 - data15 data bus i/o ncs0 - n cs3 ch ip sel e ct output l ow nrd re ad signal output low nwait external wa it signal input low nwe0 wr ite enabl e 0 output low nwe1 wr ite enabl e 1 output low nwe3 wr ite enabl e 3 output low ras row signal output l ow sda10 s dram address 10 line output sdck sdram clo ck output sdcke s dram clock enable output sdcs0 s dram chip select output low s d we s dr am writ e e n ab le out put l ow gene ral purp ose input/outp ut 2 - gpioa, gpiob, gpioc p0 - p31 parallel i /o controller gpioa i/o p0 - p31 parallel i /o controller gpiob i/o p0 - p5 para llel i /o contr o lle r gp i oc i/o p0 - p31 parallel i /o controller gpiox i/o serial pe ripheral interfac e - spi0, spi1 miso mast er in slav e out i/o mosi master ou t slav e in i/o npcs0 - npcs3 spi perip heral chip select i/o low sck clock output synchron ous serial controller - ssc rx_clock ssc rece iv e clock i/o tabl e 5-1. sig n al d e sc riptio n l i st sign al name function type ac ti ve level comments 32058k avr32-01/12 11 at32uc3a rx_data ssc rece iv e data input rx_frame_sync ssc rece ive fr ame sync i/o tx_clock ssc tr ansmit clock i/o tx_data ssc tr ansmit data output tx_frame_sync ssc transmit fr ame sync i/o timer/coun ter - timer a0 channe l 0 lin e a i/o a1 channe l 1 lin e a i/o a2 channe l 2 lin e a i/o b0 channe l 0 lin e b i/o b1 channe l 1 lin e b i/o b2 channe l 2 lin e b i/o clk0 channe l 0 external cloc k input input clk1 channe l 1 external cloc k input input clk2 channe l 2 external cloc k input input two-wi re interface - twi scl ser ial clock i/o s da seri a l da ta i/o universa l synchronous asynchro nous receiver t r an smit t e r - usar t0 , usa r t1, u s a r t2 , usa r t3 c lk c lo ck i/o cts cle a r t o s e nd in put dcd data car r ie r d e te ct onl y usa r t1 dsr data set rea dy onl y usart1 dtr data terminal ready only usart1 ri ri ng indicator onl y usart1 rts request to send output rxd receiv e data input txd transmi t data output tabl e 5-1. sig n al d e sc riptio n l i st sign al name function type ac ti ve level comments 32058k avr32-01/12 12 at32uc3a analog to digital co nver ter - adc ad 0 - ad7 ana log in put pins analog input advref ana log positive reference voltag e input analog input 2. 6 t o 3.6v pu lse width modulator - pwm pw m0 - pwm6 pwm o utput pins output univer sal serial bu s device - usb ddm usb d evice port data - analog ddp usb d evice port data + analog vbus u sb v bus mon i to r and ot g n e g o ciation analog in put usbid i d pin of the usb bus input usb_v bof u sb vbus o n/o ff: b u s p ower contro l port output audio bitstream dac (abdac) data0-data1 d /a data out outpu datan0-datan1 d /a data invert ed out outpu tabl e 5-1. sig n al d e sc riptio n l i st sign al name function type ac ti ve level comments 32058k avr32-01/12 13 at32uc3a 6. power considerations 6.1 pow er supplies th e at32 uc3a ha s several types of power supp ly pins: ? vddio: powers i/ o lines. voltag e is 3.3v nominal. ? vddana: powers the adc voltag e is 3.3v nominal. ? vddi n: in pu t vo lta g e fo r th e vo lta g e regul a tor . voltage i s 3.3v no minal. ? vddcore: powers the core , memories , and peripherals. voltag e is 1.8v nominal. ? vddp ll : power s t he pl l. vo l t a g e i s 1 . 8v no minal. the ground pins gnd a r e commo n to vddcore, v dd io , v dd pll . t h e gr ound pi n for vdd ana is gndana. refe r to ?power co nsum pti on? on pa g e 767 fo r powe r consumptio n on t he vari ous supp ly pins. 3. 3v vddana vd dio vddin vddcore vdd out vddpll advref 3. 3v 1 .8v vddana vddio vd din vd dcore vddout vddpll advref single power supply dual power supply 1.8v regulator 1.8v regulator 32058k avr32-01/12 14 at32uc3a 6.2 voltage regulator 6.2.1 single po wer supply th e at 32uc3a em b eds a volta ge regu lato r tha t converts fro m 3.3v to 1.8v. th e reg ulato r t a kes its input voltage from vddi n, and su pplies the output voltage on vddo ut. vddout should be exte rnally con nec ted to th e 1. 8v do mains . adequate input supply decouplin g is mandatory for vddin in o r der to improve st a rtu p sta b ilit y an d re duce sour ce voltage drop . two input decoup ling capacito rs must be placed close to the chip. adequate output supp ly decouplin g is mandatory for vddout to reduce ripple and avoid oscil- lati ons. th e best way t o achieve this is t o u se two c a pacit or s in paralle l betwee n v ddou t an d gnd as clos e to t he chi p as possible refe r to sectio n 38.3 on p ag e 765 fo r decouplin g capacitors values an d regulato r characteristics 6.2.2 dual powe r supply in c a se of dual power su pply, vddin and vddo ut shou ld be connected t o grou nd t o prevent fro m leaka g e curre nt. 3.3v 1.8v vddin vddout 1.8v regulator c in1 c ou t1 c out2 c in2 vddin vddout 32058k avr32-01/12 15 at32uc3a 6.3 a nalog-to-digital conver ter (a.d .c) reference. the adc reference (advref) must be provided f rom an external source. two decoupling capacitors mu st be used to insur e proper decoupling. refer to se ction 38 .4 on pag e 765 for de coupling capacit ors values an d electrical ch ar acteri st ics. in case ad c is not used, the ad vr ef pin shou ld be connected to gnd t o avoid extra consumption. advref c c vref1 vref2 3.3v 32058k avr32-01/12 16 at32uc3a 7. p ackag e an d pino ut the device pins are multiplexed with peripheral function s as described in ?periphera l multiplexing on i / o lines? on pa ge 45. figur e 7-1. tqfp10 0 pinout 1 25 26 50 51 75 76 100 tabl e 7-1. tqfp10 0 packa ge pinout 1 pb20 26 pa05 51 pa21 76 pb08 2 pb21 27 pa06 52 pa22 77 pb09 3 pb22 28 pa07 53 pa23 78 pb10 4 vddio 29 pa08 54 pa24 79 vd dio 5 gnd 30 pa09 55 pa25 80 gnd 6 pb23 31 pa10 56 pa26 81 pb11 7 pb24 32 n/c 57 pa27 82 pb12 8 pb25 33 pa11 58 pa28 83 pa29 9 pb26 34 vd d c ore 59 vddana 84 pa30 10 pb27 35 gnd 60 ad vref 85 pc02 11 vddout 36 pa12 61 gndana 86 pc03 12 vddin 37 pa13 62 vddpll 87 pb13 13 gnd 38 vd d c ore 63 pc00 88 pb14 14 pb28 39 pa 14 64 pc01 89 tms 15 pb29 40 pa15 65 pb00 90 tck 16 pb30 41 pa16 66 pb01 91 tdo 17 pb31 42 pa17 67 v dd io 92 tdi 18 reset_n 43 pa18 68 v dd io 93 pc04 19 pa00 44 pa19 69 gnd 94 pc05 20 pa01 45 pa20 70 pb02 95 pb15 21 gnd 46 vbus 71 pb03 96 pb16 22 vd dcore 47 vddio 72 pb04 97 vddcore 32058k avr32-01/12 17 at32uc3a figur e 7-2. l q fp14 4 pi no ut 23 pa02 48 dm 73 pb05 98 pb17 24 pa03 49 dp 74 pb06 99 pb18 25 pa04 50 gnd 75 pb07 100 pb19 tabl e 7-1. tqfp10 0 packa ge pinout 1 36 37 72 73 108 109 144 tabl e 7-2. vqfp144 packag e pinout 1 px00 37 gnd 73 pa21 109 gnd 2 px01 38 px10 74 pa22 110 px30 3 pb20 39 pa05 75 pa23 111 pb08 4 px02 40 px11 76 pa24 112 px31 5 pb21 41 pa06 77 pa25 113 pb09 6 pb22 42 px12 78 pa26 114 px32 7 v ddio 43 pa07 79 pa27 115 pb10 8 gnd 44 px13 80 pa28 116 vd dio 9 pb23 45 pa08 81 vddana 117 gnd 10 px03 46 px14 82 ad vref 118 px33 11 pb24 47 pa09 83 gndana 119 pb11 12 px04 48 pa10 84 vddpll 120 px34 13 pb25 49 n/c 85 pc00 121 pb12 14 pb26 50 pa 11 86 pc01 122 pa29 15 pb27 51 vdd c ore 87 px20 123 pa30 16 vddout 52 gnd 88 pb00 124 pc02 17 vddin 53 pa12 89 px21 125 pc03 18 gnd 54 pa13 90 pb01 126 pb13 19 pb28 55 vdd c ore 91 px22 127 pb14 20 pb29 56 pa14 92 v ddio 128 tms 21 pb30 57 pa15 93 v dd io 129 tck 32058k avr32-01/12 18 at32uc3a figur e 7-3. bga1 44 pinout 22 pb31 58 pa16 94 gnd 130 tdo 23 reset_n 59 px15 95 px23 131 tdi 24 px05 60 pa17 96 pb02 132 pc04 25 pa00 61 px16 97 px24 133 pc05 26 px06 62 pa18 98 pb03 134 pb15 27 pa01 63 px17 99 px25 135 px35 28 gnd 64 pa19 100 pb04 136 pb16 29 vd dcore 65 px18 101 px26 137 px36 30 pa02 66 pa20 102 pb05 138 vddcore 31 px07 67 px19 103 px27 139 pb17 32 pa03 68 vbus 104 pb06 140 px37 33 px08 69 vddio 105 px28 141 pb18 34 pa04 70 dm 106 pb07 142 px38 35 px09 71 dp 107 px29 143 pb19 36 vdd io 72 gnd 108 v ddio 144 px39 tabl e 7-2. vqfp144 packag e pinout 32058k avr32-01/12 19 at32uc3a note: nc is not c onnected. tabl e 7-3. bga144 package pinout a1..m8 1 2 3 4 5 6 7 8 a vddio pb07 pb05 pb02 pb03 pb01 pc00 pa28 b pb08 gnd pb06 pb04 vddio pb00 pc01 vddpll c pb09 px33 pa29 pc02 px28 px26 px22 px21 d pb11 pb13 pb12 px30 px29 px25 px24 px20 e pb10 vddio px32 px31 vddio px27 px23 vddana f pa30 pb14 px34 pb16 tck gnd gnd px16 g tms pc03 px36 px35 px37 gnd gnd pa16 h tdo vddcore px38 px39 vddio pa01 pa10 vddcore j tdi pb17 pb15 px00 px01 pa00 pa03 pa04 k pc05 pc04 pb19 pb20 px02 pb29 pb30 pa02 l pb21 gnd pb18 pb24 vddout px04 pb31 vddin m pb22 pb23 pb25 pb26 px03 pb27 pb28 reset_n tabl e 7-4. bga144 package pi nout a9..m12 9 10 11 12 a pa26 pa25 pa24 pa23 b pa27 pa21 gnd pa22 c advref gndana px19 pa19 d pa18 pa20 dp dm e px18 px17 vddio vbus f pa17 px15 pa15 pa14 g pa13 pa12 pa11 nc h p x11 pa08 v ddc ore v dd co re j p x14 pa07 px13 pa09 k px08 gnd pa05 px12 l px06 px10 gnd pa06 m px05 px07 px09 vddio 32058k avr32-01/12 20 at32uc3a 8. i/o line considerations 8.1 jta g pins tms, tdi and tck h ave pull-up resistors. tdo is a n output, drive n at up to vddio, and has n o pull-up resistor. 8.2 reset_n pin th e reset_n pin is a schmi tt input a nd inte grates a permanent pull-up resis tor to vddio. a s the product integra t es a power-on reset cell, the reset_n pin can be left unconnected in cas e no reset from the syste m needs to b e applie d to th e product. 8.3 t wi pins w he n the s e p in s a r e u se d fo r twi, th e pins ar e open-dr ain output s with slew-rate limitatio n and inputs wit h inputs with spike-filtering. when used as gpio-pins or used fo r othe r peripherals , the pins have th e same characterist ics as pio pins. 8.4 g pio pins all the i/o lines integrate a programmable pull-up resistor. progra m mi ng o f this p ul l- up resisto r is perform ed independ ently for each i/o line thr o ugh the gpio co ntrollers. after reset, i/o lines default as inpu ts with pull-up resistor s disabled, except wh en indicated othe rwise in t he column ?r ese t s tate ? of th e g pi o co ntr o lle r multiplexin g table s. 32058k avr32-01/12 21 at32uc3a 9. p r ocessor and architecture this chapter gives an ov erview of the avr32uc cpu. avr32uc is a n implementation of the avr32 architecture. a sum mar y o f the programming model, instructio n set and mpu is p re- sented . for furt her det ails, see the av r32 architectur e manual an d th e avr32 uc technical r efe renc e manual. 9.1 a vr32 architecture avr32 is a n ew, high-performance 32-bit ri sc microprocess or architecture, designed for cost- sensitive em bedd ed applications, with particular emphasis o n low p ower consum pt ion a n d high code d ensity. i n addition, th e instruct ion set architecture has been tune d t o allow a vari ety of microarchitect ures, enabling t he avr32 t o be implemente d as low-, mid - or high-performance processors. avr32 extends the avr fam ily into the worl d of 32 - an d 64-bit applications. t hrough a quantitati v e approach, a larg e set of industr y recognize d benchma rks ha s bee n com- pile d and analyzed to achieve th e best code densit y in it s class . in addition to lowering the memory requirement s, a compact cod e size als o contribute s t o th e c o re ?s low p ower cha rac teris- tics. th e processo r suppor ts by te an d half-word data types withou t penalty in code size and performance. memory load a nd store operations are provided for byte, half-word, word and dou ble wor d data with automa tic sign- or zero extension o f half-word and byt e data. th e c-compile r is closely linked to th e architecture a nd is able to exploit code optimization features, both fo r size and spe ed. i n order t o re duce cod e size to a mini mum, so me instruct ions have mult iple addr essing modes. as an example, instruct ions with immediates ofte n have a compac t format wit h a smaller imme- diate , an d an extended form at with a la rger immediat e. in this w a y, th e compiler is able to use the format giving the smallest code si ze. another feature of th e instructio n set is that freq uently used instruct ions, like a dd, ha ve a com- pact for m at with two o perands as well as an extended format with three operands. the lar ger format increa ses performance, allowing an addition and a d ata move i n th e sa me instructio n in a single cycle . l oad and store inst r uctions have seve ral differ ent formats in orde r to r educe code size and spee d up execution. the register file is o rg anized as sixteen 32-bi t registers and includes th e progra m counter, the link re gister, a nd the st ack pointer. i n addition, regist er r12 is designe d to hol d ret urn values from function ca lls an d is used im plicitly by some instructions. 9 .2 the av r32uc cpu th e avr3 2 uc cpu target s low- an d medium-performanc e a pplications, an d pr ovides an advanced ocd system, no ca ches, and a memory protecti on unit (mpu ). java accelerati on hardware is n o t implemented. avr32 uc p r ovides three memo ry interfaces, one high spe ed bus master fo r instruction fetch, on e hig h spee d bus master fo r data access, an d one high speed bu s slave interf ace allowing other bu s masters to access data rams i nternal to t he cpu. keeping data rams in ternal to the cp u allow s fas t access to th e rams, redu ces latency an d guarantees deterministic timing . also, powe r consumption is reduced by not needing a f ull high speed bus acce ss for memory accesses. a d edicate d da ta ram interf ace is prov ided f or communicatin g with t he inter nal data rams. 32058k avr32-01/12 22 at32uc3a a loc a l bu s interface is p rovided for connecting th e cpu to device-specif ic high-speed systems, such as fl oating-point un its and fast gpio port s. th is local bus ha s t o be enabl ed by writing the loce n bit in the cpucr syst em regist er. the local bus is able to transf e r data betw een the cpu and t he local bus slave in a single clock cycle . the local bus has a de dicat ed memory range allocat ed to it, and data transfers are performed using regula r load and stor e instructions. deta ils on which de vices that ar e mapped into th e local bus spac e is give n in the device-specific ?periphera ls? chapte r of this data sheet. figur e 9- 1 on pag e 2 2 displa ys th e conten ts of avr32uc. figur e 9-1. over view o f the avr32 uc cpu 9.2.1 pipelin e overview avr32 uc is a pipelined processor with three pipelin e stages. there are three pipe line stages, instruction fetch (if), instr uction de code (id) and instruction execut e (ex). the ex sta g e is split in to th ree pa rallel subsections, o ne arithmetic/lo gi c ( al u) section , o n e mu l tiply (mul ) sec- tion a nd on e load/store (l s) section. instructions ar e issued an d complete in o rder. certain operatio ns require severa l clock cycle s to complete, an d in th is case, th e instruction reside s in the id and ex s tages for the required num- ber of clock cycle s . since there is only three pipeline stages , no internal data forwarding i s required, an d no data depende ncies ca n ar ise in th e pipeline. figur e 9- 2 on pag e 23 shows an overview of t he avr32 uc pipelin e stages. avr32 uc cpu pipeline instruction memory controller high speed bus master mpu high speed bus high speed bus ocd system o cd int erface in terr upt co ntroller interfa ce high speed bus slave high speed bus data r am interface high spee d bus master power/ reset control reset interface cpu local bus master cpu local bus data memory controller 32058k avr32-01/12 23 at32uc3a figur e 9-2. th e avr3 2uc pipeline 9.2 .2 avr32a micro architectur e co mpli an ce avr3 2uc implements an avr32a microarchitecture. the avr32a microarchitectur e is tar- g e ted at cost-sensi tiv e, lower- end application s lik e smal ler m icr o c on t rolle rs. this microarchitectur e do es not prov ide dedicated hardwar e registe rs for shadowing o f registe r file registers in int e rrup t contex ts. additionally, it does not provide hardware regis ters f or the return address registers a nd return stat us registers . instead, all th is informatio n is stored on the system st ack. t his save s chi p are a a t t h e expen s e of slo wer interrupt handlin g. upon interrup t initiation, register s r8-r12 are automati cally pushed to th e syst em stack. these registers are pushed regard less o f the priority level of the pend ing interrupt. the return address and status register are also automaticall y pushed to stack. the interrupt handle r can therefore use r8- r12 f reely . up on in terrupt c ompl et i on, the o ld r 8- r 12 re gist er s and status r egis te r are restored, an d executio n continue s a t the return addr ess stor ed popped from stack. t he sta ck is also used to stor e th e stat us register an d return addre ss fo r exceptions and scall. e xec u ti ng t h e rete or rets in struction at the com p letion of an exception or system call will p op th is stat us register an d continue executio n a t the poppe d return address. 9.2.3 jav a support avr32uc does no t provid e jav a hardware acceleration. 9.2 .4 m em or y pr ot ecti on the mpu al lows the user to check al l memory acce sses for privilege violations. if an access i s attempted to an illega l memory address, the access is aborted and an except i on is taken. the mpu in a v r32u c is s p ecif ied i n t he avr32uc technica l referenc e manual. 9.2.5 unaligned referenc e handling avr32uc do e s not support unaligne d accesses, except fo r doubleword accesses. avr3 2 uc is able t o perf orm word-aligned st. d and ld.d . any ot her unaligned memory access will cause an address exce ption. doubleword -sized access es with word-align ed pointers will automatically be performe d as tw o word-size d accesses. if id alu m ul regfile write prefetc h unit decode unit al u unit mu l t i p ly u n it load-store unit ls regfile read 32058k avr32-01/12 24 at32uc3a the fo llowing tabl e shows t he instructions wit h suppor t for unaligne d addresses. all o ther instruct ions requir e alig ne d add r esses. 9.2.6 u nimplemente d in st ructions the following instru ct ions are unimplemented in av r 32uc, and will cause an unimplemented instruction exception if executed: ? all simd inst ructions ? a ll copr ocessor instructions ? ret j, incjosp, popjc, pushjc ? tlbr, tlbs, tlbw ? c ache 9.2. 7 cpu and architecture revision two majo r r evisions of t he avr32 uc cpu curr ently exis t. the device described in thi s datashee t uses cpu revisio n 2. the architecture revision fi eld in th e config0 syste m re gister identifies which architec ture revision is i mplemented in a s p ecific device. avr32uc cpu revision 2 is full y backward-comp atible with revision 1, ie. code compiled fo r revision 1 is binary-compatible with revision 2 cpus. tabl e 9-1. instructions wit h unaligne d refere nce support instr u ction suppor ted align m ent ld.d word st.d word 32058k avr32-01/12 25 at32uc3a 9.3 pr ogramming model 9.3.1 register fil e configuration th e avr32uc register file is s h own below. figur e 9-3. the a vr32uc regist er file 9.3.2 statu s register configuration th e s ta tus registe r (sr) is spli t int o tw o h alfwo rds , o ne uppe r an d one lower , see figu re 9- 4 on page 25 and figur e 9-5 o n pa ge 26. the lower word contains the c, z, n, v and q condition code fla g s and the r, t and l bits, while the upper halfword contains information about the mod e a nd st ate th e pr ocesso r e xec utes in. refer t o the avr32 arc hitecture manual fo r details. figur e 9-4. the status registe r hi gh halfwo rd application bi t 0 supe rv isor bit 31 pc sr int0pc fintpc int1pc sm pc r7 r5 r6 r4 r3 r1 r2 r0 bi t 0 bi t 31 pc sr r12 int0pc fintpc int1pc sm pc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 int0 sp_app sp_sys r12 r11 r9 r10 r8 exce ption nmi int1 int2 int3 lr lr b i t 0 bit 31 pc sr r12 int0pc fintpc int1pc sm pc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bi t 0 bi t 31 pc sr r12 int0pc fintpc int1pc sm pc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bi t 0 bi t 31 pc sr r12 int0pc fintpc int1pc sm pc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bi t 0 bit 31 pc sr r12 int0pc fintpc int1pc sm pc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bi t 0 bi t 31 pc sr r12 int0pc fintpc int1pc sm pc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bi t 0 bi t 31 pc sr r12 int0pc fintpc int1pc sm pc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 31 0 0 0 bit 16 interrupt level 0 mask interrupt level 1 mask interrupt level 3 mask interrupt level 2 mask 1 0 0 0 0 1 1 0 0 0 0 0 0 fe i0m gm m1 - d m0 em i2m dm - m2 lc 1 - initial value bit name i1m mode bi t 0 mode bi t 1 - mode bi t 2 reserved debug state - i3m reserved exception mask global interrupt mask debug state mask 32058k avr32-01/12 26 at32uc3a figur e 9-5. th e status register low h alfword 9.3.3 processor states 9.3.3. 1 norma l risc state the avr32 p rocessor suppor ts seve r a l differen t execution co ntexts as s hown in table 9 -2 on pag e 26. mode chang es can be mad e under soft ware control, or ca n b e caused by extern al interrupt s or exce ptio n p rocessing. a mo de can be interru pt ed by a hi g her priority m ode, but nev er b y one with lowe r priority . nested exceptions ca n be supporte d wit h a minima l software overhead. when running an operating s ystem on the avr32, user pro cesses w ill typically execute in th e ap plication mo de. the progra ms executed in this mod e a re restricted from exec utin g certain in s tr uction s. f urt her mor e , mo st sy st em reg iste rs toge t her w it h t he u pper hal fwor d o f t he sta tus register cannot be accessed. protected memo ry area s ar e also not available. all other operating modes ar e privil ege d an d ar e colle ctively calle d system mode s. th ey have fu ll access to al l priv- ileged and unpri vil eged resources. after a rese t, the proc essor will be in superv isor mode. 9.3.3.2 debug state the avr32 ca n be set in a d ebug state, whic h allo ws implementation of softwar e monito r rou- ti nes tha t ca n rea d ou t an d alt e r syste m info rma t ion fo r use du ring ap plicatio n develo pment . this im plies that all system an d application regist ers, including the status regist ers and program counters, are accessib le in debug state. t he pr ivileg ed instruction s ar e also ava ilable. bit 15 bi t 0 reserved carry zero sign 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - t r bit name initial value 0 0 l q v n z c - overflow saturation - - - lock register remap enable scratch tabl e 9-2. over view of execut ion modes , their priorities an d pr ivilege levels. priority mode securi ty description 1 non maska b le interrupt privileged non maskab le high prior ity interr upt mode 2 e xcep tion p r ivil e ged ex ecute exc eptions 3 in te rr upt 3 pr ivil eged ge neral pur pose interr upt mo de 4 in te rr upt 2 pr ivil eged ge neral pur pose interr upt mo de 5 in te rr upt 1 pr ivil eged ge neral pur pose interr upt mo de 6 in te rr upt 0 pr ivil eged ge neral pur pose interr upt mo de n/a supervisor privileged runs supervisor calls n/a application unprivileged nor mal program exec ution mode 32058k avr32-01/12 27 at32uc3a all in terrupt levels ar e by de fault disabled whe n debu g stat e is entered, but they can individually b e sw itche d o n b y th e monito r r ou tin e by clear ing th e respective m ask bit in t he status register. deb ug state ca n be entere d as described in the avr32 uc tech nical refere nce manual. deb ug state is exited by the retd instruction. 9.3.4 syste m registers the syst e m registers a re placed outsid e of t he virtua l memory space, and are o n ly accessible using the privileged mfsr and mtsr instruct ions. the table below lists th e system register s speci- fied in the avr32 architecture, some of which a re unused in avr32uc. th e programmer is responsible f or maintaining cor rect sequencin g of any ins tructions followin g a mtsr instruction. fo r detail on t he system r egister s, re fe r to the avr32uc technica l referenc e manual. tabl e 9-3. syste m re gi ste rs re g # address name function 0 0 sr status register 1 4 evba exception ve ctor base address 2 8 acba appl icatio n ca ll base address 3 12 c pucr cpu c ontrol r e gister 4 16 ecr exception ca use register 5 20 rsr_sup unused in avr32uc 6 24 rsr_int0 unused in avr32uc 7 28 rsr_int1 unused in avr32uc 8 32 rsr_int2 unused in avr32uc 9 36 rsr_int3 unused in avr32uc 10 40 rsr_ex unused in avr32uc 11 44 rsr_nmi unused in avr32uc 12 48 rsr_ d bg r etur n status r e gister for deb u g mo de 13 52 rar_sup unused in avr32uc 14 56 rar_int0 unused in avr32uc 15 60 rar_int1 unused in avr32uc 16 64 rar_int2 unused in avr32uc 17 68 rar_int3 unused in avr32uc 18 72 rar_ex unused in avr32uc 19 76 rar_nmi unused in avr32uc 20 80 rar_dbg retur n address register fo r deb ug mode 21 84 jecr unused in avr32uc 22 88 josp unused in avr32uc 23 92 java_lv0 un use d i n avr32uc 24 96 java_lv1 un use d i n avr32uc 25 100 java_lv2 unused in avr32uc 32058k avr32-01/12 28 at32uc3a 26 104 java_lv3 unused in avr32uc 27 108 java_lv4 unused in avr32uc 28 112 java_lv5 unused in avr32uc 29 116 java_lv6 unused in avr32uc 30 120 java_lv7 unused in avr32uc 31 124 jtba unused in av r32 uc 32 128 jbcr unused in avr32uc 33-63 132-252 reserved reserved fo r future use 64 256 config0 configurati on regi ster 0 65 260 config1 configurati on regi ster 1 66 264 count cycle co un ter register 67 268 compare compar e register 68 272 tlbehi unused in avr32uc 69 276 tlbelo unused in avr32uc 70 280 ptbr unused i n av r32 uc 71 284 tlbear unused in avr32uc 72 288 mmucr unused in avr32uc 73 292 tlbarlo unused in avr32uc 74 296 tlbarhi unused in avr32uc 75 3 00 p ccnt u n use d in a v r32uc 76 304 pcnt0 unused in avr32uc 77 308 pcnt1 unused in avr32uc 78 3 12 p ccr un us e d i n av r32 uc 79 316 bear bus e rror addr ess register 80 320 mpuar0 m pu address r egister regi on 0 81 324 mpuar1 m pu address r egister regi on 1 82 328 mpuar2 m pu address r egister regi on 2 83 332 mpuar3 m pu address r egister regi on 3 84 336 mpuar4 m pu address r egister regi on 4 85 340 mpuar5 m pu address r egister regi on 5 86 344 mpuar6 m pu address r egister regi on 6 87 348 mpuar7 m pu address r egister regi on 7 88 352 mpupsr0 m pu privilege select r egister regi on 0 89 356 mpupsr1 m pu privilege select r egister regi on 1 90 360 mpupsr2 m pu privilege select r egister regi on 2 91 364 mpupsr3 m pu privilege select r egister regi on 3 tabl e 9-3. system re gister s (co nti nued) re g # address name function 32058k avr32-01/12 29 at32uc3a 9.4 e xceptions and interrupts avr32uc inco rporates a powerful exception handling scheme. th e different exceptio n sources, like ill egal op-co de an d extern al interrupt requests , hav e differen t priority levels, ensuri ng a well- defined behavior when m ultiple except ions ar e received simultaneously. additionally, pending exceptions of a hi gher priority class m a y preempt handling of ongo ing exceptions of a lowe r pri- ority class. when an event occurs , the execution of th e instruct ion stream is h alted, and execut ion contro l is passe d to an event ha ndler a t an ad d ress sp ecifi e d in t able 9-4 on page 32. mo st o f the han- dler s are placed sequ entially in t he code space startin g at t he add ress specif ied by evba, with four bytes between ea ch handler. this gives a mpl e space for a jum p instruction to be placed there, jumping t o the even t rout ine itself. a few critic al handlers have larger spacing between them , allowing the entire even t routin e to be placed directly at the ad d ress spec ified by the evba-re lat i ve o ffs e t g enera t ed by ha rd w are. al l ex t e r nal i nt errupt s o urces have autove ctor ed interrupt service routine (isr) addresses. th is allows t he interrup t controll er to dire ctly specify t he is r ad dres s as an add r ess rela tive t o evba. th e autovecto r of fset h as 14 add r ess bits , gi v- ing an offs et of maximu m 163 8 4 by tes. th e target add r ess of the even t han d ler is ca lcul ate d as (evb a | event_han dl e r_of fs et), no t (evb a + eve n t_handler_of f set) , so evba and exceptio n code segments mu st be se t up appropriat ely. th e sam e m echanisms ar e used to se rvice all dif- ferent types o f events, i n cluding external in terrupt req uests , yielding a uniform event hand ling scheme. an i nt er ru p t con tr olle r does the p riority ha n dling of the exter nal int err upts an d provide s the autovecto r offset to the cpu. 9.4.1 syste m stac k issues event hand ling in avr3 2 uc uses th e syst em st ack pointed to by the syst em stack pointer, sp_sys, for pushing and p opping r8-r12, lr, status register and return address. since even t cod e may be timing- critical, sp _s ys shou ld poi n t t o mem o ry addr esses i n th e iram section, since the timin g of ac cesses to th is memory secti on is both fa st an d deterministic. 92 368 mpupsr4 m pu privilege select r egister regi on 4 93 372 mpupsr5 m pu privilege select r egister regi on 5 94 376 mpupsr6 m pu privilege select r egister regi on 6 95 380 mpupsr7 m pu privilege select r egister regi on 7 96 384 mpucra unused in this versi on of avr32uc 97 388 mpucrb unused in this versi on of avr32uc 98 392 mpubra unused in this versi on of avr32uc 99 396 mpubrb unused in this versi on of avr32uc 100 400 mpuapra m pu access perm ission register a 101 404 mpuaprb m pu access perm ission register b 102 408 mpucr mpu c ontrol register 1 0 3 - 1 91 412-764 r eserv ed r eserve d f o r futur e u se 192-255 768-1020 impl implementation defined tabl e 9-3. system re gister s (co nti nued) re g # address name function 32058k avr32-01/12 30 at32uc3a the us er must als o ma ke sure that th e syste m st ack is larg e enou gh so that an y even t is ab le to push t he required registers to st ack. i f the syst em st ack is full, and an event occurs, th e system will enter an u ndefined state. 9.4.2 exc ep tio n s a n d i nterr up t r equ ests when an ev ent othe r than scall or deb ug reque st is re ceived by th e core , th e following actions ar e performed atomically: 1. the pending event w ill no t be ac cepted if it is mask ed. the i3m, i2m, i1m, i0m, em and g m bi ts in th e statu s re g iste r a re use d t o mask diffe rent ev en ts . not a ll events ca n be masked. a fe w critical events (nmi , unrecoverabl e exception, tlb multiple hit and bu s error) ca n not be m asked . when an even t is accepted , hardware automatically sets the mask bi ts correspondin g to all sources with equa l or lowe r priority. th is inhibi ts accep- tanc e of other events of t he sam e or lowe r priority, except for th e critical events listed above. software ma y choose to clea r some or all o f th ese bits after saving th e neces- sa ry state if other p r iority schemes are desir e d. it is the ev ent source?s responsa bility to ensure tha t their events ar e left pending unt il accepted by th e cpu. 2. whe n a request is accepted, th e status register and progr am counte r of th e current con text is s t ore d to th e syst em sta ck. i f the event is a n int0, in t1, i nt2 or int3, regis- ters r8-r12 and lr are also automatica lly stored to stac k. storing the stat us register ensures that the core is r eturned to the previous execution mode when t he current event handling is c ompleted. when exceptions occur, both the e m a nd g m bi ts ar e set, and t he applicatio n may manually enabl e nested exceptions if desired by clearing the appropriate bit. each exceptio n handler has a d edicate d handler address, and this addre ss uniquel y i dentifies the exceptio n sourc e. 3. th e mod e bits ar e se t t o reflec t th e priority of t he accepted event, and th e correct regis- ter file bank is selected. the address of the event handler, as shown in t a ble 9-4, is loaded into the progra m counter. th e execution of the event handler routine then continues from the effective addr ess calculated. the rete instruct ion signals the en d of th e event. wh en encountered, th e return stat us register an d retu rn addr ess register ar e popped from the syst em st ack and restor ed to t he status reg- iste r an d progra m counter . if the rete instructio n return s from int0 , int1 , int2 or int3, regist ers r8 -r12 and lr a r e also popped from t he system stac k. th e restor ed status register contai ns informatio n allowing th e core to resume operation in the previous execut ion mode. this conclu des th e event handling. 9.4.3 supervis or calls the avr32 instruc t ion set provides a supervisor m ode call inst ruction. the scall inst ruction is designed so tha t privilege d routin es ca n be calle d from an y context. this facilitates sharin g of code betwee n differen t exec ution mo des. the scall mech anism is designe d so th at a minimal execution cycle overhead is e xperienced when performing supervisor routin e calls from time- crit ical even t handlers. the scall i nstr uction beha ves differently dependin g o n whic h mod e it i s ca l led from. t h e b ehav- iour i s detailed in the in st ruction set reference . in orde r to allo w the scall routine t o return to the correct con t ext, a r etur n f rom super visor call ins t ructio n, ret s , is implemented. in t he avr32uc cpu, scall and rets uses t he system stack to store th e return address and t he status register. 9.4.4 deb ug requests th e avr32 architecture defines a dedicated debug mode . when a debug reque st is received by t he core , debug mod e is entered. ent ry into debu g mode can b e masked by the dm bit in the 32058k avr32-01/12 31 at32uc3a stat us register. upon ent ry into debug mode, h ardware sets th e sr[d] bit and jumps t o the debu g exception handler. by default, debug mode executes in th e exceptio n context, but with de dicat ed return addres s registe r and retur n stat us re gister. t hese dedica ted regist ers remove the need for storing thi s data to the s y stem stack , t hereby improving debuggability. the mode bits in the sta t us regist er can f reely be manipulated in debug mode , t o obser ve registers in a l l contex ts, while retaining full privileges. deb ug mo de is exited by executing the retd instruct ion. this returns to th e previous context. 9.4.5 entry points for events severa l different even t handler entr y points exists . in avr32 uc , t he reset addr ess is 0x8000_0000 . th is places the reset addre ss in t he boot flash memo ry area. tlb mi ss exceptio ns and scall have a dedicated space relative t o evb a w here the ir e ven t h an- dler ca n be pl aced . this sp e eds up exec ut io n by removing the need for a j u mp instruction placed at the program addres s jumped to by the event hardware. all other exceptio ns have a d edicated event rout ine ent ry point locat ed relativ e to evba. th e h andler rout ine addr ess ident ifies the exceptio n source directly. avr32uc uses th e i tlb and dtlb protection exceptions t o signal a mp u protection violation. i tlb an d dtlb miss except ions ar e used to signal that an access address did not map to any o f the entri es in t he mpu. t lb multiple hi t exception indicates that an access address did map to multiple tlb entries , signalling an error. all external interrupt r equests have entry point s located at an offset relati ve to e vba. this autovecto r offse t is specified by a n extern al interrup t controller . the programmer must make sur e that non e o f t h e auto vecto r offset s in terfer e with th e placemen t of other code . th e autovec- to r offset has 14 address bits, gi ving an offset of maximu m 163 84 bytes. special considerations should be made wh en loading evba with a po inter. due to security con- siderations, the event handlers shou ld be located in non-writeable flash memory, or optiona lly in a p rivileg ed memory protectio n regi on if an mpu is present. if severa l event s occur on the same instruction , they are handled in a prioritize d way. the priority ordering is presented in ta bl e 9-4 . if events occur on severa l instruct ions at different location s in th e pipeline , t h e eve n ts on th e oldest i n struction are al ways h andle d b efor e a ny eve n ts o n any youn ger instruction, even if the younger instructi on has eve nts of higher priority t han the oldest instruction. an ins tructio n b is younger than an instruct ion a i f i t w a s s en t down the pipeline late r tha n a. t he a ddre sses and p rio rity of simul taneous events a r e show n i n table 9-4. s o me of t he excep- ti on s ar e un us ed i n a v r3 2 uc s i nc e i t ha s n o mm u, coprocessor interfac e or floating-point unit. 32058k avr32-01/12 32 at32uc3a tabl e 9-4. priority an d handle r addres ses fo r events priori ty ha ndler addr e ss name event sou r ce s t o r ed re tur n a d dre ss 1 0x8000_0000 reset externa l input undefined 2 provided by ocd sy stem o cd stop cpu ocd system first non- compl eted instruction 3 e vba+0x00 un recover a bl e exce ption internal p c of offe nding instruction 4 evba+0x04 tlb mu ltiple hit mpu 5 evb a+0 x08 bu s error dat a fetch data bus f irst non-c ompleted instruction 6 evba+0x0c bus error inst ruction fetch data b us firs t non-co mplete d instr u ction 7 evba+0x10 nmi exter nal input first non-c ompleted instruction 8 autovectored interrupt 3 req uest external inp ut fir st no n -com pleted in st ru cti on 9 autovectored interrupt 2 req uest external inp ut fir st no n -com pleted in st ructi on 10 autovectored interrup t 1 request externa l input fir st non-completed instruction 11 autovectored interrup t 0 request externa l input fir st non-completed instruction 12 evba+0x14 instru ction address cpu p c of offe nding instruction 13 e vba+0x50 i t lb miss m pu 14 evba+0x18 itlb protection mpu pc of of fe nding instruction 15 evba+0x1c breakpoint ocd system firs t non-c ompleted instruction 16 evba+0x20 illegal opcode instruction p c of offe nding instruction 17 evba+0x24 unimplem ented instruction instruction pc of of fe nding instruction 18 evba+0x28 privilege violation instruction pc of of fe nding instruction 19 evba+0x2c floating-point unused 20 evba+0x 30 co processor a b se nt unused 21 evba+0x100 super visor call instruction pc(super visor call) +2 22 evba+0x34 data address (read) cpu p c of offe nding instruction 23 evba+0x38 data address (w rite) cpu pc of of fe nding instruction 24 e vba+0x60 d t lb m iss (read) m pu 25 evba+0x70 dtlb miss (w rite) mpu 26 evba+0x3c dtlb protection (read) mpu pc of of fe nding instruction 27 evba+0x40 dtlb protection (w rite) mpu pc of of fe nding instruction 28 evba+0x44 dtlb modifi ed unused 32058k avr32-01/12 33 at32uc3a 10 . memories 10.1 embed ded memories ? intern al high-speed flash ? 51 2 kbytes (at32uc3a0512, at32uc3a1512) ? 25 6 kbytes (at32uc3a0256, at32uc3a1256) ? 12 8 kbytes (at32uc3a1128, at32uc3a2128) - 0 wa it state access at up to 3 3 mhz in wors t ca se conditions - 1 wa it state access at up to 6 6 mhz in wors t ca se conditions - pi pelin ed flash architecture, allowing burs t re ads fr om se quential flash locations, hiding pena lty of 1 wait stat e access - pipeli ned flash architecture typically reduce s the cycl e pe nalty of 1 wa it state operation t o o nl y 15% c ompa re d to 0 w ait s tat e op era tion - 100 0 0 0 write cycles , 15-year data ret e ntion capability - 4 ms page progra mming time , 8 ms chip era se time - sector lock capabili ties, bootl oade r pr otection , securi ty bit - 32 fuse s , eras ed during ch ip erase - use r page for data to be preserve d during chip erase ? intern al high-speed sram, singl e-cy cl e ac ces s a t fu ll sp eed ? 64 kb ytes (at32uc3a0512, at32uc3a0256, at32uc3a1512, at32uc3a1256) ? 32kbytes (at32uc3a1128) 10.2 phy sical memor y map the sys t em bus is impl emented as a bus matrix . all system bus addresses are fixed, and they ar e neve r remapp ed in an y way, no t even in boot. note that avr32 uc cpu uses u nsegmented tr anslation, as described in the avr3 2 architec tu re m a nual. the 3 2 -bi t p h ysical add r ess sp ace is mappe d as follows: tabl e 10-1. at32uc 3a phy sical me mory map device star t address size at32uc3a0512 at32uc3a1512 at32uc3a0256 at32uc3a1256 at32uc3a0128 at32uc3a1128 embedd ed sram 0x0000_0000 64 k byte 6 4 kbyte 64 k byte 64 k byte 32 k byte 32 kbyte embedd ed flash 0x8000_0000 512 kbyte 5 12 kbyte 256 kb yte 2 5 6 k by te 12 8 k by te 12 8 kbyte ebi sram cs0 0xc00 0_00 00 16 m b yte - 16 m byte - 16 m byte - ebi sram cs2 0xc80 0_00 00 16 m b yte - 16 m byte - 16 m byte - ebi sram cs3 0xcc0 0_00 00 16 m b yte - 16 m byte - 16 m byte - eb i sram c s1 /s dra m cs0 0xd0 0 0 _0000 128 m byte - 1 2 8 m by te - 1 2 8 m b yte - usb configuration 0xe000_0000 64 k byte 6 4 kbyte 64 k byte 64 k byte 64 k byte 64 kbyte hsb-p b b r i dge a 0 x fffe_0000 64 kbyte 6 4 k by te 64 kbyte 6 4 k b y te 64 kbyte 64 k b y te hsb-pb b ri dge b 0xffff_0000 64 k byte 6 4 kbyte 64 kbyte 64 kbyte 64 k byte 64 kbyte 32058k avr32-01/12 34 at32uc3a 10.3 b us matrix connections accesses t o unu sed areas returns a n erro r resul t to t he master requestin g such an access. th e bus matr ix has t he seve ral masters a nd slaves. ea ch mast er ha s it s own bu s and its ow n decoder , t hus allowing a different memory mapping per master. the master number in the table be low can be used to index t he hmatri x contro l registers. fo r example, mcfg 0 is associated with th e cpu da ta mast er interface. each sl av e has its own arbiter, thus all o wing a differ ent arbitration p er slave. th e slave number in the ta bl e be lo w ca n b e u se d t o inde x th e hma tri x contro l register s. f or e xample , scfg 3 is associated with the internal sram slave i nterface. tabl e 10-2. flas h memo ry parameters part number f la s h size (flash_pw) numb er of pages ( flash_ p) page size (flash _w) general purpose fuse bits (flash _f) at32uc3a0512 512 kbytes 1024 128 words 32 fuses at32uc3a1512 512 kbytes 1024 128 words 32 fuses at32uc3a0256 256 kbytes 512 128 words 32 fuses at32uc3a1256 256 kbytes 512 128 words 32 fuses at32uc3a1128 128 kbytes 256 128 words 32 fuses at32uc3a0128 128 kbytes 256 128 words 32 fuses tabl e 10-3. high sp eed bu s masters master 0 c pu data master 1 c pu instruction master 2 c pu sab master 3 pdca master 4 mac b dma master 5 u sbb dma tabl e 10-4. high sp eed bu s slaves slav e 0 inter nal flash slav e 1 h sb-pb br idge 0 slav e 2 h sb-pb br idge 1 slav e 3 inter nal sram slav e 4 u sbb dpram slav e 5 ebi 32058k avr32-01/12 35 at32uc3a figur e 10-1. hmatri x master / slave connections cpu data 0 cpu instruction 1 cpu s ab 2 pdca 3 macb 4 internal flash 0 hsb-pb bridg e 0 1 hsb-pb bridg e 1 2 inte rnal sram slave 3 usbb slave 4 ebi 5 usbb dma 5 hmatrix masters hmatrix slaves 32058k avr32-01/12 36 at32uc3a 11. f uses settings the fl ash block contai ns a number of genera l purpose fuses. some o f these fu ses have defined meaning s outside the flash controlle r an d ar e described in th is section. th e gener al purpos e fuses ar e eras e by a jtag chi p e rase. 11.1 f lash general pu r pose fuse register (fgpfrlo) boden: br own out detector enable bodhy st: brown out detector hysteresis bodlevel: brown out detector trigge r level this con t rols the volta ge tr igger level fo r the brown ou t detector. refe r to sectiontabl e 38-6 on pag e 765 for values description. if the bodl evel is set higher than vddcore and enabled b y fuses, the part will be in c onstant reset. to recov e r from this situation, apply an external voltag e on vddcore that is higher than the bod level and disable the bod. tabl e 11-1. fgpfr regi ster description 31 30 29 28 27 26 25 24 gpf31 gpf30 gpf29 boden bodhyst bodlevel[5:4] 23 22 21 20 19 18 17 16 bodlevel[3:0] bootprot epfl 15 14 13 12 11 10 9 8 lo ck[15: 8] 7 6 5 4 3 2 1 0 lock [7: 0] tabl e 11-2. bod en fi eld desc ri pti on boden description 0x0 bo d disabled 0x1 bo d enabl ed, bod reset enabled 0x2 bo d enabl ed, bod reset disabled 0x3 bo d disabled tabl e 11-3. bod en fi eld desc ri pti on bodhyst description 0b th e brow n ou t d e tecto r h y ster esis is disabl ed 1b he br own out detector hysteres is is enabled. 32058k avr32-01/12 37 at32uc3a loc k, epfl, bootprot th ese ar e flash controller fuses an d ar e describe d in t he fl ashc section. 11.2 default fuse value th e devices ar e shipp ed with th e fgpfrlo register value: 0xfc07ffff: ? gpf 31 fuse s e t to 1b. this fus e is use d b y th e pre-progra mm e d u sb boo tl oader. ? gpf 30 fuse s e t to 1b. this fus e is use d b y th e pre-progra mm e d u sb boo tl oader. ? gpf 29 fuse s e t to 1b. this fus e is use d b y th e pre-progra mm e d u sb boo tl oader. ? bo den fuses set to 11b. bod is disa bled. ? bodhyst fuse set to 1b. t he bod hyster esis is enabled. ? bodlevel fuses set to 000000 b . this is the mini mum vo ltage tr igger level fo r bod. ? bootpro t fuse s set t o 011b. the bootload er protected size is 8 ko. ? epf l fuse se t to 1b. extern al privileged fetc h is not locked. ? lock f uses set t o 1111111111111111b. n o regi on locked. se e also th e at32 uc3a bootloade r use r gu ide document. afte r the jtag chip er ase comman d, th e fg pf r lo r egiste r va lu e is 0x f ff fff ff. 32058k avr32-01/12 38 at32uc3a 12. peripherals 12.1 p eripheral ad dress map tabl e 12-1. peripher al address mapping address periphera l name bus 0xe000 0 000 usbb us bb slav e interf ace - usbb hsb 0xfffe0000 usbb us bb configurati on interf ace - usbb pbb 0xfffe1000 hmatrix hma trix co nfiguration interf ace - hm at rix pbb 0xfffe1400 flashc f lash controller - flashc pbb 0xfffe1800 macb ma cb configuration interface - m acb pbb 0xfffe1c00 smc static m emory controller configuratio n interfac e - smc pbb 0xfffe2000 sdramc sdra m control ler configurati on interf ace - sdr a mc pbb 0xffff0000 pdca perip heral dma interface - pdca pba 0xffff0800 intc interrupt cont roller interf ace - intc pba 0xf fff0c 00 pm powe r manager - pm pba 0xf fff0d 00 rtc r eal time cloc k - rtc pba 0xf fff0d 30 wdt w atchdog timer - wdt pba 0xf fff0d 80 eic external interrup t controll er - eic pba 0xffff1000 gpio genera l purpos e io contro ller - gpio pba 0xffff1400 usart0 universa l syn ch r ono us asynchronou s receiver tr ansmitter - usart0 pba 0xffff1800 usart1 universa l syn ch r ono us asynchronou s receiver tr ansmitter - usart1 pba 32058k avr32-01/12 39 at32uc3a 12.2 c pu local bus mapping some of th e registe rs in the gpio modu le ar e mappe d on to the cpu loc a l bu s, i n addition to being ma p ped on th e peripher al bu s. these regi sters can the r efore be re ached both b y accesses on t he peripheral bu s, an d by accesses on the local bus. mapping these regist ers on t he local bu s allows cycle-deterministic togg ling of gpio pins si nce t he cpu a nd gpi o are the o n ly m o dules connec ted to this bus. also, since the local bus runs at cpu speed, one wr it e or read operation can be p e rformed per clock cycle to the local bus- mappe d gpio registers. 0xf fff1c 00 usart2 universa l syn ch r ono us asynchronou s receiver tr ansmitter - usart2 pba 0xffff2000 usart3 universa l syn ch r ono us asynchronou s receiver tr ansmitter - usart3 pba 0xffff2400 spi0 serial peripher al interf ace - spi0 pba 0xffff2800 spi1 serial peripher al interf ace - spi1 pba 0xf fff2c 00 twi two wi re inter f ace - twi pba 0xffff3000 pwm pulse widt h modulation controller - pwm pba 0xffff3400 ssc synchronou s seri al contro ller - ssc pba 0xffff3800 tc timer/counter - tc pba 0xf fff3c 00 adc analog to digita l converte r - adc pba tabl e 12-1. peripher al address mapp ing (continued) address periphera l name bus 32058k avr32-01/12 40 at32uc3a th e followin g gpio register s ar e mappe d o n the local bus: tabl e 12-2. loca l bus mapped gpio registers port register mode local bu s address access 0 outpu t driv er enable register (oder) write 0x4000_0040 write-only set 0x4000_0044 write-only cl ear 0x 4000_ 0 048 wri t e-only toggle 0x4000_004c write-only output va lue reg ister (ovr) write 0x4000_0050 write-only set 0x4000_0054 write-only cl ear 0x 4000_ 0 058 writ e-only toggle 0x4000_005c write-only pin val ue register (pvr) - 0x4000_0060 read-only 1 outpu t driv er enable register (oder) write 0x4000_0140 write-only set 0x4000_0144 write-only cl ear 0x 4000_ 0 148 writ e-only toggle 0x4000_014c write-only output va lue reg ister (ovr) write 0x4000_0150 write-only set 0x4000_0154 write-only cl ear 0x 4000_ 0 158 writ e-only toggle 0x4000_015c write-only pin val ue register (pvr) - 0x4000_0160 read-only 2 outpu t driv er enable register (oder) write 0x4000_0240 write-only set 0x4000_0244 write-only cl ear 0x 4000_ 0 248 writ e-only toggle 0x4000_024c write-only output va lue reg ister (ovr) write 0x4000_0250 write-only set 0x4000_0254 write-only cl ear 0x 4000_ 0 258 writ e-only toggle 0x4000_025c write-only pin val ue register (pvr) - 0x4000_0260 read-only 32058k avr32-01/12 41 at32uc3a 12.3 interrupt r equest signal map th e variou s module s may output interrup t request signals. th ese sig nals are routed t o th e inter- rupt cont r oller (intc), described in a later c hapter. the i nterrupt contr oller supports up to 64 grou ps of interrupt requests. each g roup ca n hav e up to 32 i nterrupt requ est sign als. all interrupt sign als in the same group share t he sa me autov ector ad dress and prio rity level. refer t o the documentation for th e individu al submodules for a descri ption of th e semant ics o f the different interr upt r equ ests. th e interrupt request sig nals ar e co nnected to th e intc as follows. 3 outpu t driv er enable register (oder) write 0x4000_0340 write-only set 0x4000_0344 write-only cl ear 0x 4000_ 0 348 wri t e-only toggle 0x4000_034c write-only output va lue reg ister (ovr) write 0x4000_0350 write-only set 0x4000_0354 write-only cl ear 0x 4000_ 0 358 wri t e-only toggle 0x4000_035c write-only pin val ue register (pvr) - 0x4000_0360 read-only tabl e 12-2. loca l bus mapped gpio registers port register mode local bu s address access tabl e 12-3. interrup t request signa l map group line module signal 0 0 avr 32 uc cpu with optiona l mpu and optional ocd sysblock comp are 1 0 externa l interr upt controller eic 0 1 externa l interr upt controller eic 1 2 externa l interr upt controller eic 2 3 externa l interr upt controller eic 3 4 externa l interr upt controller eic 4 5 externa l interr upt controller eic 5 6 externa l interr upt controller eic 6 7 externa l interr upt controller eic 7 8 rea l time counter rtc 9 po w er mana ger pm 10 frequ ency meter freqm 32058k avr32-01/12 42 at32uc3a 2 0 g eneral pur pose input/output gpio 0 1 g eneral pur pose input/output gpio 1 2 g eneral pur pose input/output gpio 2 3 g eneral pur pose input/output gpio 3 4 g eneral pur pose input/output gpio 4 5 g eneral pur pose input/output gpio 5 6 g eneral pur pose input/output gpio 6 7 g eneral pur pose input/output gpio 7 8 g eneral pur pose input/output gpio 8 9 g eneral pur pose input/output gpio 9 10 general pu r pose input/output gpio 1 0 11 general pu r pose input/output gpio 1 1 12 general pu r pose input/output gpio 1 2 13 general pu r pose input/output gpio 1 3 3 0 pe r iphera l dma c ontroller pdca 0 1 pe r iphera l dma c ontroller pdca 1 2 pe r iphera l dma c ontroller pdca 2 3 pe r iphera l dma c ontroller pdca 3 4 pe r iphera l dma c ontroller pdca 4 5 pe r iphera l dma c ontroller pdca 5 6 pe r iphera l dma c ontroller pdca 6 7 pe r iphera l dma c ontroller pdca 7 8 pe r iphera l dma c ontroller pdca 8 9 pe r iphera l dma c ontroller pdca 9 10 periphera l dma controller p dca 10 11 periphera l dma controller p dca 11 12 periphera l dma controller p dca 12 13 periphera l dma controller p dca 13 14 periphera l dma controller p dca 14 4 0 flash co ntroller flashc 5 0 u ni v ersal syn chron ous/asyn chrono us receiver/transmitter usart0 6 0 u ni v ersal syn chron ous/asyn chrono us receiver/transmitter usart1 7 0 u ni v ersal syn chron ous/asyn chrono us receiver/transmitter usart2 8 0 u ni v ersal syn chron ous/asyn chrono us receiver/transmitter usart3 tabl e 12-3. interrup t request signa l map 32058k avr32-01/12 43 at32uc3a 12.4 clock connections 12.4.1 timer/counters each time r/counte r channe l can independent ly select an internal or exter nal cloc k sour ce fo r its counte r: 12.4.2 usarts each usar t ca n be c onne cted t o an intern ally di vide d clock: 9 0 serial peripheral interface spi0 10 0 serial peripheral interface spi1 11 0 two-w ire interface twi 12 0 pulse wi dth modulation controller pwm 13 0 synchro nous seri al controller ssc 14 0 timer/counter tc0 1 timer/counter tc1 2 timer/counter tc2 15 0 ana log to digital converter adc 16 0 ether net mac macb 17 0 usb 2.0 ot g interface usbb 18 0 s dram controller sdramc 19 0 audio bitstream dac dac tabl e 12-3. interrup t request signa l map tabl e 12-4. timer/counter clock conne ctions source name connection inter nal timer_c l ock1 32 khz oscil l at or timer_clock2 pb a cloc k / 2 timer_clock3 pb a cloc k / 8 timer_clock4 pb a cloc k / 32 timer_clock5 pb a cloc k / 128 external xc0 see secti on 12.7 xc1 xc2 tabl e 12-5. usa rt clock connections usart source name connection 0 internal clk_div p ba cloc k / 8 1 2 3 32058k avr32-01/12 44 at32uc3a 12.4 .3 spis each sp i ca n be connected to an i nternally divided clock: 12.5 nexus ocd a ux por t connections i f the o c d tr ace syste m is enab l ed , t he t rac e s ystem w ill take co ntrol over a number of pins, irre- spectively o f t he pio configuration. two differ ent ocd trace pi n mappings are possible, depending on the configurati o n of the oc d axs register. for details, see the avr32 uc tech- nica l re ferenc e m anu al . 12.6 p dc handshake signals th e pdc an d the periphera l modu les communicate through a set of handshake sign als. the fol- lowing table defines the valid settings for the peripheral identifier (p id) in the pdc peripheral select registe r (psr). tabl e 12-6. spi clock conne ctions spi source name connection 0 internal clk_div p ba cloc k or pb a cloc k / 32 1 tabl e 12-7. nexus ocd aux port connections pin axs=0 axs=1 evti_n pb19 pa08 mdo[5] pb16 p a27 m do [4] pb14 p a26 m do [3] pb13 p a25 m do [2] pb12 p a24 m do [1] pb11 p a23 m do [0] pb10 p a22 evto_n pb20 pb20 mcko pb21 pa21 mseo[1] pb04 pa07 mseo[0] pb17 pa28 tabl e 12-8. pdc han d shake signals pid value periphera l module & d irection 0 adc 1 ssc - rx 2 usar t0 - rx 3 usar t1 - rx 32058k avr32-01/12 45 at32uc3a 12.7 p eripheral multiple xing on i/o lines each gp io line c a n be assigned to one of 3 pe ripheral function s; a, b or c. th e following table define how the i/o lines on the periphera ls a, b a nd c ar e multiplexe d by th e gpio. 4 usar t2 - rx 5 usar t3 - rx 6 twi - rx 7 spi0 - rx 8 spi1 - rx 9 ssc - tx 10 usar t0 - tx 11 usar t1 - tx 12 usar t2 - tx 13 usar t3 - tx 14 twi - tx 15 spi0 - tx 16 spi1 - tx 17 abdac tabl e 12-8. pdc han d shake signals pid value periphera l module & d irection tabl e 12-9. gpio controller fun c tion multiplexing tqfp100 vqfp144 pin g pio pin function a function b function c 19 25 pa00 gpio 0 usart0 - rxd tc - clk0 20 27 pa01 gpio 1 usar t0 - txd tc - clk1 23 30 pa02 gpio 2 usart0 - clk tc - clk2 24 32 pa 03 g pio 3 us art 0 - rts ei m - extint[ 4] d ac - data[0] 25 34 pa04 gpio 4 usar t0 - cts eim - extint[5] dac - datan[0] 26 39 pa05 gpio 5 usart1 - rxd pwm - pwm[4] 27 41 pa06 gpio 6 usar t1 - txd pwm - pwm[5] 28 43 p a07 g pi o 7 usa rt1 - clk pm - g c lk[0] spi 0 - npcs [3] 29 45 pa08 gpio 8 usar t1 - rts spi0 - npcs[1] eim - extint[7] 30 47 pa09 gpio 9 usar t1 - cts spi0 - npcs[2] macb - wol 31 48 pa10 gpio 10 spi0 - npcs[0] eim - extint[6] 33 50 pa11 gpio 11 spi0 - miso usb - usb_id 36 53 pa12 gpio 12 spi0 - mosi usb - usb_vbof 37 54 pa13 gpio 13 spi0 - sck 39 56 pa 14 g pio 14 ssc - tx_frame_sync spi1 - npcs[0] ebi - ncs[0] 40 57 pa15 gpio 15 ssc - tx_clock spi1 - sck ebi - addr[20] 32058k avr32-01/12 46 at32uc3a 41 58 pa 16 gpio 16 ssc - tx_da ta spi1 - mosi eb i - add r [21] 42 60 pa17 gpio 17 ssc - rx_data spi1 - miso ebi - addr[22] 43 62 pa18 gpio 18 ssc - rx_clock spi1 - npcs[1] macb - wol 44 64 pa 19 g pio 19 ssc - rx_frame_sync spi1 - npcs[2] 45 66 pa20 gpio 20 eim - extint[8] spi1 - npcs[3] 51 73 pa21 gpio 21 adc - ad[0] eim - extint[0] usb - usb_id 52 74 pa22 gpio 22 adc - ad[1] eim - extint[1] usb - usb_vbof 53 75 pa23 gpio 23 adc - ad[2] eim - extint[2] dac - data[1] 54 76 pa24 gpio 24 adc - ad[3] eim - extint[3] dac - datan[1] 55 77 pa 25 g pio 25 adc - ad[ 4] ei m - scan [ 0] ebi - ncs[0] 56 78 pa 26 g pio 26 ad c - ad[5] ei m - scan [ 1] ebi - addr [20] 57 79 pa 27 g pio 27 ad c - ad[6] ei m - scan [ 2] ebi - add r [21] 58 80 pa 28 g pio 28 ad c - ad[7] ei m - scan [ 3] ebi - addr [22] 83 122 pa29 gpio 29 twi - sda usart2 - rts 84 123 p a 30 gpio 30 twi - scl u sart2 - c ts 65 88 pb00 gpio 32 mac b - tx_c lk usa r t2 - r ts u sart3 - r ts 66 90 pb01 gpio 33 macb - tx_en usart2 - cts usart3 - cts 70 96 p b02 g pio 34 m acb - txd[ 0] d ac - data[ 0] 71 98 p b03 g pio 35 m acb - txd[ 1] d ac - datan[0] 72 100 pb04 gpio 36 macb - crs usart3 - clk ebi - ncs[3] 73 102 p b05 g pio 37 m acb - rxd [ 0] d ac - data[ 1] 74 104 p b06 g pio 38 m acb - rxd [ 1] dac - datan[1] 75 106 p b07 g pio 39 ma cb - rx_er 76 111 pb08 gpio 40 macb - mdc 77 113 p b09 g pio 41 mac b - m dio 78 115 pb10 gpio 42 macb - txd[2] usart3 - rxd ebi - sdck 81 119 pb11 gpio 43 ma cb - txd[3] usa r t3 - txd ebi - sdc ke 82 121 pb12 gpio 44 macb - tx_er tc - clk0 ebi - ras 87 126 pb13 gpio 45 macb - rxd[2] tc - clk1 ebi - cas 88 127 pb14 gpio 46 ma cb - rxd[ 3] tc - clk2 ebi - sd we 95 134 pb15 gpio 47 macb - rx_dv 96 136 p b16 g pio 48 ma cb - c ol u sb - usb_id ebi - sd a10 98 139 pb17 gpio 49 macb - rx_clk usb - usb_vbof ebi - addr[23] 99 141 pb18 gpio 50 macb - speed adc - trigger pwm - pwm[6] 100 143 pb19 gpio 51 pwm - pwm[0] pm - gclk[0] eim - scan[4] 1 3 pb20 gpio 52 pwm - pwm[1] pm - g c lk[1] eim - scan[5] 2 5 pb21 gpio 53 pwm - pwm[2] pm - g c lk[2] eim - scan[6] 3 6 pb22 gpio 54 pwm - pwm[3] pm - g c lk[3] eim - scan[7] 6 9 pb23 gpio 55 tc - a0 usar t1 - dcd tabl e 12-9. gpio controller fun c tion multiplexing 32058k avr32-01/12 47 at32uc3a 7 11 pb24 gpio 56 tc - b0 usart1 - dsr 8 13 p b25 gpio 57 tc - a1 usa rt1 - d tr 9 14 p b26 gpio 58 tc - b1 u sart1 - ri 10 15 pb27 gpio 59 tc - a2 pwm - pwm[4] 14 19 pb28 gpio 60 tc - b2 pwm - pwm[5] 15 20 pb29 gpio 61 usart2 - rxd pm - gclk[1] ebi - ncs[2] 16 21 pb30 gpio 62 usar t2 - txd pm - gclk[2] ebi - sdcs 17 22 pb31 gpio 63 usart2 - clk pm - gclk[3] ebi - nwait 63 85 pc 00 gpio 64 64 86 pc 01 gpio 65 85 124 pc 02 gpio 66 86 125 pc 03 gpio 67 93 132 pc 04 gpio 68 94 133 pc 05 gpio 69 1 px00 gpio 100 ebi - data [10] usar t0 - rxd 2 px01 gpio 99 ebi - data[9] usart0 - txd 4 px02 gpio 98 ebi - data[8] usart0 - cts 10 px03 gpio 97 ebi - data[7] usart0 - rts 12 px04 gpio 96 ebi - data[6] usart1 - rxd 24 px05 gpio 95 ebi - data[5] usart1 - txd 26 px06 gpio 94 ebi - data[4] usart1 - cts 31 px07 gpio 93 ebi - data[3] usart1 - rts 33 px08 gpio 92 ebi - data[2] usart3 - rxd 35 px09 gpio 91 ebi - data[1] usart3 - txd 38 px10 gpio 90 ebi - data[0] usart2 - rxd 40 px11 gpio 109 ebi - nwe1 usart2 - txd 42 px12 gpio 108 ebi - nwe0 usart2 - cts 44 px13 gpio 107 ebi - nrd u sart 2 - r ts 46 px14 gpio 106 ebi - ncs[1] tc - a0 59 px15 gpio 89 ebi - addr[19] usart3 - rts tc - b0 61 px16 gpio 88 ebi - addr[18] usart3 - cts tc - a1 63 px17 gpio 87 ebi - addr[17] tc - b1 65 px18 gpio 86 ebi - addr[16] tc - a2 67 px19 gpio 85 ebi - addr[15] eim - scan[0] tc - b2 87 px20 gpio 84 ebi - addr[14] eim - scan[1] tc - clk0 89 px21 gpio 83 ebi - addr[13] eim - scan[2] tc - clk1 91 px22 gpio 82 ebi - addr[12] eim - scan[3] tc - clk2 95 px23 gpio 81 ebi - addr[11] eim - scan[4] 97 px24 gpio 80 ebi - addr[10] eim - scan[5] tabl e 12-9. gpio controller fun c tion multiplexing 32058k avr32-01/12 48 at32uc3a 12.8 o scillator pinout the os c illators are not ma pped to the normal a, b or c functions and their muxings are controlle d by regist ers in th e power manage r (pm). please refer t o the power manag er chapter f or more info rmatio n ab out t his. 12.9 usart configuration 99 px25 gpio 79 ebi - addr[9] eim - scan[6] 101 px26 gpio 78 ebi - addr[8] eim - scan[7] 103 px27 gpio 77 ebi - addr[7] spi0 - miso 105 px28 gpio 76 ebi - addr[6] spi0 - mosi 107 px29 gpio 75 ebi - addr[5] spi0 - sck 110 px30 gpio 74 ebi - addr[4] spi0 - npcs[0] 112 px31 gpio 73 ebi - addr[3] spi0 - npcs[1] 114 px32 gpio 72 ebi - addr[2] spi0 - npcs[2] 118 px33 gpio 71 ebi - addr[1] spi0 - npcs[3] 120 px34 gpio 70 ebi - addr[0] spi1 - miso 135 px35 gpio 105 ebi - data[15] spi1 - mosi 137 px36 gpio 104 ebi - data [14] spi1 - sck 140 px37 gpio 103 ebi - data [13] spi1 - npcs[0] 142 px38 gpio 102 ebi - data [12] spi1 - npcs[1] 144 px39 gpio 101 ebi - data [11] spi1 - npcs[2] tabl e 12-9. gpio controller fun c tion multiplexing tabl e 12-10. oscillator pinout tq fp100 p in vqf p144 pin pad oscillato r p in 85 1 24 p c02 xin0 93 1 32 p c04 xin1 63 85 pc00 xin32 86 125 pc03 xout0 94 133 pc05 xout1 64 86 pc01 xout32 tabl e 12-11. usar t supporte d mode spi rs485 iso7816 irda modem manchester encoding usart0 yes no no no no no usart1 yes yes yes yes yes yes usart2 yes no no no no no usart3 yes no no no no no 32058k avr32-01/12 49 at32uc3a 12.10 gpio t he g pi o o pe n drai n f ea t ure (gp i o odm er r egiste r (open drain m o de enable re gister)) is not available fo r this device. 12.11 peripheral overview 12.11.1 extern al bu s i nt erface ? optimized fo r application memory space s upport ? integrat e s tw o external memory controllers: ? s tatic me mo r y contr oller ? s dram cont roller ? op timiz ed ex t ern a l bus : ?16-bit data bus ? 24 - bit a ddres s b u s , u p to 1 6 -m b y te s a ddr essab le ? o pti mize d pin mu lt ip lexing to re duce latencies on external me mories ? 4 sram chip select s , 1sdra m chip s el e ct: ? s tatic memory controller on ncs0 ? s dram cont roller or st atic memory contro ller on ncs1 ? s tatic memory controller on ncs2 ? s tatic memory controller on ncs3 12.11.2 stati c memory controller ? 4 chip s elects available ? 64-mby te address space per chip s elect ? 8-, 16- b it data bus ? word, halfword, byte transfers ? byte write or b y te select lines ? programmabl e setup, pulse and hold tim e f o r re a d sig n a l s pe r ch i p se lect ? programmabl e setup, pulse a n d hold time for wr ite signal s per chip select ? programmabl e data float ti me per ch ip select ? com p lian t w i th lcd m odu le ? extern al wa it req u est ? a u t o mati c switc h t o s low clock m ode ? asynchrono us read in page mode supported: page size ranges fr om 4 to 32 bytes 12.11.3 s dram controller ? numerou s configurations supported ? 2 k, 4k, 8k ro w addres s memory parts ? s dram with tw o or four internal banks ? s dram with 1 6 -bit data path ? programming facilities ? word, half-word, byte access ? automatic page brea k when memory boundary has b e en reached ? m ulti bank ping-pong access ? timing parameters specified by software ? automati c refres h operation, refre sh rate i s programmable ? energy-saving capabilities ? s elf- refresh , p o w e r-down a n d deep power modes supported 32058k avr32-01/12 50 at32uc3a ? s upport s mobile sdra m devices ? erro r detection ? r efr esh error int errupt ? sdram power- up initialization by software ? cas l atency of 1, 2, 3 supported ? au to precharge command n ot used 12.11.4 u sb controller ? usb 2.0 co mplian t, full-/low -speed (f s/ls) and on- the-go (o tg), 12 mbit/s ? 7 pi pes/endpoints ? 960 byte s of e m bedd ed dual-por t ram (dpram) fo r pipes/endpoints ? up to 2 memor y ban ks pe r pipe/endpoin t (not fo r contro l pipe/endpoint) ? flexibl e pipe/endpoint configuratio n an d management with dedica ted dma channels ? on-chip transceiver s including pull-ups 12.11.5 serial peripheral interface ? support s communicatio n with serial externa l devices ? four ch ip selects with extern al decode r support allo w comm unication with up to 15 peripherals ? s erial memories, su ch as datafla sh an d 3-w ir e eep roms ? s erial p eripher als, such as adcs, dacs, l cd controller s, can controller s and sensors ? exter nal co-processors ? maste r or sl a ve s e rial periphera l bu s inte rf ace ? 8 - to 16-bit programmab le data lengt h p er chip select ? p rogrammabl e phas e and polarity per ch ip select ? pro gra mmabl e t ra nsf e r d ela ys betwee n consecu tive t r ansfer s and be tw e en c loc k and da ta per ch ip select ? programmabl e dela y betwee n consecutive transfers ? s ele c t a ble mod e f au lt detect io n ? very fa st transfer s supported ? transfer s wi th baud r ates up to peripheral bu s a (pba ) max frequency ? th e ch i p se le ct li n e ma y b e left act i ve to speed up transfe r s on the sam e device 12.11.6 two-wire interface ? high speed up to 400kbit/s ? compatibi lity with standard two-wire se rial memory ? one, tw o or three bytes fo r slave address ? sequen tial re ad/write operations 12.11.7 usart ? programmabl e baud rate generator ? 5- t o 9-bi t full-duple x synchronous or as y nchr onous se r ial comm unication s ? 1 , 1.5 or 2 stop bits in asynchronous mode or 1 or 2 st op bi ts in synchronou s mode ? parity generation an d error detection ? f raming erro r detection, overrun erro r detection ? msb- or lsb-fi rst ? op ti o nal break gene ration an d detect ion ? by 8 or by-16 over -sampling receiver frequency ? hardw are handshaking rts-cts ? receiver time-out and transmitte r timeguard ? optio nal multi-drop mode with address generation and detection 32058k avr32-01/12 51 at32uc3a ? optio nal manche ster encoding ? rs48 5 with driver contro l signal ? iso7816, t = 0 or t = 1 protocols for inte rfacing with smart cards ? nac k handling , erro r coun ter wi th repetition an d iteration limit ? irda modulation an d demodulation ? commu nication at up to 11 5.2 kbps ? t est modes ? re m ote l oo pback , local loop back , automati c ech o ? spi mode ? mast er or sl ave ? s erial c lo c k pro gramma bl e phase and pola ri ty ? spi se rial clock (sck) frequenc y up t o intern al cloc k frequency pba/4 ? suppor ts connection of two periph eral dma contro ller chan nels (pdc) ? offers buffer transfer without p rocessor intervention 12.11.8 seria l synchronous controller ? provid es serial synchronou s communication links us ed in audi o a n d tel ecom applic ations (with codecs i n ma ster or sl av e mo de s, i2s, tdm bus e s, magnetic card reader, etc.) ? contains an independent re ceive r an d transm itte r and a c o mmon cloc k divider ? offer s a configura b le fram e sync and dat a length ? rece iver and transmitter ca n be progra mmed to star t automaticall y or on dete ction of different event o n the fram e sync signal ? rece iver an d transm itte r include a d a ta signal, a cloc k signal and a frame synch ro nization signal 12.11.9 tim er counter ? thre e 16-bit timer counter channels ? wi de range of function s including: ? frequency measurement ? e vent counting ? i nte rva l measurement ? p ul se generation ? delay timing ? p ulse widt h modulation ? up/down capabilities ? ea c h c ha n nel is u ser -con figurable an d contains: ? three external clock inputs ? five internal cloc k inputs ? two multi-purpos e input/outp ut signals ? tw o gl ob a l reg iste r s t ha t ac t on all three tc channels 12.11.10 pulse widt h modulat ion controller ? 7 chan nels, one 20-bit coun ter per channel ? common clock generator, providi ng thirteen differe nt clocks ? a modul o n coun ter providin g eleven clocks ? two independ ent line ar dividers working on modul o n coun ter outputs ? independent chan nel programming ? i ndependent enab le disable commands ? indepen dent clock ? in d epen dent p eri o d a n d d u t y cyc le, wit h do ubl e bu ff e rizati on ? programmabl e sele ction of the output w avef orm polarity ? p rogrammabl e center or l e ft aligned output waveform 32058k avr32-01/12 52 at32uc3a 12.11.11 ethernet 10/100 mac ? compat ibility with ieee standard 802.3 ? 10 and 1 0 0 mbits pe r se cond data t h ro ughp ut ca pa bili ty ? full - an d half-duplex operations ? mii or rmii interf ace to th e physical layer ? register inte rfa ce to addres s, da ta, statu s and contro l registers ? dma interf ace, operat ing as a m a ster on the memory controller ? interrupt ge neration to signal re ceive and transmit completion ? 28-b yte tran smit and 28-by te rece ive fifos ? au tomatic pad an d crc genera tion on transmitted frames ? addre ss c h e c ki ng logic to rec ogn ize fou r 4 8-bi t a dd r es ses ? suppor t promiscu ous mode wher e all va lid fram es ar e copied to memo ry ? support physical laye r manage ment through mdio in terface contro l o f alarm an d update time/calendar data 12.11.12 audi o bitstream dac ? digital ste reo dac ? over sample d d / a c on v ersi on arch i t e c t ure ? oversampling ra tio fixed 128x ? f ir equalization filter ? dig ital interpolatio n filt er: comb4 ? 3rd order sigm a-delta d/a converters ? digital bi ts tream outputs ? parallel interface ? connected to peripheral dma controller for background transfer wi thout cpu intervention 32058k avr32-01/12 53 at32uc3a 13. pow er manage r (pm) re v: 2.0.0.1 13.1 features ? contro ls integr ated oscillator s and plls ? generates clock s and resets fo r digital logic ? suppo r ts 2 cr ys tal oscillato r s 45 0 kh z-16 mhz ? suppor ts 2 plls 80-2 40 mhz ? suppor ts 32 khz ultra-lo w powe r oscillator ? integrated low-powe r rc oscillator ? on-the fl y frequency change of cp u, hsb, pb a, and pbb clocks ? sl eep m o d e s a llo w s imp l e disabl ing of logic cloc ks, plls, and oscillators ? module-level clock gating throug h maskabl e peripheral clocks ? wake-up fr om internal or ex ternal inte rrupts ? ge ne r i c cloc k s wi t h w ide fr equ e n c y r a ng e p rovid ed ? au tomatic identificat ion of rese t sources ? control s brownout detector (bod), rc oscillator, and bandgap voltag e referenc e through control and c alibratio n registers 13.2 description the powe r manager (pm) contr ols the oscillato rs and plls, and ge nerat es th e clocks and resets in the device. the pm controls two fast crystal o scillators , as we ll as two pll s, whic h can multiply the clock fro m either os cillator to provid e higher frequencies. additionally, a low-power 32 khz oscillator is used to generate the real-time counte r clock for high accura cy real-time measurements. the pm also con t ains a low-power rc oscillator with fast start-up time, which can be used to clock th e digita l logic. the provided clocks are divided into synch r onous and generic clocks. the synchronous clocks are used to clock the mai n digi tal logic in the device, namely th e cpu, and the modules and peripherals connected to t he hs b , pb a , and pbb bu se s. t he gene ri c c lo ck s are asynchronous clocks, which ca n be tun ed pr ecisely withi n a wide frequen cy range, whic h makes them suitable fo r peripherals that require specif ic frequencies, such as time rs and communicati on modules. th e pm also cont ains advanced power-saving features, allowing the user to optimize the power consumptio n for an ap plicatio n. th e synchronous clocks ar e divided into thr ee clock domains, on e for the cpu a n d hsb, o ne fo r modu les on th e pba bus, a nd on e fo r modu les on the pbb bus.the three clocks ca n run at different speeds, so t he user ca n save power by running periph- erals a t a relatively lo w clock, whi le ma in ta inin g a high cpu performance. additionally , the clocks ca n be in depe nde n tly ch ang e d o n-the- fly, wit hou t hal ti ng an y pe rip herals. this en ables th e use r to adjust t he sp eed o f t he cpu and memories t o the dynamic load of t h e application, without disturbing or re-configuring active p eripherals. each module also has a separate clock, enabling t he user to swit ch off the clock for inac tive modules, to save further po w er. additionally, clocks and o sc il lat ors can be automat ic ally sw itched off during idle period s by using the s leep instruction on the cpu. the s y stem will return to normal on occurren ce of interrupts. th e powe r manage r also contains a rese t controller, which co llects all poss ible rese t sources, gener ate s har d a n d soft resets, an d all o ws th e res e t sour ce t o be identifie d b y so ftware. 32058k avr32-01/12 54 at32uc3a 13.3 block diagram figur e 13-1. power manage r bloc k diagram sleep contro ller os cillator and pll contr ol pll0 pll1 synchronous clock generator generic clock gener ator reset controller oscillato r 0 oscillato r 1 rc os cillator star tup counter slow clock sleep instruction power-on detector othe r reset sources resets generic clocks synchronous clocks cpu, hsb, pba, pbb osc/pll control signals rcosc 32 khz os cillator 32 khz clock for rtc interrupts external reset pad calibration registers brown-out detector vol tag e re gul a t or fus es 32058k avr32-01/12 55 at32uc3a 13.4 p roduct dependencies 13.4.1 i/ o li nes the pm provides a number of gene r ic clock out puts, which can be connect ed to out put pins, multi ple x ed w it h gpio lin e s . t he prog ramm er must f irst pro gra m th e gpio c ontroller t o as sig n thes e pins to their peripheral function. i f t he i/ o pins o f t he pm are no t used by the application , t hey can b e us ed fo r oth e r pur poses by th e gpio controller. 13.4 .2 interrupt th e pm interrupt line is co nnected to o ne o f the internal sour ces o f th e interrup t controller. using the pm interrupt requires the interrup t controller t o be programmed first. 13.4 .3 cloc k implementation in at 32 uc3a, the hsb shar es the sour ce clock with the cpu. th i s means that writing to the hsbd iv and hsbse l bits in cksel has no effect. these bits wi l l always read the same as cpud iv and cpusel. 13.5 functional description 13.5.1 s low cl o ck th e slow cl ock is generate d from an intern al rc oscillator which is alw ays running, except in stat ic mode. th e slow cl ock ca n be used for t he main clock in t h e device, as described in ?syn- chronous clocks? on page 5 8. t he slow clock is also used for th e watchd og timer and measuri ng variou s del ays i n th e p owe r m an age r. the rc oscillator has a 3 cy cle s sta r tup time, and i s al ways a vail able w hen t he cp u i s running. the rc oscillator operates at approximately 115 khz, and can be calibrated to a narrow ra nge by the r coscc al fuses. software ca n also c hange rc osc illator calibra tion through the use o f t he rccr register. please see the electrical characterist ics sectio n fo r details. rc oscillator ca n also be used as the rtc clock wh en crystal accuracy is not required. 13.5.2 oscillator 0 a nd 1 op eration t he tw o mai n oscillators ar e designe d to be used with a n e xter nal 450 khz to 16 mhz crystal an d two biasin g capacitors , as sh own in figur e 13-2 . oscillator 0 can be us ed for the main clock in t he device , as describ ed in ?synchronous clocks ? on pag e 58. both oscillators can b e u sed as sour ce for th e gene ric clocks, as describe d in ?gene ric clocks ? on pag e 61. the oscillator s are disabled b y default after reset. w h en the oscillators ar e disa bled, the xi n and xout pins can be used a s genera l purp o se i/os . w he n t h e os cilla tors are configured to us e an ext ernal clock, the clock must be applied to t he xi n pin while t he xout pin can be used as a general p ur po s e i/ o. the os cillators can be enab l ed by writing to the o s cne n bits in m cctrl . operation mode (external cloc k or cr ysta l) is chosen b y writing to the mod e field in oscctrln. oscillator s are automati cally switched off in cert ain sleep mode s to reduce power consumption, as describ ed in section 13.5.7 o n pag e 60. after a hard reset, or wh en wa king up from a sleep mode that di sabled the o s cillators, the oscil- lators may need a certain amoun t of time to stabilize on the corr ec t frequency. th is start-up time can be set in th e oscctrln register. 32058k avr32-01/12 56 at32uc3a the pm mask s the osc illator outputs during the start- up time, to ensure t hat no unstable clocks propagate to the digita l lo gic. th e oscnrdy bi ts in poscsr a r e auto mati cally s e t a n d clea red according to the st atus of the oscillators . a zero to one transition on these bit s can also be con- figured to generate an interrupt, as descri b ed in ?interrupt enable/disable/mask/status/clear? on pag e 76. figur e 13-2. oscillator connections 13.5.3 32 kh z oscillat or operation the 3 2 kh z oscillat or op erates a s described for o s cillator 0 and 1 above. the 32 kh z oscillator is us ed as source cloc k for t he real-tim e counter. th e oscillator is disa bled by default , bu t can be enabled by writin g osc32e n in oscctrl32. the oscillator i s an ultra-lo w po wer design and remains enabled in all s leep modes ex cept static mode. while the 3 2 khz oscillator is dis able d, th e xin32 and xout32 pi ns are available as general purpose i/os. wh en the oscillator is co nfigured to work with an external clock (mode field i n oscctrl3 2 register ), th e exte rnal cloc k must be connected to xin32 while th e xout32 pin can be used as a g eneral purpose i/o. the startup time of the 3 2 khz oscillator ca n be set in the oscctrl32, after which osc32rd y in poscsr is s et. an interrupt ca n be generate d on a zero to one transitio n of osc32rdy. as a cryst al oscillato r usua lly requir es a very long startup time (up to 1 sec ond) , th e 32 khz oscillator w ill keep running across rese ts, except power-on-reset. 13.5.4 pll o peration the de v ice contai ns tw o pll s, pll 0 a n d pll 1 . t he s e a r e dis abl ed b y de fa ult, b ut can be enabled to provide high frequen cy sour ce clocks for synchronous or gene ric cloc ks. the plls can take either o s cillator 0 or 1 as reference clock. t he pll output is divided by a multiplicatio n factor , and th e pll compar es the re sulting clock to the refere nce clock. th e pll will adjus t its outp ut frequency until the two co mpared clocks are equal, thus lo ck ing the outp ut frequency to a mu ltip le of th e r efer e nce cl ock fre que ncy. the vol t age con t rolled osci l la tor inside the pl l can generate frequencies from 80 to 240 m hz. to ma ke the pl l output frequencie s u nd e r 8 0 mh z th e otp [1 ] bitfield co uld be set. this will xin xout c 2 c 1 32058k avr32-01/12 57 at32uc3a divide th e outpu t of the pll by two an d b r ing the clo ck in rang e o f th e ma x frequency o f the cpu. when t he pl l is switched on, or when changing th e clock source or multiplication factor for the pll, the pll is unlock ed a nd the outpu t freque ncy is undefined. t he pll clock for th e digital lo gic is automatically masked when th e pll is u nlocked, to preven t connected digita l logi c from receivin g a to o high frequency and thus become unstable. figur e 13-3. pl l wit h contro l logic an d filters 13.5.4 .1 enabling the pll plln is enabled by wr iting the pllen bit in th e plln register. pllos c select s osc illator 0 or 1 a s clo ck source. the pllmul an d plld iv bitfields must be written with t he multiplication and division factors, respectively, creating t he voltag e controlle d ocillator frequency f vco and t he pll frequency f pll : f vco = (pl lmul+1)/(plldiv ) ? f osc if plldiv > 0. f vco = 2* (pllmul+1 ) ? f osc if plldiv = 0. if pllopt[1] field is s et to 0: f pll = f vco. if pllopt[1] field is s et to 1: f pll = f vco / 2 . th e plln:pllopt fiel d should be se t to proper values according to the pl l operating fre- quency. t he pllopt fi eld ca n als o be se t to divide th e outpu t frequ ency o f the pl ls by 2. th e lo ck signal for ea ch pll is availa ble as a l ockn flag in poscsr. an in terrup t can be gen- erate d o n a 0 to 1 transitio n o f th ese bits. phase detector output d i vi d er 0 1 osc0 clock osc1 clock pllo sc pllo pt pllm u l lock bit mask pll clock i n p u t d ivider plld iv 1 /2 pllo pt[1] 0 1 v c o f vco f pll lock detector 32058k avr32-01/12 58 at32uc3a 13.5.5 synchronous clocks the slow clock (default), o scillato r 0, or pll0 provide the source for the main clock, which is the comm on root for th e synchr onous cloc ks for th e cpu/hsb, pba, an d pbb mo dules. the main clock is d i vided by an 8-bit prescaler, and ea ch of these four synchronous clocks can run from an y ta ppin g of t hi s p resc a ler, or th e undivi ded mai n clock, a s l ong a s f cpu f pba,b, . the synchro- no us cloc k source ca n be change d on-the fly, responding to vary ing load in t h e application. the clock do m ains can be shut d own in sleep mode, as described in ?sleep modes? on page 60 . additionally , the cloc ks for eac h module in t he four dom ains can be individ ually masked, to avoid pow er consu mptio n i n inactive modules. figur e 13-4. synchrono us cloc k generation 13.5.5.1 selecting pl l or oscillator fo r the main clock th e comm on ma in clock ca n be conne cted to the slow clock, oscillator 0, or pll0. by default, the main clock w ill be connected to the s low clo ck. the user can connect the main cloc k to oscil- lator 0 o r pll0 by w riting the mcsel bitfield in the main cloc k control register (m cctrl ). this must only b e done after that unit has been enabled, otherwise a deadlock will occur. car e should also be taken that the new frequency of the synchronous clocks does not exce e d the max im um frequen cy fo r e ac h cl ock domai n. 13.5.5.2 selectin g synchronou s clock division ratio the ma in clock feed s a n 8-bi t prescaler, which ca n be used t o generate th e synchronou s clocks. by default, the synchronous clocks run on th e undivided main clock. the user can select a pres- mask prescaler osc0 clock pll0 clock mcsel 0 1 cpusel cpudiv main clock sleep controller cpuma sk cpu cl ocks hsb cl ocks pbac l oc ks pbb c locks sleep instruction slow clock 32058k avr32-01/12 59 at32uc3a caler division fo r t he cpu clock by writing c ksel:cpudi v to 1 and cpusel to t he prescaling value, resulting in a cpu cloc k frequency: f cpu = f main / 2 (cpusel+1) similarly, the clock for the pba, and p bb can be divided by writin g their respective bitfields. to ensu re correct operation , frequen cies must be sel ect ed so that f cpu f pba,b . also , frequencies must never exceed the specifie d max imum frequency fo r ea ch clock domain. cksel can be written without ha l ting or disabling peri pheral modules. writing cksel allows a new clock se tting to be written to a ll synchronou s clo c ks at th e same time. it i s possible to keep one or more clocks un ch anged by writing the same va lue a before to the xxxd iv and xxxsel bit- fields. t his way, it is possible to e. g. sc ale cpu and h sb s peed a ccord ing t o th e re quired performance, whi l e keeping the pba and pbb frequency constant. 13.5.5 .3 clock read y flag there is a slight dela y fro m c ks e l is w ritte n an d th e ne w cloc k settin g become s e ffec tive. dur- ing this interval, the clock ready ( c krdy) flag in is r will read a s 0. if ier:ckrd y is written t o 1, th e po wer ma nag e r in terr upt can be tr igge re d whe n t he new clock s ettin g is effective. cksel must not be re-writte n while ckrdy is 0, or th e system may b eco me unstab le or hang. 13.5.6 pe riph eral cloc k ma sking by default, th e clock for all modules are enabled, regardless of which modules are actua lly being used. it is possibl e to dis able the clock for a m o dule in th e cpu , hsb, pba , or pbb cl ock dom ain by writing t he corresponding bit in the cloc k m a sk re giste r (cp u/h sb /pba/pb b) to 0. when a module i s not clo c ked, it will ce ase operation, and its re gisters cannot be read or written. th e module ca n b e re-enable d late r by writing th e correspondin g ma sk bit t o 1. a modul e ma y be conn ected to severa l clock dom ains, in which case it will have several mask bits. ta ble 13-5 cont ains a list of implemente d maskab le clocks. 13.5.6.1 cautionar y note note that clocks s h ould only be switched off if it i s c e rta i n th at th e modul e wil l n ot be u se d. switching off the clock for the internal ram will cause a p r oblem if the stack is mapped there. swit ching off the clock to the power manager (pm), which contains the mask registers, o r the corres ponding pbx bridge, will make i t imposs ible to write the mask registers again. in this case , t hey can only be re-enabl ed by a system reset. 13.5.6.2 m ask r ea dy fl ag du e to synchronization in the clo ck generator , there is a s light delay from a m ask reg ister is writ- te n until the new mask sett ing goes into effect. when cl ea ring mask bits, this delay can usually be igno r ed. however, when sett ing mask bits, th e regist ers in t he co rresponding module must not b e written until the clock has actually be re-enabled. t he status flag mskrdy in is r pro- vide s th e re quired mask status info rmation. when wr iting either mask register with any value, this bit is cleare d. the bit is set when the clocks have b een enabled an d disabled according to th e ne w mas k setting . option ally, the powe r manager interrupt can be enable d by writing the mskrdy bi t in ier. 32058k avr32-01/12 60 at32uc3a 13.5.7 sleep mo des in no rmal o peration , all clock dom a ins are active , allowin g soft ware ex ec ut io n a n d pe riph era l operation. when th e cpu is idle, it is possible to swit ch off th e cpu clock an d option ally other clock domains t o save power. this is ac tivate d by the sleep ins t ruction, wh ich take s the sleep mo de ind ex number as argument. 13.5.7.1 entering and exit ing sleep modes the s l eep inst ruction w i l l ha lt t he cpu and al l modules belonging to t he stopped clock domains. the modu l e s will be ha l t ed r egard less o f t h e bit settings of the ma sk registers. oscillators and plls can also b e switched off to save power. so me of these modules have a rel- atively l o ng start-up time, an d are only swi tc hed o f f w he n v ery l o w po we r con sum pti o n i s required. th e cpu and affected mod ules ar e restart ed when th e slee p mode is exi ted. this occurs whe n an interrup t triggers. note that even if an in terrupt is e nab led in sle ep mode, it ma y no t trigger if t he sour ce module is n o t clocked. 13.5.7.2 su ppo rted sle ep mo des th e f o llowin g slee p mo des ar e sup por ted. th ese a r e det ailed in tabl e 13-1. ?idle: the cpu is s topped , the rest o f the chip is o perating. wake- up sour ces are any in terrupt. ?frozen: the cpu a nd hsb modu les are stopped, peripheral s ar e operating. wake-u p sources ar e an y interrupt from pb mo dules. ?standby: all sync hronous clocks are stopped, b u t oscillators and plls are running, allowin g qu ick wake-up to normal mode. wake-up so urces ar e rtc or exter nal interrupt (eic). ?stop: as standby, but oscilla t or 0 a nd 1, and the plls are sto p ped. 32 khz (if enabled) an d rc oscillators and r t c/wdt still operate. wake- up sources are rt c, external interrupt (eic), or extern al reset pin. ?deeps top : all sy nchronou s clocks , oscill ator 0 an d 1 a n d pll 0 a n d 1 ar e st op ped. 32 khz oscillator ca n run if enabled. rc oscillator st ill operates. bandgap volt age referenc e and bod is turne d off. wake-u p sources are rtc, external interrupt (eic) o r extern al reset pin. ?static: all o scil lators, including 32 khz and rc oscillator are stopped . bandgap voltage refer- ence bod detector is turne d off. wake-u p sources ar e extern al interrupt (eic) in asynch ronous mo de only or external reset pin. tabl e 13-1. slee p modes index sleep mode cpu hsb pba,b gclk osc0,1 pll0,1 osc32 rcosc bod & b and g ap voltage regulator 0 idle stop run run run run run on fu ll power 1 frozen stop stop run run run run on fu ll power 2 s t a n d by stop stop stop run run run on full power 3 stop stop stop stop stop run run on lo w power 4 deepstop stop st op st op stop r un r un off lo w po wer 5 static stop stop stop stop stop stop off lo w power 32058k avr32-01/12 61 at32uc3a th e p owe r leve l of t he inter nal volta ge regulator is als o adj uste d accor din g to the slee p mode to reduce th e internal regulator power consumption. 13.5.7.3 precautions whe n enteri ng slee p mode mo dules commun icating with exter nal circui ts shou ld normally be disable d before entering a sleep mode that w ill stop the mo dule operation. this prevents erra tic behavior when entering or exiting sleep mo de . please refer to th e relevant module d ocumentation f or recommended actions. communication between t he synchron ous clock doma ins is disturbe d when enteri ng an d exiting sleep modes. this means that bus t ransactio ns ar e no t allowe d between clock domains affected by the sleep mode. the s ystem may hang if th e bus clocks are st opped in the middl e of a bu s transaction. th e cpu is automati cally stopp ed in a safe state to ensur e that all cpu bu s operations are com- plete when t he sle ep mode g oes into effect. th us, wh en entering idle mode, no f urther action is ne cess ary. when entering a sleep mod e (except id le mode), all hsb mast ers must be st opped before entering the sleep mode. also, if ther e is a ch ance that an y pb write operation s ar e incomplete, t he cpu shou ld perfor m a read operation from an y register on t he pb bu s before executing the sleep instru ct ion. this will stall the cpu while waiting for any pen ding pb operations t o complete. 13.5.7.4 wak e up th e usb can be used to wake up th e par t fr om sleep modes throu gh regist er pm_awen o f the power manager. 13.5.8 generic clocks timers, communication modules, and other modules connected to external circuitry may require specif ic clock frequencies to operat e correctly. th e po wer manager contains an implementation define d number of generic cloc ks tha t ca n provid e a wide rang e of accurate cloc k frequencies. each generic clock module runs from either o scilla tor 0 or 1, or pll0 or 1 . t he selected s ource can op t ionally be d ivi ded by an y ev en intege r up to 5 12. each clock can be indepe ndently enabled and disabled, and is al so automati cally disabl ed along wi th peripheral clocks by the slee p controller. 32058k avr32-01/12 62 at32uc3a figur e 13-5. gene ric cloc k generation 13.5.8.1 enablin g a gener ic clock a gene r ic clock is enabled by writing the cen bit in gcctrl to 1. each ge neric clock can use either oscillator 0 or 1 o r pll 0 o r 1 a s sourc e, a s s e le ct ed by the pllsel and oscs el bits. th e source clock c a n optionally be divide d by writin g diven to 1 a n d th e division factor to div, resultin g in th e output frequency: f gclk = f src / (2*(div+1)) 13.5.8.2 disab ling a generi c clock the g e neric clock can b e d i sabled by wri tin g cen t o 0 or ent ering a sleep mode t hat disables the pb c locks. i n eithe r case , t he gene ri c c loc k wil l be switc hed off on the fir s t falling edge after the disabling event, to ens u re that no glitches occur. if ce n is written to 0, the bit will still read a s 1 until the ne xt falling edge o ccu rs, and the cloc k is actually sw itched off. when writing cen to 0 , t he othe r bits in gcctrl shou ld not be chang ed un til cen read s as 0 , to avoi d glitches on the gener ic cl oc k. whe n th e cloc k is disabled , bot h t he pr escale r a n d outp ut a re rese t. 13.5.8.3 changing clock frequency when changing gener ic clock frequency by writ ing gcctrl , t he cloc k shoul d be switched of f by t he procedur e above, befor e bein g re-enabl ed with t he new cloc k sour ce o r division setting. this preven ts glit ches during th e transition. divider 0 1 o sc0 clock pl l0 clock pllsel oscsel o sc1 clock pll1 clock generi c clock div 0 1 diven mask cen sleep controller 32058k avr32-01/12 63 at32uc3a 13.5.8.4 gene ric cl oc k implementati on in at32u c3a, there are 6 generi c clocks. these a r e allocate d to different func tions as sh own in ta ble 13-2. 13.5.9 divi ded pb clocks the c l ock gener at or i n t he p ower mana ger p rovides divided pba a n d pbb cloc ks for use by perip herals that require a prescale d pbx clock. this is described in th e documentation for the relevant modules. the divided clocks are not directly ma sk able, but are stopped in sleep modes where the pbx clocks a r e stopped. 13.5.10 deb ug operation duri ng a debug session , th e use r may need t o ha lt th e syste m to inspec t mem ory and cpu r eg- iste rs. the clocks normally keep running during this debug oper a t ion, but some peripherals may require the cloc ks t o b e stopped, e.g. to prevent time r overflow, wh ich would caus e th e program to fai l . for th i s reason, peripherals on th e pba and pb b buses may us e ?debug qualifie d? pbx clocks. th is is describe d in t he documentatio n fo r the relevant modu les. the divid ed pbx clocks ar e alwa ys debu g qualified clocks. debug qualified pb cloc ks ar e st opped during debug operation. the debug syst em can option- ally ke e p these clocks running during the debug operation. this is desc r ibed in the doc ume ntat ion fo r t h e on -c hip deb ug sys t em. 13.5.11 res et controller the reset controller collects the various rese t sources in the syste m and generates hard and soft rese ts for th e digi tal logic. the device contains a power- on detector, which ke eps the system reset until power is stable. thi s elim ina te s t h e need for externa l reset circuitr y t o g uarante e stabl e ope rati on whe n po wer ing up th e device. tabl e 13-2. generi c clock alloca ti on clock number function 0 gclk 0 pin 1 gclk 1 pin 2 gclk 2 pin 3 gclk 3 pin 4 usbb 5 abdac 32058k avr32-01/12 64 at32uc3a it is also possible to reset the device by asserting the reset_n pin. this pin has an internal pul- lup, and does no t need to be driven externa lly when negated. tabl e 13-4 lists th ese an d oth er reset sources suppor te d by the re set controller. figur e 13-6. reset controlle r block diagram in addi t ion t o the list e d re se t ty pe s, the jtag ca n kee p pa rts o f th e de vic e s tat ica lly reset through t he jtag reset register. see jtag documentation fo r details. tabl e 13-3. reset descrip tion when a reset occurs , so me part s o f the chip ar e no t necessar ily reset, depending on th e reset source. only the power on reset (po r ) will force a reset of the whole chip. rese t source description power-o n reset supply voltage belo w the power-on rese t detector threshold voltage extern al reset r eset_n pin asserted browno ut reset supply voltage belo w the brown out re set dete ctor threshold voltage cpu error caused by an il legal cpu acce ss to externa l memory while i n s u perv i s or mo de watch dog timer see watchdo g time r documentation. ocd see on-chi p debug documentation jt a g reset controller reset_n p ow er-o n detector ocd w atchdog reset rc_rcause cpu, hsb , pba, pbb oc d, rtc/ w dt clo c k generato browno ut detector 32058k avr32-01/12 65 at32uc3a ta ble 13-4 lists part s o f the device that ar e reset, dependin g on the reset source. th e cause o f the last reset can be r e ad fr om th e rcause register. th is register contains o ne bit fo r e ach r eset s ou r ce, an d can b e rea d durin g th e boot seque nc e of a n applic atio n t o de term ine the prope r actio n t o be taken. 13.5.11.1 power-on detector the power-on de t ect or mon ito rs th e v ddcor e suppl y pi n and g e ne rates a r ese t when t he devic e i s pow ered on. t he rese t is active u ntil the sup p ly voltag e fro m the linear regula tor is above the power-on threshold lev e l. the reset will be re -activated if the vo ltage drops below th e power-on threshol d level. see electrical characteristics fo r paramet ric details. 13.5.11.2 brown-out detector the brown-out detector (bod) m o nitors the vddcore supply pin and compares the suppl y voltage to th e brown-ou t detection leve l, as se t in bod:level. th e bod is di sabled by d efault, bu t ca n be enabled either by so ftware or by flash fuses. th e brown-ou t detecto r can either gen- er ate an int e rrupt o r a rese t wh en the su pply voltag e is b elo w th e br own-o ut detec tio n le vel. i n an y case, th e bod outpu t is availabl e in bit poscr: bodet bit. not e tha t any c hange t o t he bod: level fi eld o f t he b od r eg ist e r sh ould b e done with th e bo d deactivat e d t o avoid spuri ous rese t o r interru pt. se e electrica l char acter istic s f or p arametric de t ai ls. tabl e 13-4. effect of th e different rese t events power-on reset exte rnal reset watchdog res et bod reset cpu error reset ocd reset cpu/hsb/pba/pbb (excluding powe r manager) y y y y y y 3 2 khz oscillator y n n n n n rtc control register y n n n n n gplp registers y n n n n n watchd og control register y y n y y y vol ta g e calibratio n regist er y n n n n n rc oscillator calibration register y n n n n n bod control register y y n n n n bandgap control register y y n n n n clock control registers y y y y y y osc0/osc1 and control registers y y y y y y pll0/pl l1 and control registers y y y y y y ocd system a nd ocd registers y y n y y n 32058k avr32-01/12 66 at32uc3a 13.5.11.3 externa l reset the ex t ernal reset detector moni tors the state of the reset_n pi n. by default, a low level on this pin will generate a re se t. 13.5.12 calibra tion registers th e powe r manager contro ls the calibr ation of the rc o scillator , volta ge regulato r, bandgap voltag e refere nce through severa l calibration s registers. th ose calibrati on registers ar e loaded after a powe r on reset with default va lues stor ed in fac- tory-programme d flas h fuses. although it is not rec omm en d ed t o ove rri de def aul t factory settings, it i s still possible to overrid e these default values by writing to those register s. to preven t unexpect ed writes d ue to software bugs, writ e access to these register s is protected by a ?k ey?. first, a write to the registe r must be made wi t h the f i el d ?key? equa l to 0x55 then a second write mus t be issued with the ? k ey? field equ al t o 0xaa 13.6 u ser interface offset register name access reset state 0x0000 main clock c ontrol mc ctrl r ead/wr ite 0x00000 0 00 0x0004 clock select cksel read/write 0x00000000 0x0008 cpu mask cpumask read/write 0x00000003 0x000c hsb mask hsbmask read/write 0x0000007f 0x0010 pba mask pbamask read/w r ite 0 x0000ffff 0x0014 pbb mask pbbmask read/write 0x0000003f 0 x0018 - 0 x00 1c r eser v ed 0x0020 pll0 control pll0 read/write 0x00000000 0x0024 pll1 control pll1 read/write 0x00000000 0x0028 oscillator 0 control register oscctrl0 read/write 0x00000000 0x002c oscillator 1 control register oscctrl1 read/write 0x00000000 0 x0030 osci lla t or 32 c ontr ol re gist er os cc trl32 read /wr ite 0x000 00000 0x0034 reserved 0x0038 reserved 0x003c reserved 0x0040 pm interrupt enable register ier write only 0x00000000 0x0044 pm interrupt disable register idr write only 0x00000000 0x0048 pm interrupt mask register imr read only 0x00000000 0x004c pm interrupt status register isr read only 0x00000000 0x0050 pm interrupt clear register icr write only 0x00000000 0x0054 power and oscillators status register poscsr read/write 0x00000000 0 x0058 - 0 x00 5c r eser v ed 32058k avr32-01/12 67 at32uc3a 0x0060 generic clock control gcctrl read/write 0x00000000 0x0064 - 0x 00bc rese rv ed 0 x00 c0 rc oscil lato r calib ra tion r egister rccr read/w rite f actor y settings 0x00c4 bandgap calibration register bgcr read/write factory settings 0x00c8 linear regulator calibration register vregcr read/write factory settings 0x00cc reserved 0x00d0 bod level register bod read/write bod fuses in flash 0x00d4 - 0x013c reserved 0 x0140 re set cau se r eg ist er r c a u se read only la test re set sour ce 0 x0144 - 0 x01fc r ese rv ed 0x0200 general purpose low-power register 0 gplp0 read/write 0x00000000 0x0204 general purpose low-power register 1 gplp1 read/write 0x00000000 32058k avr32-01/12 68 at32uc3a 13.6.1 main clock control name: mcctrl acces s type: read/write ? mcsel: main clo c k select 0: th e slow cl oc k is the source fo r the main clock 1: oscil lator 0 is source fo r the main clock 2: p l l0 is source fo r the main clo c k 3: rese rv ed ? osc0en : oscillator 0 enable 0: oscil lator 0 is disabled 1: oscil l ator 0 i s enabled ? osc1en : oscillator 1 enable 0: oscil lator 1is disabled 1: oscil lator 1is enabled 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - osc1en osc0en mcsel 32058k avr32-01/12 69 at32uc3a 13.6.2 cloc k select name: cksel acces s type: read/write ? pbbdiv, pbbsel: pbb div ision and cloc k select pbbdiv = 0: pb b cloc k equals main clock. pbbdiv = 1: pb b cloc k equals main clock divided by 2 (pbbsel+1) . ? pbadiv , pb asel: pb a division and clock select pbadiv = 0: pb a cloc k equals main clock. pbadiv = 1: pb a cloc k equals main clock divided by 2 (pbasel+1) . ? hsbdiv, hsbsel: hsb div ision and cloc k select f or t h e at 3 2uc3 a, hsbdiv alwa y s equ a l s c pud iv, an d hsbsel alw a y s eq ua ls cpuse l , as t he hsb clo c k i s a lwa ys equa l to the cpu clo ck. ? cpudiv, cpusel: cpu div ision and cloc k select c pu d iv = 0: cpu c l oc k eq uals m ai n cl o c k. cpudiv = 1: cpu cl oc k eq uals main cloc k divided by 2 (cpusel+ 1) . note that if xxxdi v is written to 0, xxxsel shoul d als o be written to 0 to ensur e correct operation. also note that writing thi s register clea rs poscsr:ckrdy. the registe r mu st not be re-written unt il ckrdy go es high. 31 30 29 28 27 26 25 24 pbbdiv - - - - pbbsel 23 22 21 20 19 18 17 16 pbadiv - - - - pbasel 15 14 13 12 11 10 9 8 hsbdiv - - - - hsbsel 7 6 5 4 3 2 1 0 cpudiv - - - - cpusel 32058k avr32-01/12 70 at32uc3a 13.6.3 cloc k mask name: cpu/hsb/pba/pbbmask acces s type: read/write ? mask: clo c k mask if bit n is c leared , the clock fo r modul e n is stopp ed. if b it n is set, the clock fo r modul e n is enabl ed accordi ng to the current powe r mode . the nu mber of implemente d bits in ea ch ma sk register , as we ll as wh ich modul e cloc k is controlled by ea ch bit, is show n in tab le 13-5. 31 30 29 28 27 26 25 24 mask[31:24] 23 22 21 20 19 18 17 16 mask[23:16] 15 14 13 12 11 10 9 8 mask[15:8] 7 6 5 4 3 2 1 0 mask[7:0] tabl e 13-5. maskabl e mo dule cl oc ks i n a t32 uc3a. bit cpumask hsbmask pbamask pbbmask 0 - flashc intc hmatrix 1 ocd pba b ridge gpio usbb 2 - pbb b ridge pdca flashc 3 - usbb pm/rtc/eic macb 4 - macb adc smc 5 - pdca spi0 sdramc 6 - e bi sp i1 - 7 - - twi - 8 - - usart0 - 9 - - usart1 - 10 - - usart2 - 11 - - usart3 - 12 - - pwm - 13 - - ssc - 32058k avr32-01/12 71 at32uc3a 14 - - tc - 15 - - abdac - 16 systim er (compare/count registers clk) - - - 31: 17 - - - - tabl e 13-5. maskabl e mo dule cl oc ks i n a t32 uc3a. bit cpumask hsbmask pbamask pbbmask 32058k avr32-01/12 72 at32uc3a 13.6.4 pll con trol name: pll0,1 acces s type: read/write ? reser ved: reser ved bitfields reserved for intern al use. alwa ys wr ite t o 0. ? pllcount : pl l count specifie s the number of sl ow cloc k cycles before isr:lockn wi ll be set after pll n ha s been written, or aft e r plln has be en automatica lly re-enable d after exiti ng a sleep mode. ? pllmul: pll multip ly factor ? plldiv: pll division factor th ese bitfields determin e the ra tio of th e pl l output frequen cy (volta ge controll ed oscill ator frequency f vco ) t o t he source oscill ator frequency: f vco = (pllmul+1)/(plldiv) ? f osc if plld iv > 0. f vco = 2 *(pllmul+1) ? f osc if plld iv = 0. if pllopt[1] fi eld is set to 0: f pll = f vco. if pllopt[1] fi eld is set to 1: f pll = f vco / 2 . note that th e mul fiel d canno t be eq ual to 0 or 1, or t h e behav ior of the pll w ill be undefined. ? pllopt : pll option sele ct the operating range fo r the pll. pllopt[0]: se le ct the vco frequency range. pllopt[1]: en able the ex tra outpu t divider. pllopt[2]: d i sa bl e th e wi de-b a ndwi dt h mo d e (wid e- bandwidth mo de a llo ws a f as t er s t a rt up tim e a nd ou t-of - lo ck time ). 31 30 29 28 27 26 25 24 reserved pllcount 23 22 21 20 19 18 17 16 reserved pllmul 15 14 13 12 11 10 9 8 reserved plldiv 7 6 5 4 3 2 1 0 - - - pllopt pllosc pllen 32058k avr32-01/12 73 at32uc3a ? pllosc: pll o scil lato r s e lec t 0: oscil lator 0 i s t he source fo r the pll. 1: oscil lator 1 i s t he source fo r the pll. ? pllen: pll ena ble 0: p l l is disa bl ed . 1: p l l is enabled. tabl e 13-6. pllop t field s description in at32uc3a description pllopt [0] : vc o fr equ ency 0 160mhz 75 at32uc3a 13.6.6 p m 32 khz oscillat or contro l register regist er name oscctr l 32 register access read/write note : this register is o nly reset b y power-on reset ? osc32en: enable th e 32 khz oscillator 0: 3 2 k h z oscill a tor is d i sabled 1: 3 2 khz oscill ato r is enabled ? mode: oscillator mode choo se betwe e n crysta l, o r extern al clock 0: e x ternal cloc k conn e cte d o n xin 3 2 , xout32 ca n be used as a i/o (n o crystal) 1: crysta l is con necte d to xin3 2 /xo u t 3 2 2 to 7: reserved ? star tup: oscillator star tup time select startup time for 32 khz oscillator 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - startup 15 14 13 12 11 10 9 8 - - - - - mode 7 6 5 4 3 2 1 0 - - - - - - - osc32en tabl e 13-8. startup time for 32 khz os cillator startup number of rc os cillator clock cycle approx imative equiva lent time (rcosc = 11 5 khz) 0 0 0 1 128 1. 1 ms 2 8192 72.3 ms 3 16384 143 ms 4 65536 570 ms 5 131072 1. 1 s 6 262144 2. 3 s 7 524288 4. 6 s 32058k avr32-01/12 76 at32uc3a 13.6 .7 interrupt enable/disable /ma sk/status/clear name: ier/idr/imr/isr/icr acces s type: ier/idr/icr: write-only imr/isr: read-only ? boddet: brow n out detection set to 1 when 0 to 1 t ransition on poscsr:boddet b it is detected: bod has de tected that powe r supp ly is goin g below bod r efere nce value. ? os c 32rdy : 3 2 khz osc i ll at or re ady se t t o 1 wh e n 0 t o 1 t ransi tio n o n t h e pos c sr: osc 32rd y b it is d et ec te d : the 3 2 khz oscillator i s st able and re ady to be used as clock s ource. ? o s c 1r d y : os c i ll ato r 1 rea dy set to 1 wh en 0 to 1 t ransiti on on the poscsr:osc1rdy bit is detected: oscillator 1 i s stable a nd r eady t o b e u s e d as clock source. ? o s c 0r d y : os c i ll ato r 0 rea dy set to 1 wh en 0 to 1 t ransiti on on the poscsr:osc1rdy bit is detected: oscillator 1 i s stable a nd r eady t o b e u s e d as clock source. ? mskrdy: ma sk ready se t to 1 wh en 0 t o 1 t ransi t i on on t h e poscs r: m s kr dy bi t i s d etec te d: clocks are now mas k ed according to the (cpu/h sb/pba/pbb)_mask registers. ? ckrdy: cloc k ready 0: th e cksel re g i ste r ha s b een w ri t ten, an d the n e w c lo c k se ttin g i s no t ye t effe ct iv e. 1: th e synchronou s cloc ks have frequencies as indicated in the cksel register. n ote: writ i n g icr : ckrd y to 1 h a s n o eff ec t. ? lock1 : pll1 locked se t to 1 wh en 0 t o 1 t ransi t i on on t h e poscs r: l o ck1 b i t i s d etec te d: pl l 1 is locked an d ready t o be select ed as clock source. ? lock0 : pll0 locked se t to 1 wh en 0 t o 1 t ransi t i on on t h e poscs r: l o ck0 b i t i s d etec te d: pl l 0 is locked an d ready t o be select ed as clock source. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - boddet 15 14 13 12 11 10 9 8 - - - - - - osc32rdy osc1rdy 7 6 5 4 3 2 1 0 osc0 rdy m skr dy ckr dy - - - lock 1 l ock0 32058k avr32-01/12 77 at32uc3a th e effect of writing o r reading t he bits liste d abov e depends on whic h register is bein g accessed: ? ie r (write-only ) 0: no ef fect 1: enab le interrupt ? idr (write-only) 0: no ef fect 1: disab l e in terr upt ? im r (read-only) 0: interr upt is disabled 1: interr upt is enabled ? is r (read-only) 0: a n interrupt ev ent has not occu rred or has be e n pre vi ously cle a red 1: a n interrupt ev ent has not occurred ? icr (write-only) 0: no ef fect 1: clea r correspo ndin g e ve nt 32058k avr32-01/12 78 at32uc3a 13.6.8 pow e r a nd os cil lators stat us name: poscsr acces s type: read-only ? boddet: brow n out detection 0: no bod event 1: bod has detected that p owe r suppl y is goi ng belo w bod reference value. ? os c 32rdy : 3 2 khz osc i ll at or re ady 0: the 3 2 khz oscillator is not enabled o r not ready . 1: the 3 2 khz oscillator is stable and read y to be u s ed as cloc k source. ? osc1rd y : osc1 r ea dy 0: oscil lator 1 n o t enabl ed or not ready. 1: oscil lator 1 is stabl e a nd read y to be use d as cloc k source. ? osc0rd y : osc0 r ea dy 0: oscil lator 0 n o t enabl ed or not ready. 1: oscil lator 0 is stabl e a nd read y to be use d as cloc k source. ? mskrdy: ma sk ready 0: m a sk register ha s be en changed , masking i n progress. 1: clo ck are mas k ed according to xxx_mask ? ckrdy: 0: th e cksel re g i ste r ha s b een w ri t ten, an d the n e w c lo c k se ttin g i s no t ye t effe ct iv e. 1: th e synchronou s cloc ks have frequencies as indicated in the cksel register. ? lock1 : p l l 1 loc ke d 0:pll 1 is un locked 1: pll 1 i s lo ck ed , a n d r ead y t o be s el e ct e d as clo c k s o u r c e. ? lock0 : p l l 0 loc ke d 0: p l l 0 is u nlo cked 1: p l l 0 is lock ed , a n d r e a d y t o b e s e l ected a s c l o c k s ource. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - boddet 15 14 13 12 11 10 9 8 - - - - - - osc32rdy osc1rdy 7 6 5 4 3 2 1 0 osc0r d y mskrd y c krdy - - - loc k1 lock0 32058k avr32-01/12 79 at32uc3a 13.6.9 generic cloc k control name: gcctrl acces s type: read/write ther e is on e gcctrl regist er pe r gene ric cloc k in t he design. ? div : division factor ? diven: divide ena ble 0: th e g ener ic cloc k equal s the undivid ed source clock. 1: th e g ener ic cloc k equal s the source cloc k divided by 2*(div+1). ? cen: clo ck enable 0: clo ck is sto p ped. 1: clo ck is running. ? pllsel: pll select 0: oscil lator is source fo r the generic clock. 1: p l l is source fo r the gener ic clock. ? oscs el: oscillator select 0: oscil l ator (o r pll) 0 is source fo r the gener ic clock. 1: oscil l ator (o r pll) 1 is source fo r the gener ic clock. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 div[7:0] 7 6 5 4 3 2 1 0 - - - diven - cen pllsel oscsel 32058k avr32-01/12 80 at32uc3a 13.6.10 res et cause name: rcause acces s type: read-only ? por power-on reset th e cpu wa s rese t due to the sup ply voltage being lowe r than the p ower-on thresh old level. ? bo d : bro wn -ou t res et th e cpu wa s rese t due to the sup ply voltag e being lowe r than the br own- out threshold level. ? ext : external reset pin the cpu wa s reset due to t he reset pin being asserted. ? wd t: wa t c h do g rese t th e cpu wa s rese t becau se of a watchd og timeout. ? jtag : jtag reset th e cpu w a s res e t b y se t ti n g t h e b it r c_ c p u in t h e j ta g r e se t regi s t e r. ? cpuerr: cpu er ror th e cpu wa s rese t becau se it h ad detected a n illega l access. ? ocdrst: ocd reset th e cpu wa s rese t becau se th e res strobe in the ocd deve lo pmen t contr ol register ha s b ee n w r it t en t o on e. ? j ta g h ard : j tag har d re s et th e chip wa s re set b y s e tt in g th e b i t rc _ o c d i n t he jtag reset register or by us ing the jtag halt instruction. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - jtaghard ocdrst 7 6 5 4 3 2 1 0 cpuerr - - jtag wdt ext bod por 32058k avr32-01/12 81 at32uc3a 13.6.1 1 bod control bod le ve l regist er regist er name bod register access read/write ? key: register w r ite protection thi s f i e l d mu s t b e w ri t te n t wi ce , firs t w it h k e y valu e 0 x55 , th en 0xaa, for a writ e o perat i on to h av e a n eff e ct. ? fc d: bod fuse calibr ation done set to 1 when ctrl, hyst and level fields has been updated b y the flas h fuse s afte r powe r-on res et o r fla sh fuses update if on e , th e ctrl , hyst an d level values w ill no t be up dated again by flash fuse s ca n be cleared to al lo w subsequent overwritin g of the value by fl ash fuses ? ctrl: bo d control 0: bod is of f 1: bod is ena bled an d can reset the chip 2: bo d is en abled a n d b u t c a n n ot res e t t he c h ip . o nly in terr u pt wi ll be sent to interr upt controller, if enabled in t h e imr register. 3: bod is off ? hyst : bod hysteresis 0: no hysteresis 1: hyster esis on ? level: bod l evel th is fie ld sets the triggering threshol d of the bo d. see el ectric al char acte r i stics fo r actu al vo lt a ge le vels. note that an y c h ange to the level f i eld of th e bod register shou ld be d o ne with th e bod deact iv ated t o av oi d sp ur io us res e t or inter rupt. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 - - - - - - - fcd 15 14 13 12 11 10 9 8 - - - - - - ctrl 7 6 5 4 3 2 1 0 - hyst level 32058k avr32-01/12 82 at32uc3a 13.6.1 2 rc oscillat or calibration regist er name rccr register access read/write ? calib : calibration value ca l ibrat i on v al ue fo r th e r c os ci llato r. ? fc d: fl ash calibratio n done set to 1 when ctrl, h yst , and level fiel ds have been updated by the flash fuses a f ter powe r-on reset, or after flash fuses are repr og rammed. the ctrl, hyst an d l evel values wi ll not be up d ated again by th e flash fuse s until a n e w power-on reset o r th e fcd fi eld is w r itt e n to zer o. ? key: register w r ite protection thi s f i e l d mu s t b e w ri t te n t wi ce , firs t w it h k e y valu e 0 x55 , th en 0xaa, for a writ e o perat i on to h av e a n eff e ct. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 - - - - - - - fcd 15 14 13 12 11 10 9 8 - - - - - - calib 7 6 5 4 3 2 1 0 calib 32058k avr32-01/12 83 at32uc3a 13.6.1 3 bandg ap c alibr at ion regist er name bgcr register access read/write ? key: register w r ite protection this fiel d mu st be written twice , first with key v alu e 0x55, th en 0xaa , for a w rit e operation to hav e an effect. ? calib : calibration value calibration va lue for ba ndgap. see electric al characteristic s for voltage values. ? fc d: fl ash calibratio n done set to 1 wh en the ca lib fiel d h a s b ee n u pdated b y the f l ash fuses after p ow er-o n rese t or whe n the flash fuses are reprog rammed. the cali b fi eld wi ll not be upd ated again by th e flash fuse s until a n e w powe r-on reset or the fcd f i eld is wr itten to zero. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 - - - - - - - fcd 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - calib 32058k avr32-01/12 84 at32uc3a 13.6.14 pm voltage regulat or calibration register regist er name vregcr register access read/write ? key: register w r ite protection thi s f i e l d mu s t b e w ri t te n t wi ce , firs t w it h k e y valu e 0 x55 , th en 0xaa, for a writ e o perat i on to h av e a n eff e ct. ? calib : calibration value calibration value for voltage regulator . see electrical characteristics for voltage values. ? fc d: fl ash calibratio n done set to 1 wh en the ca lib fiel d h a s b ee n u pdated b y the f l ash fuses after p ow er-o n rese t or whe n the flash fuses are reprog rammed. the cali b fi eld wi ll not be upd ated again by th e flash fuse s until a n e w powe r-on reset or the fcd f i eld is wr itten to zero. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 - - - - - - - fcd 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - calib 32058k avr32-01/12 85 at32uc3a 13.6.15 general purpos e low-pow er register 0/1 regist er name gplp0,1 register access read/write thes e registers are genera l purpos e 32-bit registers that are reset only by power-on-reset. any other reset w ill keep the conten t of thes e registe rs untouched. 31 30 29 28 27 26 25 24 gplp 23 22 21 20 19 18 17 16 gplp 15 14 13 12 11 10 9 8 gplp 7 6 5 4 3 2 1 0 gplp 32058k avr32-01/12 86 at32uc3a 14. real time counter (rtc) re v: 2.3.0.1 14.1 features ? 32 -bit re al-time counte r with 16 -bit prescaler ? cloc ked fr om rc oscillat or or 32 khz oscillator ? high resoluti on: max count frequenc y 16 khz ? lon g delays ? m ax timeout 272 years ? extremel y low po wer consumption ? availabl e in all sleep modes exce pt static ? interrupt on wrap 14.2 description the real time c ounter (rtc ) e nables periodi c interrupts at long in tervals, or acc urat e mea- surement of rea l-time se quences. th e rtc is fe d from a 16-bit prescaler , which i s cloc ked from the rc os c illator or the 32 kh z oscillator. any tapp ing of the pres caler can be selected as clock source for t he rtc, enabling bot h hi gh resoluti on and lo ng timeouts. t he pres caler cann ot be written direct ly, bu t ca n be cleared by t he user. t h e rt c can g enera te an in terr up t when t he c ount er wraps a round t he v alue s to r ed in the top register , producin g accurate period ic interrupts. 32058k avr32-01/12 87 at32uc3a 14.3 block diagram figur e 14-1. real time counte r modul e block diagram 14.4 p roduct dependencies 14.4.1 power management th e rt c is continuo usly clocked, an d remain s operating i n a ll sle ep mo des except static. inter- rup ts ar e not available in deepsto p mode. 14.4 .2 interrupt th e rtc interrupt line is c onnecte d to on e o f the internal sources of t he interrupt controller. us ing th e rtc i nt erru p t re quires th e interrup t con troller t o b e p rogramm ed first. 14.4.3 debug operation th e rtc prescale r is frozen during deb ug operation, unless the ocd sys t em keep s peripherals runn ing i n debu g operation. 14.4.4 clocks th e rt c can use the intern al rc oscillator as clock source. this oscil la tor i s al wa ys enab l ed whenever th ese modules are active. please refer to the electrical characterist ics chapter for the characterist ic frequenc y of this oscillator ( f rc ). the rt c can also use the 32 khz crys tal oscilla tor as cloc k source. this osc illator must be enab led befor e use. ple ase refer t o th e powe r manage r chapter fo r details. 14.5 functional description 14.5.1 rt c operation 14.5.1 .1 sour ce clock the rtc is enabled b y writing the en bit in the ctrl register t o 1. t he 1 6-bit pres cal er will t hen increment on th e selected clock. the prescale r cannot be read or written, but it c a n be reset by writing the pclr strobe. 16-bit prescaler rc osc 32- bit coun t er rtc_val rtc_top topi irq 32 khz rtc_ctrl en clk32 pclr 1 0 32058k avr32-01/12 88 at32uc3a the clk32 bit selects either the rc oscillator o r the 32 khz oscillator as clock source for th e prescaler. th e pse l bitfie ld selects the prescaler tappi ng , s el ecti ng t he s ource clock for the rtc: f rtc = 2 - (psel+1) * ( f rc o r 32 khz) 14.5.1.2 counte r operation when enabled, the rt c w ill increme n t until it reaches top, and the n wrap to 0x0. the status bi t topi in isr i s se t when this occurs . from 0x 0 the co unter will count top+ 1 cycles of the source clock before i t wrap s ba ck t o 0x0. the rtc cou n t value ca n be read fr om or writte n to t he regist er val. due t o synchronization, continuous reading of the val with the lowest pre s caler sett ing will skip every other value. 14.5.1.3 rt c interrupt writin g the to pi bit in ier enab les the rtc interrupt, while writin g th e corresponding bit in id r disables the rtc i nterrup t. im r can be read to se e whethe r or no t the interrupt is enabled . if enabled, an interrup t wi l l be g e ner ated if the topi flag in isr is se t. t h e fl ag c an b e cl e are d by writing topi in icr to one. th e rt c interrupt ca n wake th e cpu from a ll sle ep mode s except deepsto p an d stat ic mode. 14.5.1.4 rtc wakeup th e rtc can also w ake up t he cpu direct ly withou t triggering an interrup t wh en th e to pi flag in is r is set. in this case , the cpu will co ntinue exec uting from the instructio n follow ing the sleep instruction. thi s d ire ct rt c wak eup i s enable d b y w ri tin g t h e wake_e n bit in t he ctrl register to one. when the cpu wa kes from sleep, t he w ake_e n bi t must be writt en to zero to clear the interna l wake signal to the sleep contr o ller, otherw ise a new sleep instruction w ill have no effect. the rtc wake up is avail a ble in all sleep mode s except stat ic mode. the rtc wakeup can be configured independently o f the rtc in terrupt. 14.5.1 .5 bu sy bit due to t he crossing of cloc k domains, th e rt c uses a fe w cloc k cycles t o propagate t he values stored in ctrl , to p, and val to the rtc. th e busy bit in ctrl indi cates that a regi st er write is still going on and all write s to to p, ctrl, and val will be di scarded until busy goes lo w again. 32058k avr32-01/12 89 at32uc3a 14.6 u ser interface 14.6.1 rtc control name: ctrl acces s type: read/write ? clken: clo c k enable 0: th e cloc k is disabled 1: th e clock i s enabled ? psel: prescale selec t selects prescaler bit psel a s source clo ck fo r the rtc. ? busy: rtc busy 0: th e rtc acce pts writes to top, val, a nd ctrl. 1: th e rtc is bu sy an d will discar d wr ites to top, val, an d ctrl. ? clk32: 32 khz o s cillator select 0: th e rtc uses the rc osci ll ator as cloc k source 1: th e rt c uses the 3 2 khz osci l lator as cloc k source offset register register na me access reset 0x00 rt c control ctrl read/write 0x0 0x04 rtc value val read/write 0x0 0x08 rtc top top read/write 0x0 0x10 rt c interr upt enable ier write-only 0x0 0x14 rt c interrup t disable idr write-only 0x0 0x 18 r t c i nterru p t m a sk i mr re ad- o n ly 0x0 0x1c rt c interrup t status isr read-only 0x0 0x20 rt c interrupt clear icr write-only 0x0 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - clken 15 14 13 12 11 10 9 8 - - - - psel 7 6 5 4 3 2 1 0 - - - busy clk32 wake_en pclr en 32058k avr32-01/12 90 at32uc3a ? wake_en: wakeup enable 0: th e rt c d oes not wake up t h e cpu from sleep modes 1: th e rtc wake s up the cpu from sl e ep modes. ? pclr: pr escale r clear writi ng 1 to this stro be clea rs the prescaler. ? en: enable 0: th e rtc is d isabled 1: t h e rtc i s enabl ed 32058k avr32-01/12 91 at32uc3a 14.6.2 rtc value name: val acces s type: read/write ? val: rtc value this value is in cremented on every rising ed ge of the so urce clock. 31 30 29 28 27 26 25 24 val [ 3 1: 24] 23 22 21 20 19 18 17 16 val [ 2 3: 16] 15 14 13 12 11 10 9 8 val[15:8] 7 6 5 4 3 2 1 0 val[7:0] 32058k avr32-01/12 92 at32uc3a 14.6.3 rtc top name: top acces s type: read/write ? top: rtc top value va l wraps at this value. 31 30 29 28 27 26 25 24 top[31:24] 23 22 21 20 19 18 17 16 top[23:16] 15 14 13 12 11 10 9 8 top[15:8] 7 6 5 4 3 2 1 0 top[7:0] 32058k avr32-01/12 93 at32uc3a 14.6.4 rtc inte rrupt enable/disable/mask/status/clear name: ier/idr/imr/isr/icr acces s type: ier/idr/icr: write-only imr/isr: read-only ? topi: to p interrupt va l has wrapped at its to p value. th e effe ct of writing or reading this bit depe nds on whic h register is b ein g accessed: ? ie r (write-only ) 0: no ef fect 1: enab le interrupt ? idr (write-only) 0: no ef fect 1: disab l e in terr upt ? im r (read-only) 0: interr upt is disabled 1: interr upt is enabled ? is r (read-only) 0: a n interrupt ev ent has occurred 1: a n i nterrupt ev en has no t occurred ? icr (write-only) 0: no ef fect 1: clear i nterrupt even 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - topi 32058k avr32-01/12 94 at32uc3a 15. watch dog timer (wdt) re v: 2.3.0.1 15.1 features ? watchdog ti mer counter with 16-bi t prescaler ? cloc ked f r om rc os cillator 15.2 description th e watchdog timer (wdt) has a prescale r generating a timeout period. th is prescaler is clocked from the rc o s cillator. th e watchdog timer must be periodic ally reset b y s oftware within the timeout period, otherwise , the de vice is reset and starts executin g from t he boot vector. this allows t he device to recover fr om a condition that ha s caused th e system to be unstable. 15.3 block diagram figur e 15-1. watchdo g time r modul e block diagram 15.4 p roduct dependencies 15.4.1 power management when t he wdt is enabled , t he wdt rema ins clocke d in a ll sleep modes, and it is not possible to ente r stat ic mode. 15.4.2 debug operation th e wdt prescaler is frozen duri ng deb ug operation, un less the oc d syste m keep s peripherals runn ing i n debu g operation. 15.4.3 clocks the wdt can us e t he inte rnal rc oscillator as clock source. this osc illa t or is always enabled whenever th ese modules are active. please refer to the electrical characterist ics chapter for the characterist ic frequenc y of this oscillator ( f rc ). rcosc wdt_clr watchdog detector wdt_ctrl 32-bit prescaler watchdog reset en 32058k avr32-01/12 95 at32uc3a 15.5 functional description th e wdt is enabled by writing the en bi t in the ctr l regi ster to one. this also enables the r c clock f or the prescaler. the psel bitfie ld in th e same register selects the watchdog timeout period: t wdt = 2 (psel+1) / f rc the ne xt timeout period w ill begin as soon a s the watchdog reset has o c cured and co unt down during the reset sequenc e. ca re must be taken when selectin g t he ps el v alu e s o that the time- ou t period is g reater than the startup time of th e chip , othe rwise a watchdog reset can rese t the ch ip befor e any code ha s bee n run. to avoid accidental disabling o f the watchdog , t he ctrl register must be writt en twice , first with the key fiel d set to 0x5 5 , the n 0xaa with out chan gin g th e other bitfiel ds . failure to do so wil l cause the writ e operatio n t o be ignored, and ctr l d oes no t change value. th e cl r register must be writte n wit h any va lue wit h regular inte rvals shorte r th an th e watchdog timeout period. otherwise , t he device will receive a so f t reset, and the code will s t art executing from th e boot vector. when the wdt i s enabled, it is not po ss ible to enter static mo de. attempting to do so will result in e ntering shutdo wn mode, leaving th e wdt operational. 32058k avr32-01/12 96 at32uc3a 15.6 u ser interface offset register register na me access reset 0x00 w dt control ctrl read/write 0x0 0x04 wdt clear clr write-only 0x0 32058k avr32-01/12 97 at32uc3a 15.6 .1 wdt control name: ctrl acces s type: read/write ? key th is bitfield mu st be writ ten twice, first with key va lue 0x55 , then 0xaa, for a w rite o peration t o be e ff e ctiv e. th i s b i tfield alwa ys reads as zero. ? psel: prescale selec t prescaler bit psel is used a s watc hdog ti meout period. ? en: wdt ena ble 0: wdt is d isa bl ed . 1: wdt is e nabled. 31 30 29 28 27 26 25 24 key[7:0] 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - psel 7 6 5 4 3 2 1 0 - - - - - - - en 32058k avr32-01/12 98 at32uc3a 15.6.2 wdt cl ear name: clr acces s type: write-only whe n th e watchdog time r is enabled, this registe r m ust b e periodica lly written, wit h an y value, within the watchdog timeout period, to preven t a watchdog reset. 32058k avr32-01/12 99 at32uc3a 16. interrupt controller (intc) re v: 1.0.1.1 16.1 description t he in tc collect s interrupt req ue sts fro m th e p eripherals, prioritizes them , an d d eliv er s an int er- rupt request and a n autovector to t he cpu. th e avr3 2 architecture supports 4 p riori ty levels for regular, maskab le interrupts , an d a non-maskabl e interrupt (nmi). t he in tc sup p or ts up to 64 g roup s of interrupts . each grou p ca n ha v e u p t o 32 inte rr up t re quest lines, these lines are connected to the peripherals. ea ch grou p ha s an interrupt priority register (ipr ) and an interrup t reques t register (irr). th e iprs are used t o assign a p riority level and an au tovector t o ea ch g rou p , an d t he irrs are used to i de ntif y th e active interru pt request with in each gro u p. if a gro up has o nly one in terrupt request line, an active interrupt g roup uniquely iden tifie s t h e act iv e in te r rup t re q ue s t li ne, and th e correspon ding irr is n o t ne eded. t he intc also pr ovides o ne inte rrupt caus e re gister (icr) per priority level. these re gisters id entify the group t hat ha s a pe nding interru pt of the corresponding priority level. if sever al grou ps ha ve an pend ing interrupt o f th e sa me level, t he grou p with the lo west number ta kes priority. 16.2 block diagram figure 16- 1 on pa ge 99 give s a n ove rview o f the in tc. th e grey boxe s represen t registe rs that can be accessed via t he peripher al bus (pb). th e interrupt requests from the peripherals (ireqn) a nd th e nmi are in put on th e left side of t h e f i gure . sign als t o and fro m t he cpu ar e on the right side of the figure. figur e 16-1. ove r view o f th e inte rr upt controller 16.3 operation al l o f t he i nco mi ng i nter rup t re quests (ir eq s) ar e sampl ed in to t he c o rresp ondi n g i nte rru pt request register (irr). the ir rs must be accessed to identify which ireq wi thin a group that is active . i f several ireq s within the sa me grou p is active, th e interrupt se rvice routin e must pri- re qu est maski ng or ireq0 ireq1 ireq2 ireq31 gr pre q0 masks sreg masks i[3-0]m gm intlevel a ut ovector priori tiz er cpu interrupt controller or grpreqn nmireq or ireq32 ireq33 ireq34 ireq63 gr pre q1 irr registers ipr registers ic r registers int_level, offset int_level, offset int_level, offset ipr0 ipr1 iprn irr0 irr1 irrn valreq0 valreq1 valr eqn 32058k avr32-01/12 100 at32uc3a oritiz e be tween them . al l o f th e inpu t line s in eac h g rou p a re logic a lly-ore d to gethe r to fo rm the grpreq n lin es, indicati ng if ther e is a pend ing interrupt in t he correspondin g group. t he r equest mask ing h ard w are m a ps ea c h o f t he grp r eq line s t o a p r ior it y l evel from in t0 t o in t3 by associating each group with the intlevel field in the corresponding ipr register. th e grpreq inputs are the n masked by the i0m, i1m, i2m, i3m an d gm mask bits fr om th e cpu sta- tus register. any interrupt grou p that has a p ending interrupt of a priority level that is n o t masked by the cpu stat us register , gets its correspondin g valreq lin e asserted. the prioritizer hardware uses t h e valr eq lines and the intlevel fi eld in the iprs to select the pending int errupt of the highest priority. if a nmi int errupt is p ending, it aut omatically get s high- est priority of any pendin g interrupt. if s evera l interrupt groups of th e highes t pendin g interrupt level ha ve pending interrupts, t he interrupt group with t he highest number is sel ected. interrupt level (i nt level) and ha n dler autovector offset (autovector) of the selected inter- ru pt are transmitted t o the cpu for interrupt handling an d context switchin g. the cpu doesn't need to know which in terrupt is requesti ng handling, but on ly th e level and t he offset o f the han- dler ad dr ess. the i rr register s con t ain th e int errupt requ est lines o f t he group s and can b e read via pb f or checking which interrupts o f t he gro u p a r e act ually ac tive. masking o f the interrup t requests is done based on five int errup t ma sk bits o f the cpu stat us register , namely interrup t le vel 3 ma sk (i3m) to interrup t leve l 0 mask (i0m), and globa l inter r up t ma sk (gm) . an interrupt requ est is masked if either the glob al interrupt mask or the correspond- ing in terrupt leve l mask bit is set. 16.3.1 non m askable interrupts a nm i request has pri ority over all o the r interrupt requests. nm i has a dedicat ed exceptio n vec- t or ad dress defin ed by th e avr32 architecture, so autovecto r is undefined when in tlevel indicates that an nmi is pending. 16.3.2 cpu r esponse when the c pu receiv es an interr upt request it checks if any other exceptions are pending . if no except ions of higher p rio rity are pending, interrupt handling is initia t ed. when initiatin g interrupt handling , the corresponding interrupt ma sk bit is s et a utom atically fo r th is and lower le vels in sta- tus register . e.g, if interrup t on level 3 is a pproved fo r handling the interrupt mask bits i3 m, i2m, i1m, and i0m are set in s t atus register. if int errupt on level 1 is approve d the masking bits i1m, and i0m ar e se t in status register. the handle r offse t is calculated from autovector and evba and a change-of-f l ow to this address is performed. sett ing of t he interrupt mask bits prevents t he interrupts f rom the same an d lower levels to b e passed trough t he interrupt controller. sett ing of the same l e vel mask bit prevent s also multiple request of t he same interrupt t o happen. it i s the responsibility of the h andler so ftware to clear the interrupt request that cau s ed the inter- rupt befor e returning from the interrup t handler . if the conditions that caused t he interrupt ar e not cleared, the interrupt request remains active. 16.3.3 clearing an interrupt request clearing o f t he interrupt request is done by wri ting to regist ers in th e corresponding peripheral module, which then clears the correspondin g nmireq/ireq signal. the recommended way of clearing an inte rrupt request is a stor e op eration to t he controlling peri pheral regi ster, follow ed b y a du mm y load oper at ion from the sa me r egister. this causes a 32058k avr32-01/12 101 at32uc3a pipeline stall, which pr even ts th e interrupt fro m accidentally re-triggerin g in case th e handler is exi te d and the inter rup t m a sk is cleared befor e t he inte rr upt r equ e st is clea re d. 16.4 u ser interface th is chapte r lists the intc register s ar e accessible through t he pb bus. t he register s ar e used to contr o l th e be h aviour an d re ad th e st at us o f th e intc. 16.4.1 memory map the following table shows the addre ss ma p o f the intc registers, relative to the base addr ess of the intc. 16.4 .2 interrupt request map th e mapping of interrupt requests from peripheral s to intreqs is p resente d in th e peripherals section. tabl e 16-1. intc addr ess map offset register name access reset value 0 interru pt priority regist er 0 ipr0 read/write 0x0000_0000 4 interru pt priority regist er 1 ipr1 read/write 0x0000_0000 ... ... ... ... ... 252 in terru pt p rio ri ty r egis t er 63 ipr63 read/write 0x0000_0000 256 interru pt reque st registe r 0 irr0 read-only n/a 260 interru pt reque st registe r 1 irr1 read-only n/a ... ... ... ... ... 508 interru pt reque st register 63 irr63 read-only n/a 512 interru pt ca use registe r 3 icr3 read-only n/a 516 interru pt ca use registe r 2 icr2 read-only n/a 520 interru pt ca use registe r 1 icr1 read-only n/a 524 interru pt ca use registe r 0 icr0 read-only n/a 32058k avr32-01/12 102 at32uc3a 16.4 .3 interrupt request registers register name: irr0...irr63 access type: read-only ? irr: interrupt reques t line 0 = n o interrupt requ est is pendi n g on this inpu t reque st inp ut. 1 = a n interrupt request is p ending on th is input request input. the ar e 6 4 irrs , o ne f o r each gro up. each irr ha s 32 bits , o ne fo r each po ssible inte rru p t re ques t, fo r a to tal of 20 48 p os- sible inpu t lines. the irrs are read b y t he software interrupt hand ler in order to determine which interru pt request is pending. the i rrs ar e samp led continuously, an d ar e read-only. 31 30 29 28 27 26 25 24 irr(32*x+31) irr(32*x+30) irr(32*x+29) irr(32*x+28) ir r( 32*x+27) i rr( 32 *x+26) i rr(3 2 *x+25) ir r(32*x + 2 4) 23 22 21 20 19 18 17 16 irr(32*x+23) irr(32*x+22) irr(32*x+21) irr(32*x+20) ir r( 32*x+19) i rr( 32 *x+18) i rr(3 2 *x+17) ir r(32*x + 1 6) 15 14 13 12 11 10 9 8 irr(32*x+15) irr(32*x+14) irr(32*x+13) irr(32*x+12) irr(32*x+11) irr(32*x+10) irr(32*x+9) irr(32*x+8) 7 6 5 4 3 2 1 0 irr(32*x+7) irr(32*x+6) irr(32*x+5) irr(32*x+4) i rr(3 2*x+3) i rr( 3 2*x + 2 ) irr(32*x+1) ir r( 32 *x+0) 32058k avr32-01/12 103 at32uc3a 16.4 .4 interrupt priority registers register name: ipr0...ip r63 acces s type: read/write ? i n t lev el: int e rrup t le vel associated with this group indicates the evba-relative off s et o f the interrupt h andl er of the corresponding group: ? auto vec tor: autov ect or a ddress fo r th is group handle r offset is use d to give t he addr ess o f the interrupt handler. th e least significant bit shou ld be written to zero t o give halfwor d alignment 31 30 29 28 27 26 25 24 intlevel[1 :0] - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - autovector[13:8] 7 6 5 4 3 2 1 0 autovector[7:0] intlevel[1:0] priority 0 0 int0 0 1 int1 1 0 int2 1 1 int3 32058k avr32-01/12 104 at32uc3a 16.4.5 interrup t caus e registers register name: icr0...icr3 access type: read-only ? cause: interrupt grou p cau sing interrupt of prio rit y n icrn identif ies th e group with t he highest priori ty that ha s a pending interrupt of level n. if no interrup ts of le vel n ar e pend- ing, or the priorit y level is mas k ed, the value of icrn is u ndefined. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - cause 32058k avr32-01/12 105 at32uc3a 17. external interrup ts contro ller (eic) re v: 2.3.0.2 17.1 features ? dedicated interrupt r equ ests fo r eac h inter r upt ? individually maskab le interrupts ? interrup t on risin g or falling edge ? interrup t on high or l ow level ? asynchrono us interrupts fo r sleep modes without clock ? filtering of interrupt lines ? ke ypad scan support ? maskab le nmi interrupt 17.2 description the ex t ernal interr upt module allows pins t o be configure d as external interrupts. each pin ha s it s own interrupt request and ca n be individually mask ed . e ach pi n ca n g e nera t e an inter rup t o n rising or falling edge, or high or low level . ever y line has a con figurable filter too re move spikes on the interrupt lines . ever y interrupt pi n can also be configured to be asynchronous to wake up the part from slee p mo des wher e th e clock has been disabled. a n on-maskable interru pt (nmi) is also suppor ted. th is ha s th e sam e prope rties as the other external interrupts, but is co nnecte d to th e nmi request of the cpu, enablin g it to interrupt any othe r interrupt mode. th e exter nal interrup t module ha s suppor t fo r keypad scanning fo r keypad s lai d out in r o ws and col u m ns . c olu m ns a r e dr ive n by a s epara t e s et of sc anni n g ou t puts, w hile r ow s are s ensed by the external interrupt line s . th e p resse d key will tri gg er a n i n terru pt, wh i c h ca n be identified through th e user reg ister s o f th e modu l e. th e ext ern al in terrup t m odul e ca n wak e up t he part fr om sleep m odes without trigger ing an interrup t. in th is mode, code executio n starts from th e instruction following t he slee p instruction. 32058k avr32-01/12 106 at32uc3a 17.3 block diagram figur e 17-1. extern al interru p t m o dule block diag ram 17.4 p roduct dependencies 17.4.1 i/ o li nes th e external interrupt an d keypad scan pins are mult iplexed with pio lines. to ac t as external interrupts, t hese pins must be con figured as i nputs pins by t he pio controller. it is also p ossible t o trigger the interru pt by driving t hese pins from register s in t he pi o controller, o r another peripher al output connecte d to th e sa me pin. 17.4.2 power management all i nterrup ts ar e availabl e in every sleep mode . howeve r, i n slee p modes w her e t he clock is stopped, asynchrono us interrup ts must be selected. 17.4 .3 interrupt the ex t ernal inter rupt lin es are connected to internal sources of the interrupt controller. using the external interrut ps require s th e interrupt controller to b e programmed first. using t he non- ma skab le inte rrup t d oes no t req uir e th e interru p t co ntr oll e r to be pr ogr a mmed. edge/level detector mask irqn extintn nmi eim_level e i m_mod e eim_edge eim_ier eim_idr eim_imr filter eim_filter polarity control eim_level eim_mode eim_edge asynchronus detector wake detect eim_wake enable eim_en eim_d is eim_ctrl prescaler shifter presc en eim_scan pin scan rc clk intn eim_icr eim_isr 32058k avr32-01/12 107 at32uc3a 17.5 functional description 17.5 .1 external interrupts to enable an external inte r rupt extintn must be wri tten to 1 in register en. similarly, writin g exti ntn t o 1 i n register dis di sables th e inte rrupt. the sta tus of each interru pt line can be observed in t h e ctrl register. each ex t ernal interr upt pin extintn can be configu red to produ ce an interr upt on rising or fall- ing ed g e, or high or low leve l. extern al interr upts are configured by th e mode, edge , and level registers. each interrupt n has a b i t int n i n ea c h of these registers. similarly, each interrupt has a corresponding bit in ea ch o f t he interrupt contro l and status regis- ters . writin g 1 to the intn stro be in ier enable s th e external interrupt on pin extintn, whil e writing 1 to in tn in idr disables the external inter rupt. imr can be read t o check which inter- rupt s ar e enabled. when t he in te rrupt triggers, the correspondin g bit in isr will be set. the fla g remain s set until the corresponding strobe b i t in ic r is writ ten to 1. writing intn in m o de to 0 e nables edg e triggered interrup ts, wh ile writing the bit to 1 e nables level triggered interrupt s. if extintn is configured as an edge triggered interrupt , writing intn in edg e to 0 will trigger th e interrupt on falling edge, wh ile writing the bit t o 1 wil l tri gge r th e inte rrupt on r i sing edge. if extintn is configured as a l e vel triggered inte rrupt, writing intn in level to 0 will trigger the interrupt on lo w level, w hi l e wr iting the bit to 1 will trigger t h e interrupt on high level. to remove sp ike s that ar e longer tha n th e clock peri od i n the current mod e each ext er nal in ter- rupt contains a filter that can b e enabled by w ritin g 1 to intn to filter. each interrupt line can be made a synchronous by writing 1 to in tn in the asyn c register. this will route the in terrupt signal th rough the asynchro nous path of the mod ule . a l l ed g e i n t e rrup t s will be interpreted a s lev e l interrupts and the filter is disabled. 17.5.1.1 synchronization of external interrupts th e pin value of th e extintn pins is n orm ally sy nchro nized to th e cpu clock, so spikes shorte r than a cpu clock cycle are not guaranteed to prod uce an interrupt. in stop mode , spikes shorter than a 32 khz clock cycl e ar e not guarantee d t o produce an interrupt. in static mode, only unsynchr o nized interrupts rem ain acti ve, and any short spike on t his inter- rupt w ill wake up the device. 17.5.1.2 wakeup th e external interrupts ca n b e used to wake up th e part fro m sleep mod es. th e wakeup ca n be interpreted in tw o ways. if the corresponding bit in imr is set, th e n the executio n starts at the interrupt ha n dler for this i n terrupt. if the bit in i m r is not set, the n t h e exe cu tion starts fr om the next instructio n afte r th e sleep instruction. 17.5 .2 non-maskable interrupt the nmi s u pports the same features as the external interrupts, and is accessed thr ough the same regis t ers. th e description in se ctio n 1 7.5. 1 s hou ld be f o llowed , accessin g t he n m i bit instea d o f the int n bits. 32058k avr32-01/12 108 at32uc3a t h e nm i i s non - m as k able wit hin th e cp u i n th e sen se that it can in terrupt a n y ot her e xecu t io n mode. still, as for the other e xte rnal interrupts, the actual nm i in put l i ne c an be ena bl ed a nd dis- abled by accessing t he register s in the exter nal interr upt mod ule. these interrupt s ar e not enabled by defaul t, all owing t he proper interrupt vecto rs to be set up b y th e cpu be fore the interrup ts ar e enabled. 17.5.3 keyp ad sc an support th e exter nal interrup t module also inclu d es su ppor t fo r keypad scanning. the keypad scan f ea- ture is co mpatible with keypad s organized as ro ws and column s, where a ro w is shorted against a col u mn whe n a ke y is pressed. the rows should be connected to the external interrup t pins with p ullups e nabled in the gpio module. these external i nterrupts sh ould be enabled as low level or f a lling edge interrupts . the colu mns should be connected to th e availa ble scan pins. th e gpio must be configured to le t the required scan pi ns be c ontrolled by the ei c module. un used extern al interrup t or scan pi ns can be left controlle d by th e gpi o o r other peripherals. t h e key pa d s can function is e n abl ed by wri tin g :en t o 1, whic h sta r ts th e keypad sca n counter . the sca n output s ar e t r istated , ex cep t s can[0], wh ich is driven t o zero. after 2 (scan:presc+1) rc cloc k c ycles this pattern is left shifted, so that scan[1] is d r iven to zero while the othe r out- pu ts are tristated. this seq uenc e repeat s infinitely, wrapping from t he most significant scan pi n to scan[0]. when a key is pressed , t he pulled-u p ro w is driven to zero by t h e column , an d an external inter- ru pt trigge rs. th e scannin g stops, a nd th e softwar e can th en identify th e key pressed by the interrupt status registe r and the scan:pin s value. th e scann ing stops wh enever there is an active inte rrupt re quest fro m th e eic to the cpu. when th e cpu clears the interrupt flags, scanning resumes. 32058k avr32-01/12 109 at32uc3a 17.6 u ser interface offset register register na me access reset 0x00 eic interrup t enable ier write-only 0x0 0x04 eic i nterrupt disable idr write-only 0x0 0x08 eic int err upt mask imr read-only 0x0 0x0c eic inter rup t status isr read-only 0x0 0x10 eic int err upt clear icr write-only 0x0 0x14 external interrup t mode mode read/write 0x0 0x18 extern al interr upt edge edge read/write 0x0 0x1c e x t e rn a l i n terr upt l evel l evel rea d/ w r i te 0x0 0x20 external interrup t filter filter read/write 0x0 0x24 extern al interrupt test test read/write 0x0 0x28 exter nal interr upt asynchronous async read/write 0x0 0x2c exter n al inter r upt scan scan read/ wri te 0x0 0x30 extern al interr upt enable en write-only 0x0 0x34 external interrup t disable dis write-only 0x0 0x38 external interrup t control ctrl read/write 0x0 32058k avr32-01/12 110 at32uc3a 17.6 .1 eic interrupt enable/disable/mask/status/clear name: ier/idr/imr/isr/icr acces s type: ier/idr/icr: write-only imr/isr: read-only th e effect of writing o r reading t he bits liste d abov e depends on whic h register is bein g accessed: ? ie r (write-only ) 0: no ef fect 1: enab le interrupt ? idr (write-only) 0: no ef fect 1: disab l e in terr upt ? im r (read-only) 0: interr upt is disabled 1: interr upt is enabled ? is r (read-only) 0: a n interrupt ev ent has occurred 1: a n i nterrupt ev en has no t occurred ? icr (write-only) 0: no ef fect 1: clear i nterrupt event 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - nmi 7 6 5 4 3 2 1 0 int7 int6 int5 int4 int3 int2 int1 int0 32058k avr32-01/12 111 at32uc3a 17.6.2 exter n al interrup t m ode/edg e/leve l/filter/asy nc name: mode /edge/level/filter/a sync acces s type: read/write th e b i t interpretation is r egiste r specifi c: ? mode 0: inter r up t is e d ge t r igge red 1: interr upt is leve l triggered ? edge 0: inter rup t trig gers on falling edge 1: inter rup t trig gers on rising edge ? level 0: inter rup t trig gers on lo w level 1: inter rup t trig gers on high level ? filter 0: inter rup t is no t filtered 1: interr upt is filtered ? async 0: interr upt is synchronized to th e clock 1: interr upt is asynchronous 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - nmi 7 6 5 4 3 2 1 0 int7 int6 int5 int4 int3 int2 int1 int0 32058k avr32-01/12 112 at32uc3a 17.6.3 externa l interrupt test name: test acces s type: read/write ? nmi if test_en is 1, the val ue of this bi t wil l be the valu e to the interrupt detector an d the value on th e pad wil l be ignored. ? intn if test_en is 1, the val ue of this bi t wil l be the valu e to the interrupt detector an d the value on th e pad wil l be ignored. ? test_en 0: exte r na l i n terr upt t e st is disa bled 1: e xte rna l int er rup t t e s t i s en ab l ed 31 30 29 28 27 26 25 24 test_en - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - nmi 7 6 5 4 3 2 1 0 int7 int6 int5 int4 int3 int2 int1 int0 32058k avr32-01/12 113 at32uc3a 17.6 .4 external inte rrupt scan name: scan acces s type: read/write ? en 0: ke ypad scanning is disabled 1: ke ypad scannin g is enabled ? presc prescale select fo r the ke ypad s can ra te: scan rate = 2 (scan:presc+1) t rc th e rc cloc k perio d can be fou nd in the electrical character istics section. ? p in the index o f th e current ly active sca n pin. writing to this bitfiel d ha s n o effect. 31 30 29 28 27 26 25 24 - - - - - pin[2:0] 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - presc[4:0] 7 6 5 4 3 2 1 0 - - - - - - - en 32058k avr32-01/12 114 at32uc3a 17.6 .5 external inte rrupt enable/disable/control name: en/dis/ctrl acces s type: en/d is : write-only ctrl: read-only th e b i t interpretation is r egiste r specifi c: ? en 0: no ef fect 1: interr upt is enabled ? dis 0: no ef fect 1: interr upt is disabled ? ctrl 0: interr upt is disabled 1: interr upt is enabled 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - nmi 7 6 5 4 3 2 1 0 int7 int6 int5 int4 int3 int2 int1 int0 32058k avr32-01/12 115 at32uc3a 18. f lash contro ller (flashc) re v: 2.0.0.2 18.1 features ? co n tro ls flas h bloc k w i t h du al rea d po rt s all o w i n g sta g ger e d r ead s. ? suppor ts 0 and 1 wa it state bus access. ? allows interleaved burst reads fo r systems with on e wa it state, outputti ng one 32-bit word per clock cycle. ? 32 -bit hsb interface fo r r eads fr om flash array an d writes to page buffer. ? 32 -bit pb interface for issuing comma nds to and configuration of the controller. ? 16 l ock bi ts, eac h protecting a reg ion consisting of (total nu mber of pag es in the flash bloc k / 16 ) pages. ? regions can be ind i vidu all y protec te d o r u npr ote cte d. ? additiona l protection of th e bo ot loader pages. ? suppor ts read s an d writes of general-purp ose nvm bits. ? suppor ts rea d s an d writes o f ad di tion al nv m pag es. ? suppor ts device protection throug h a securi ty bit. ? dedicated co mmand for chip-erase , firs t erasing all on-chip volati le memo rie s befo r e e ra si ng flash and clearing s ecurity bit. ? interf ace to po wer manager fo r power-dow n of flash-blocks in sle ep mode. 18.2 description t h e fla s h co ntro ll e r (fla sh c ) inte rfac es a fl ash block wi t h th e 32- bit in te rna l h sb bu s. pe rfor- mance fo r uncached systems wi t h high clock-fr equency and one wait st ate is increased by placi ng word s wit h sequential addres ses in alternating flash subblocks. having one read inter- f ac e p e r s u bbl ock a llo ws the m t o be r ead i n pa r al lel . whil e da t a f rom one fla sh s ubblo ck i s b ei ng ou tpu t o n t h e b us, th e s equent ial addr es s i s be ing read from the other flas h su bbl o ck and will be ready in the next cloc k cycle. th e controller also manages the programming, erasing, lockin g and unlocking seque nces with dedicated commands. 18.3 pr oduct dependencies 18.3.1 pow e r m anageme nt the hflash c has two bus c l ocks connected: o ne high speed bus clock (clk_flashc_hsb ) and on e peripheral bu s clock (clk_flashc_pb). these clocks are generated by the power manag er. bot h clocks are tu rned on by d efaul t, but the user h as to ensur e tha t clk_ flashc_hsb is no t tu rned of f b e for e rea din g t he flash or writ in g t he pa ge- buffer and that clk_ flashc_pb is no t turne d of befor e accessing the fl ashc configuration an d contro l registers. 18.3 .2 interrupt th e flashc interrupt li nes ar e connected to intern al sour ces of th e interrupt controller. using fl ashc interrutps requires t he interrupt controlle r to b e programmed first. 32058k avr32-01/12 116 at32uc3a 18.4 functional description 18.4.1 bu s interfaces th e flashc has two bu s interfaces, on e high-spe ed bus (hsb) interface for read s from the flash arra y and writes to th e page buffer, and one peripheral bu s (pb) interface for writing command s an d contro l t o an d reading stat us from the controller. 18.4.2 memory organization to maxi mize perfo rmance for high clock-fr equency systems , flashc interfaces to a flas h bloc k with two r ead ports . the flash bloc k has sever al parameters, given by the design of th e flash bloc k. refer to th e ?memories? chapter for t he device-specific values of th e parameters. ? p page s (flash_p) ? w wor ds i n eac h pag e an d i n th e pag e b uffe r (flash _w) ? pw words in total (flash_pw) ? f general-purpose fu se bits (flash_f) ? 1 secu r ity fuse bit ? 1 user page 18.4.3 us er page th e user pag e is a n addition al page, outside the regula r flash array, that ca n be used t o store vari ous data, like calibration data and seri al number s. this pag e is not eras ed by regular chip erase. the use r p age c a n only be writ ten an d erased by proprietary commands. read a ccesses to t h e use r p ag e is p erfo rme d just a s any o the r rea d ac ce ss to the fl ash . t h e addr ess ma p of th e use r pa ge is giv en in figure 18-1. 18.4 .4 re ad operations th e flashc pro v ides tw o different read mode s: ? 0 wa it stat e (0ws) for clock freque ncies < (access ti me of th e flas h plus the bus delay) ? 1 wa it stat e (1ws) for clock freque ncies < (access ti me of th e flas h plus the bus delay)/2 higher clock frequencies that would require more wait sta t es are not supported by the flash controll er. the programmer ca n select t he wait stat es require d by writing to th e fws field in t he flash con t rol regis t er (fc r) . i t is t h e responsi b ility of the programmer t o s e lect a nu m be r o f w ait states compatible with t he clock frequen cy and timing characterist ics of the fl ash block. in 0ws mo de, only one of the two flash read port s is accessed. the other flash read port is i dle. in 1 w s mode, both fl as h r ea d port s ar e active . on e re a d por t rea din g th e add ress ed word , and the othe r readin g th e ne xt sequential word. if the clock fre q uency allo ws, the user should use 0ws m o de, because this giv e s the lowest powe r consumption for low-freque ncy syst ems as on ly on e flash read port is read. using 1w s mod e has a power/perform ance ratio approaching 0ws m o de as the clock frequency approaches twice th e max frequency of 0w s mode. using two flash read port s use twice the power, bu t also give twice th e performance. 32058k avr32-01/12 117 at32uc3a th e flas h controller supports flash bloc ks wit h up to 2^21 wor d addresses, as displ ayed in fig- ur e 18-1 . reading th e memory spac e between address pw a nd 2^2 1 -1 return s a n u nd efined result . th e user pa ge is permanently mapped to wor d addr ess 2^21. figur e 18-1. memory map for the flas h memories 18.4.5 quick page read a d edicate d comman d, qu ick page read (qpr ), is provided to r ea d al l wo rds in an addresse d page. all bits in a ll word s in this pag e ar e and?ed together, returnin g a 1-bit result. this re sult is placed in t he quick page read result ( qprr) bit in flash s tat us register (fsr). t he qpr co mmand is useful to check that a page is in an erased state. the qp r instru ction is much faste r than performing the erased- p age ch eck using a regu lar software subroutine. 18.4 .6 writ e page buffer operations the inte r nal memory area rese rved f or the embedded flash ca n also be wr itten through a write- only page buffer. t he page buffer is a ddressed only by the address bi ts require d to address w word s (since t he page buffe r is wor d addressable ) and thus wr ap aroun d within the internal memory are a addr ess spac e a nd appea r t o be repeate d within it. when wri ting to th e page buffer, t he pagen fi eld in t he fcmd register is updat ed with the page number correspondin g to page address o f th e latest word written into the page buffer. tabl e 18-1. us er row addresses memory type star t address, by te sized size mai n array 0 pw wo rds = 4pw bytes user 2^23 = 8388608 128 words = 512 bytes 0 pw -1 pw 2^21+128 unused flash data array u nused u ser page f lash w ith ex tr a page 2^21 a ll addresses are w or d addresses 32058k avr32-01/12 118 at32uc3a th e pag e buffer is als o use d fo r writ es to th e user page. write operatio ns ca n be prevented by programming the memory protection unit o f the cpu. writ in g 8-b it and 16-bit d a t a t o th e pa ge bu ffe r is n ot a l lo we d an d ma y l e a d to unpr edict abl e data corruption. pag e buffe r write operation s ar e performed wit h 4 wait states. writin g to th e pag e b uffer can on ly chan ge page b uffer bits fr om one to zer o, ie writing 0xaaaaaaaa to a page b u ffer location that has the val ue 0x00000000, will not change the page buf fer value. the only way to change a bit f rom zero t o one, is t o rese t the ent ire page buffer w it h the c lear pag e buffer command. the pag e buff er is not automat ically reset af ter a page writ e. the programmer should do this manua lly by issuin g th e clear page buffer flas h command . th is can be done after a page w rite, or befor e t h e p age b uff e r is l o ade d with da ta t o b e store d to th e flash pag e. exam ple: w ritin g a wo r d in to word ad dress 13 0 of a fl ash with 1 2 8 words in the p a ge buffer. pagen will be updated with the value 1, and t he word will be writ ten int o word 2 in t he page buffer. 18.4.7 writing wor ds t o a pag e t ha t i s n ot c omplet el y e ras ed this can be used for eeprom emu lat ion , i.e . w r it es wi th granularity of on e word instead of an entire pa ge. only word s that ar e in an completely erased state (0xffffffff ) can be changed. t he procedur e is as follows: 1. clear page buffer 2. write to th e page buffer th e resu lt of the logical bitwis e and operatio n between the con tents of th e fl ash pa ge an d t he new data t o write . on ly wo rd s tha t we re in a n er ased stat e ca n be cha nge d fro m th e o r igin al page. 3. write page. 18.5 f lash commands th e fl ashc offers a com mand set to manage programm ing of the fl ash memory , lock ing and unlocking of regions, and full flash erasing. see c hapter 18.8.3 for a compl ete list of com mands. to run a command, t he field cmd of the fla s h command regist er (fcmd) has t o be written wit h the comman d number. as soo n a s th e fcmd regist er is written , t he frdy flag is auto- ma tically cleared. once th e current comma nd is complete , the frdy fl ag is automaticall y set. if an interrup t ha s been enable d b y setting th e bit frdy in fcr, the interrupt lin e o f the flash contr oller is a c tiva ted. a l l f la s h comman ds exc ep t fo r qu ick p a ge r ea d ( qp r ) wi ll gene ra te an inte rr upt re quest up o n comp letio n if frdy i s set. afte r a comm an d h as b ee n writte n t o fc md , th e p rog rammi n g algor ithm shou ld wait un til th e command has been executed be f ore attempti ng to re ad instruct ions or dat a from the fl as h or writin g to the page buffer, as the fl ash will be busy. the waiting can be performed e i ther by polling t he flash stat us register (fsr) or by waiting for the fl ash ready interrupt. the com- ma nd written to fcmd is ini tiated on the firs t clock cycle where the hsb b u s interf ace in fl ashc is idle. the use r must mak e sure tha t th e a cce ss p atte rn to t he fl ashc hsb inte r- fa ce contai ns an idle cycle so tha t t he comman d is allowed to start. make su re that no bus master s suc h as dma con t rollers are perf orming en dless burst transfers from the flash. also, make sur e tha t t he cpu does no t perf orm end less burst transfers f rom flash. this is d one by 32058k avr32-01/12 119 at32uc3a letting t he cpu enter sleep mode after writing to fcmd, or by po lling fsr for command com- pletion. this polling will result in an a ccess pattern w ith idle h sb cycles. all the commands are protec t ed by t he same keywor d, which has to be written in t he eight highest bits of the fcmd register . writing fcm d w it h data tha t does no t c o nt ain the c o r r e c t key and/o r wit h an inva lid comma nd ha s no effect on the flash memory ; however , th e proge flag is s e t in t he flash s t atus regist er (fsr). this flag is au t omatically cle ared by a read access to the fsr regis ter. writing a comman d to fcmd whil e a not her command is b eing execut ed ha s no effect o n the flash memory; however , the prog e flag is se t in the flash statu s registe r (fsr). this flag is automati cally cleared by a rea d acce ss to the fsr register. if t he cur rent com m an d wr ites o r era ses a p a ge in a locked r egion , o r a pag e pr otect e d by the bootprot fuses , t he comman d ha s n o effe ct on th e flas h memory; however, the locke flag is se t in the fsr registe r . this flag is au t omatically cleared by a read access to the fsr re g is te r. 18.5 .1 write/erase page operation flash technology requires that an erase must be don e before programming. th e entire flash can be e rase d by an eras e all comma nd. alternat ively, pag es can be individually er ased by t he er ase page command. th e user pag e can be writte n an d erase d usin g th e mechanisms descr ibed in this chapter. afte r programmin g, th e page can be locke d to prevent miscellaneo us writ e o r erase sequence s. locking is pe rformed on a p er-region ba sis, so lockin g a region lo cks all pages inside th e regi on. additio nal protection is pr ovided fo r the lowerm ost add ress sp ace of the flash. this a ddr ess space is allocated for t he boot loader, and is pr otected both by t h e lock bit(s) correspondin g to th is addr ess space, and t he bootprot[2:0] fuses. data t o be wr itte n ar e stor ed in an inter nal bu ffe r calle d p ag e buffer. t he pa g e buff er contains w word s. the page buff er wrap s around within the intern al memory area addre ss space and appears t o be repeat ed by t he number of pages in it . writing o f 8-bit and 16 - bit data t o the pag e buffer is not allowe d an d ma y lead to unpredictab le dat a corruption. data must b e written to the page buffer befor e th e programming command is wri tten to the flas h command register fcmd. th e sequence is as follows: ? reset th e page buffe r with th e clear pag e buffe r command. ? f ill the page buff er with the desired contents, using only 32-bit access. ? programming starts as soo n a s th e programming key and th e programm ing command are w ritte n to th e fla sh co mm and registe r. the page n fie l d i n th e fla sh command reg ister (fcmd) m ust contai n th e addres s of th e page t o write. page n is automatically updated when writin g to th e page buffer, but ca n also be written to directly. th e frdy bi t in the flash stat us registe r (f sr) is automatica lly cleared when the page writ e operatio n starts. ? when programming is co mpleted , t he bit frdy in t he fl ash status registe r (f sr) is set. if an interrupt wa s enabled by setting the bi t frdy in fcr , the interrupt line of the flash controller i s set. tw o e r rors ca n b e de te cte d in th e fs r re gister afte r a progra mm i ng sequ enc e: ? programming error: a bad keywor d and/o r a n inva lid comman d hav e been writt en in the fcmd regis ter. 32058k avr32-01/12 120 at32uc3a ? loc k error: t he page to be programme d belo ngs t o a locke d region . a command must be executed to unlock th e correspondin g region befor e programmin g can start. 18.5 .2 erase al l operation the entire memory is erased if th e er ase all comman d ( ea) is writte n to t he flash command registe r (fcmd). erase all e r ases all bits in the flas h array. th e user pa ge is not erased. all fl ash memory locations , th e general-purpose fuse bits, an d t he securit y bi t ar e er ased (reset to 0xf f ) afte r an e r ase all. the ea command also ensures th at all volatile memorie s , such a s register file a nd rams, are erase d before t he securi ty bit is erased. er ase all operati on is allowed on ly if no region s are locked, an d th e boot prot fuses are p rogra m me d wit h a regi o n s ize o f 0 . thu s , if at lea s t on e regio n i s loc k ed, th e b i t lo ck e i n fsr is se t and t he command is cancell ed . if th e bit locke has been writte n t o 1 i n fcr , the interrupt line rises. when the command is c omplete, th e bi t frdy bi t in th e flash stat us registe r (fsr ) is se t. if a n i n te rru pt ha s bee n enabled b y s e t tin g t he bi t fr dy in fcr , the int errup t l in e o f the flash controller is se t. tw o errors ca n be detected in th e fsr registe r afte r issuing the command: ? programming error: a bad keywor d and/o r a n inva lid comman d hav e been writt en in the fcmd regis ter. ? loc k error: at least one lock region to b e erased is p rotected, or bootpro t is different fro m 0. t he erase command has been refused and no page ha s been erased . a clear lock bit command mu st be execute d previously to unlock th e corresponding lock regions. 18.5 .3 re gion lock bits the fl ash block has p pages, and thes e pages are group ed int o 16 lock regions, each regio n containing p/ 16 pages. each r egion ha s a dedicated lock bi t preventing writing and erasing page s i n th e r egi on . after p roductio n , t h e device may ha ve som e reg ion s lo cked. t h ese lock ed regions a re reserved fo r a bo ot or defa ult application. locke d regi ons ca n b e unlocke d t o be erase d and the n programmed wit h another applicat ion or other data. to l o ck o r unlo ck a re gion , the c omman ds loc k r e gio n c ont ainin g pag e (lp ) and u nl ock regi on containing pa ge (up ) ar e provided. writ ing on e o f th ese commands , together with the numbe r of th e pa ge whos e regi on sho uld be locked/unlocked, performs the desire d operation. on e erro r can be det ect ed i n the fs r re giste r after issuing t he command: ? programming error: a bad keywor d and/o r a n inva lid comman d hav e been writt en in the fcmd regis ter. the l ock bits ar e implement ed using the lowest 16 general-purp ose fus e bits. th is me ans that lock bi ts ca n al so be set/cleared using t he commands for writing/erasin g general-purpose fuse b its, s e e ch ap t e r 18. 6. t he ge n er al- p urp o se bi t b ein g i n a n e rase d ( 1) s tate m ean s t ha t t h e region is unlocked. th e lowermos t page s in th e flash ca n addit i ona lly be protecte d by t h e bootprot fu ses, see section 18.6. 18.6 g eneral-purpose fuse bits each fl ash block h a s a num ber of g eneral-pu rpose fuse bits that the a pplication prog rammer can use freely. the fu se bits ca n be written a nd erase d us ing dedicated commands, and read 32058k avr32-01/12 121 at32uc3a thro ugh a dedica ted peripheral bus addr e ss. som e of the general-purp ose fuse bits are reserved fo r special purposes, and shoul d not b e u sed for o the r functions.: th e bootpro t fuse s protects the follo wing addr ess space fo r th e boot loader: to e ras e o r writ e a general-purpose fus e bit, t he commands wr ite general-pur pose fuse bit (wgpb) and erase general-purpose fuse bit ( e gpb) are provided. writing o ne of these tabl e 18-2. general-purp ose fu ses wit h special functions general- purp ose fuse number name usage 15:0 lock regi on lock bits. 16 epfl extern al privileged fe tch lock . used to prev ent the cpu from fetching instructions from extern al memori es when in privileged mode . this bi t can only be chang ed when th e security b it is cleare d. the address rang e corresponding to external memorie s is d e vice- sp e cific, an d n ot kno w n t o t h e fl ash control l er . th is fuse b i t is simply routed ou t of the cpu or bu s system, the fla s h contro ller does not treat this fuse in any special way, except that it ca n no t b e a ltered when th e security bit is set. if t h e securi ty bit is set, on ly an external jtag chip erase can clea r epfl. no i ntern al comma nds can alter epfl if t he securi ty bit is set. wh en th e fuse is erased (i.e. "1 "), the cpu can execute instructions fetched from external memories . when th e fuse is programmed (i.e . "0"), instru ctions can no t be executed from external memories. 19:17 bootprot used to select one of f our different bootloa der sizes. pages include d in th e bootloa der area ca n no t b e erased or programmed except by a j tag chip erase. bootprot can only be change d when the secur ity bi t is cleared. if t h e securi ty bit is set, on ly an external jtag chip erase can clea r bootprot , an d thereb y allo w th e p ages protected by bootprot to be pro grammed . no intern al command s can alter bo otprot or th e page s protected by bootprot if t he securi ty bit is set. tabl e 18-3. boot load er area specifie d by bootprot bootprot page s protected by bootprot size of p rotected memory 7 none 0 6 0-1 1kbyte 5 0-3 2kbyte 4 0-7 4kbyte 3 0-15 8kbyte 2 0-31 16kb yte 1 0-63 32kb yte 0 0-127 64kb yte 32058k avr32-01/12 122 at32uc3a c omm ands , t oget her wit h th e numb er of t h e fuse t o writ e/erase , perfo rm s t he desi red operation. an entire general-pur pos e fus e by te can be wri tt en at a time by using th e prog ra m gp fuse by te (pgpfb) instruction. a pgpfb to gp fuse byte 2 is not allowed if the flas h is lo cked by t he security bit. th e pf b comman d is issued wit h a parameter in the pagen field: ? pagen[2 :0 ] - byt e to write ? pagen[10:3] - fuse value t o write all general - p urpose f u ses c a n b e erase d b y the e rase al l g e neral-purp ose fu s e s (ea gp) command . an eagp command is no t allowe d if the fl ash is locked by th e security bit. two e rro rs ca n b e detect ed in the fs r register after issuin g th ese commands: ? programming error: a bad keywor d and/o r a n inva lid comman d hav e been writt en in the fcmd regis ter. ? loc k error : a write or eras e of an y of th e special-function fuse bits in ta ble 18-3 was att empted while th e fla sh is l ocked by the security bit. the l ock bits ar e implement ed using the lowest 16 general-purp ose fus e bits. th is me ans that the 16 lowes t general-purpose f use bits can also be writ t en/erased using t he commands for locking/unlockin g regions, see secti o n 18. 5.3. 18.7 s ecurity bit the security bit allows the entire chip to be locked from extern al jtag or other debug access fo r code security. the secu rity bit ca n be written by a dedicate d command , set secu rity bit (ssb). once set, the on l y way to clear the security bit is through the jta g chip erase command. once the security bit is set, the fo ll owing fl ash control ler commands will be unavail able and retur n a lock erro r if attempted: ? write gene ral- pur pos e f u s e bit ( wgpb) to bootprot or epfl fuses ? er as e gener al- pur pos e fu se bit (egpb) to bo otprot or epfl fuses ? progr a m general-purp ose fus e byt e (pgpfb ) o f fus e byt e 2 ? era se all general-pur pose fuses (eagpf) on e erro r can be det ect ed i n the fs r r egis te r afte r issuing t he comm an d: ? programming error: a bad keywor d and/o r a n inva lid comman d hav e been writt en in the fcmd regis ter. 32058k avr32-01/12 123 at32uc3a 18.8 u ser interface 18.8.1 addres s map the followin g addresses ar e used by the flashc. all o ffset s are relative to the base address allocated to the fl ash controller. (*) t he va lue o f th e lo ck bi ts is de pe nden t o f thei r progra mme d state . all o the r bi ts in fsr are 0. all bi ts in fg pfr and fcfr ar e dependent on the programmed state o f the fuses they map to. any bi ts in th ese register s no t mapped t o a fu se re ad 0. tabl e 18-4. flash controller registe r mapping offset register name access reset state 0x0 f lash contro l register fcr r/w 0 0x4 f lash command register fcmd r/w 0 0x8 f lash status register fsr r/w 0 (*) 0xc f lash ge neral purp ose fu se regi ster hi fgpfrhi r na ( *) 0x10 f la sh ge n e r a l pu rpo s e fu s e r e gi s t e r lo fg pfr lo r na ( *) 32058k avr32-01/12 124 at32uc3a 18.8.2 flas h contro l registe r (fcr) offset: 0x0 frdy: flash ready interrupt enable 0: fla s h rea dy do es not generat e a n inte rrupt. 1: flash read y generate s an interrupt. locke: l o ck erro r interr upt enable 0: lo ck error d oes not generat e an interrupt. 1: lo ck error generate s an interrupt. proge: programming err or interrupt enable 0: programmin g error d oes no t generat e a n interrupt. 1: programmin g erro r generates an interrupt. fw s: flas h w ait s ta te 0: the flash is r e ad wit h 0 wa it states. 1: the flash is r e ad wit h 1 wa it state. sasd : sense am p l ifier sam ple disable 0: the se nse amplifie rs in the fl ash ar e in samp ling mode. 1: the se nse amplifie rs in the fl ash ar e permanentl y enabled. consumes mor e power. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - sasd 7 6 5 4 3 2 1 0 - fws - - proge locke - frdy 32058k avr32-01/12 125 at32uc3a 18.8.3 flas h comma nd register (fcmd) offset: 0x4 the fcmd can not be w rit ten if the flas h is in t he proce ss of pe rforming a flash command. doing so will cause the fcr wr ite to be ignored, and the pr oge bit to be set. cmd: com ma nd this field defin es the flash co m mand. i ssuing a n y unused comman d will cause th e program- min g error flag t o be set, and t he correspondin g interrup t to be request ed if th e prog e bit in fc r is se t. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 pa gen [15:8] 15 14 13 12 11 10 9 8 page n [7:0] 7 6 5 4 3 2 1 0 - - cmd tabl e 18-5. set of commands command value mnemonic no o peration 0 nop writ e page 1 wp erase page 2 ep clear pa ge buffer 3 cpb lock regi on containin g given page 4 lp unlock re gion cont a ini ng gi ve n p age 5 up eras e all 6 ea w r i t e g en era l-p u rp os e fus e bit 7 wg pb eras e general-purp ose fuse bit 8 egpb set secu ri ty bit 9 ssb program gp fuse byte 10 pgpfb eras e all gpfuses 11 eagpf quick pa ge read 12 qpr writ e user page 13 wup eras e us er pa ge 14 eup quick pa ge read user page 15 qprup 32058k avr32-01/12 126 at32uc3a pagen: page number th e pag en fie l d is use d t o address a p ag e or fus e bi t fo r certai n operations. in orde r to sim- plify pro gramming , the page n fiel d is automatically updated eve ry time the page bu ffer is written t o. for every page buf f er write , t he pagen fi eld is upda ted wit h the pag e n umber of the addre ss being written to. ha rdware automatic ally masks wr ites to the pagen fi eld so that only bits representing v a lid page number s can be writte n, all ot her bits in pagen are always 0. as an e x ample, in a flash wi th 1024 pages (page 0 - page 1023), bi ts 15:10 will always be 0. k ey : w rite pr ot e ction k ey th is fiel d should be written with the value 0xa5 t o enab le th e command defined by t he bits of th e reg ist er . i f th e fi el d is writte n with a different value , t h e writ e i s n ot perfo rme d an d no act ion is sta rted. this fiel d alwa ys re ads as 0. tabl e 18-6. semantic of pag en fi e l d in different commands command pa gen description n o operati on no t us ed write page the numb er of the pa ge t o write clear pa ge buffer not used lock regi on containin g given page page number wh ose regi on shou ld be locked unlock region containi ng given page page number wh ose regi on shou ld be unlocked erase all n ot used w r ite g ene r a l-purp os e fu se bit g pfus e # eras e general-purp ose fuse bit g pfuse # set secu ri ty bit n ot used program gp fuse by te writed ata[7:0], byteaddress[2:0] erase al l gp fuses n ot used quick pa ge read page number writ e user page not used eras e user page not used quic k pa ge rea d user page not used 32058k avr32-01/12 127 at32uc3a 18.8.4 fla s h stat us r egis t e r (f s r) offset : 0x08 frdy: f lash rea dy status 0: th e flas h controller is b u sy and th e applicatio n mu st wait before runnin g a new command. 1: th e flas h controller is r eady to ru n a ne w command. locke: l o ck erro r status autom atic all y c leare d whe n fsr is rea d. 0: n o programmin g of a t le ast on e locke d lock regio n ha s happen ed since the las t r ead of fsr. 1: programmin g of at least o ne locked lo ck region has ha ppened since the last rea d of fsr. proge: pr ogr ammi ng err or sta tus automatica lly cle are d whe n fsr is read. 0: no in valid comma nds and no bad keywo r ds wer e writt en in t he flash comman d register fcmd. 1: an inva lid c omm a nd and/o r a b a d ke ywor d was/we re writt en in th e flash comm and regis- te r fcmd. securit y: securi t y bi t st at us 0: th e securi ty bit is in active. 1: th e securi ty bit is active. qprr: q uic k page rea d result 0: th e result is zero, i.e. th e page is n o t erased. 1: th e resu lt is one, i. e. th e page is erased. autom atic all y c leare d whe n fsr is rea d. 31 30 29 28 27 26 25 24 lock1 5 lock1 4 lock13 lock1 2 lock11 lock10 lock9 lock8 23 22 21 20 19 18 17 16 lock7 lock6 lock5 lock4 lock3 lock2 lock1 lock0 15 14 13 12 11 10 9 8 fsz - - - - 7 6 5 4 3 2 1 0 - - qpr r s ec urity prog e lo ck e - f r dy 32058k avr32-01/12 128 at32uc3a fsz: flas h size the si ze of t he flash . not al l de vic e fami l ie s w ill provide all flash si zes indica ted in the table. l o ck x : lo ck r e gio n x lo c k stat us 0: the corresponding lock region is not locked. 1: the corresponding lock region is l ocked. tabl e 18-7. flas h size fsz flash size 0 3 2 kbyte 1 6 4 kbyte 2 128 kbyte 3 256 kbyte 4 384 kbyte 5 512 kbyte 6 768 kbyte 7 1 024 kbyte 32058k avr32-01/12 129 at32uc3a 18.8.5 fla sh ge n era l p ur po se f us e register hi gh (fg pfrhi) offset : 0x0c this register is o n ly used in system s wit h more than 32 gp fuses. gpfxx : general purpo se fus e xx 0: the fus e has a written/programm ed state. 1: the fuse h as an erase d stat e. 31 30 29 28 27 26 25 24 gpf63 gpf62 gpf61 gpf60 gpf59 gpf58 gpf57 gp f56 23 22 21 20 19 18 17 16 gpf55 gpf54 gpf53 gpf52 gpf51 gp f50 gp f49 gp f48 15 14 13 12 11 10 9 8 gpf47 gpf46 gpf45 gpf44 gpf43 gp f42 gp f41 gp f40 7 6 5 4 3 2 1 0 gpf39 gpf38 gpf37 gpf36 gpf35 gp f34 gp f33 gp f32 32058k avr32-01/12 130 at32uc3a 18.8.6 flas h genera l purp ose fu se register lo w (fgpfrlo) offset : 0x10 gpfxx : general purpo se fus e xx 0: the fus e has a written/programm ed state. 1: the fuse h as an erase d stat e. 31 30 29 28 27 26 25 24 gpf31 gpf30 gpf29 gpf28 gpf27 gpf26 gpf25 gp f24 23 22 21 20 19 18 17 16 gpf23 gpf22 gpf21 gpf20 gpf19 gp f18 gp f17 gp f16 15 14 13 12 11 10 9 8 gpf15 gpf14 gpf13 gpf12 gpf11 gp f10 gp f09 gp f08 7 6 5 4 3 2 1 0 gpf07 gpf06 gpf05 gpf04 gpf03 gp f02 gp f01 gp f00 32058k avr32-01/12 131 at32uc3a 32058k avr32-01/12 132 at32uc3a 19. hsb bus matrix (hmatrix) re v: 2.3.0.1 19.1 features ? use r inte rface on p eri phe ral b us ? configurab le number of m aster s (up to sixteen) ? configurab le number of slav es (up to sixteen) ? one de coder for each master ? three dif f erent memory mappings fo r each mast er (interna l and external boot , remap) ? on e remap function fo r each master ? programmabl e arbitration fo r each slave ? ro un d-robin ? fixed priority ? programmabl e default master fo r each slave ? n o default ma ster ? l ast accesse d default master ? fixed de fault master ? one c y cl e latenc y f o r th e fi rst ac ces s of a b ur st ? zero cycl e latency fo r defaul t master ? on e sp ecial function register fo r each slav e (n ot dedicated) 19.2 description th e bus m atrix impleme nts a multi-la yer bus structu re, that en ables parallel access p aths betwe en mult iple high speed bus (hsb) mast ers an d slaves in a system, thus increasing the overall bandwidth. the b u s matr ix interconnect s up to 16 hsb m aster s to up to 16 hsb slaves . the no r mal lat ency to connect a master t o a slave is o ne cycle excep t f or th e default mast er of t he a ccess e d slav e wh ic h i s co nn ec te d dir ect ly (zer o cycle la tency) . th e bus m atr ix provid es 16 special func tion register s (sfr ) t hat allo w th e bu s m a trix to sup por t a pplicatio n specific features. 19.3 memor y mapping th e bus matr ix provides one decoder for every hsb mas te r int erf ace. th e de code r offe rs e ach hsb mas ter several memo ry mappings . in fact, depending on the product, ea ch memo ry area may be assig ned to severa l slaves. booting at the same addr ess wh ile using differe nt hsb slaves (i .e. extern al ram, internal ro m or intern al flash, etc. ) becomes possible. t he bus matrix user interfac e provides master rema p contro l register (mr cr) that performs rema p action for ever y mast er independently. 19.4 s pecial bus granting mechanism th e bus matr ix provides some speculat ive bus granting techniqu es in order t o anticipate access requests from some masters. this mech an ism reduces latenc y at firs t access of a b urst or single transfer. this bus granting mechan ism sets a di fferent default master fo r ever y slave. at the end o f the curren t access, if no other request is p ending , the slave rema ins connect ed to its associated defau lt master. a slave can be associat ed wit h thre e kin ds of defaul t master s: no default master , last acce ss maste r and fi xed default master. 32058k avr32-01/12 133 at32uc3a 19.4.1 no d efaul t master at the end of the c urrent acce ss, if no other request is pending, the slave is disconnected from all ma st ers. no defaul t master su its low-power mode. 19.4.2 last acces s master at the end o f the curren t access, if no other request is p ending , the slave rema ins connect ed to t he last master that performe d an access request. 19.4.3 fixed defaul t master at th e end of t he curren t access, if n o other requ est is pending, th e slave connects to its fixed defaul t m ast er. unlik e l ast access m a ster , th e f i xe d mast e r do e s n ot cha n g e unles s t h e us er modifie s it by a softwar e action (field fixed_defms tr of th e related scfg). t o cha ng e from on e kin d o f de fault maste r t o an ot her , th e bu s matr ix user in te rf ace provides the slave configuration registers, one fo r each slave , tha t se t a default master for each slave. the slave c onfiguratio n register contains two fields: defmst r_type and fixed_defmstr. th e 2-bit defmstr_ type fi eld selects the default mast er ty pe (no default , las t acces s master , f ixed default master), whereas the 4-bi t fixed_defmstr fi eld select s a fixe d default master pro- vided that defmstr_type is se t to fixed d efault master. please refer to t he bus matr ix user interf ace description. 19.5 arbitration th e b us m a t r ix p r ovi des a n arbitra ti o n mecha nism t h at red uce s la t en c y wh e n conflic t cas es occur, i.e. when tw o or more masters tr y t o access the same slave at th e sa me time . o ne arbiter pe r hsb slave is provided, t hus arbitrati ng each slav e differently. the bu s matrix provides the user wi th the poss ibility of choosing betw een 2 arbitration types for each slave: 1. round-robin arbitratio n (default) 2. fixe d priori ty arbitration this choice is mad e vi a th e fi eld arbt of th e slav e co nfiguratio n registers (scf g). each algorit hm ma y be complemented by selecting a default master configuration for each slave. whe n a re -a rb i tratio n m u st be do ne , specif ic condi tions apply. see section 19.5. 1 ?arbitration rules ? o n pa ge 133 . 19.5 .1 arbitratio n rules eac h arbit er has th e ability t o arbitrat e betwee n two or mor e differe nt maste r requests. in o rder t o avoi d burst breakin g an d also to p rovide the maximu m th roughput for sla ve in terf aces, arbitr a- ti on may only tak e pl ace during th e following cycles: 1. idle cycles: when a sl ave is n o t connecte d to any master or is connected to a m aster which is not currently ac cess ing it. 2. sing le cycles : wh en a slave is cur r en tly do ing a sin g le access. 3. en d of burs t cycles: when the current cycle is the la st cycle of a burst transfer. for define d length burst, p r edict ed e nd of bu rs t m atche s t h e s i ze of t h e t r ansfe r but is man- age d differently fo r undefin ed length burst. se e sectio n ?19.5.1.1? on pag e 134. 32058k avr32-01/12 134 at32uc3a 4. slot cycle limit: when t he slot cycle c ounte r has reached t he limit valu e indicating that t he current master access is t o o long and mu st b e broken. se e sectio n ?19.5.1.2 ? on pag e 134. 19.5.1.1 undefined length burst arbitration in orde r to avoid long slave ha ndling during undefine d l eng t h bur sts (incr), the b us matrix pro- vides specific logic in orde r t o re -arbitrat e before the end of the in cr transfer. a predicte d end of burst is used as a defin ed length burst transfer and can be selected from among the following five possibilities: 1. infinite: no predicted end of bu rst is gene r ated and there f ore incr bu rst transfer will neve r b e broken. 2. on e be at burs ts: p r edicte d e n d o f bu rst is ge nerate d at ea ch sin gle transfer insi d e the incp transfer. 3. fou r beat bursts: predicte d en d of bu rst is generate d at th e end of each four beat boundar y ins ide incr transfer. 4. eigh t beat bursts: predicte d end of burs t is generate d a t th e en d of e ach eight beat boundar y ins ide incr transfer. 5. sixteen beat bursts: predicted end of burst is generated at th e en d of ea ch sixtee n beat boundar y ins ide incr transfer. th is selection ca n be do ne through th e field ulbt of the m a ster configuration registers (mcfg ). 19.5.1.2 slot cycle limi t arbitration th e bus matrix contains specific logic t o break lon g accesses , such as very lon g bursts on a v e r y sl o w sl a ve ( e .g ., an e x ternal lo w speed mem ory ). at the beginn i ng of t he bu rst a cce ss , a counter is l oaded wi th the valu e previously written in th e slot_cycle fiel d of the related slave configuratio n register (scfg) and decreased a t each clo ck cy cle. when the counte r reaches z e ro, t h e arb it e r h as the abilit y t o re-arbi t ra t e at the e n d o f t he cur r en t by t e, h alf w o r d o r w o r d transfer. 19 .5.2 round-r obin arbit r at ion t his algor i th m allo ws the b u s m a tri x arb i ter s t o d i spatc h t he r eques ts f ro m d iff e ren t m aste rs to t he sa me slave in a r ound-robin manner . i f two o r more mast er requests ar ise a t t he sa me time, the master with the lowest number is first serviced, then the othe rs ar e serviced in a r ound-robin manner. ther e ar e thre e round-robi n algorithms implemented: ? r ound-robi n arbitrat ion withou t default master ? round-robi n arbitrat ion wit h last default master ? round-robi n arbitrat ion wit h fixe d defaul t master 19.5.2.1 round-robin arbitratio n without default master this is t he ma i n algorith m use d by b us matr ix arbiters . it allo ws th e b us matr ix t o dispatch requests from different mast ers to the same slav e in a pure round-robin manner . a t the en d of the current access , i f no other requ es t is pen din g, the slave is disc o nnected from all masters. this con figurat ion incu rs one lat ency cycle for the first ac cess of a bu rst. arbitratio n without default master ca n be used for masters that perfor m significant bursts. 32058k avr32-01/12 135 at32uc3a 19.5.2.2 round-robin arbitratio n with la st defaul t master this is a biased roun d- robin algorithm used by bu s ma t ri x arbiter s . i t allow s t he b us mat r i x t o remove the one lat e ncy cycle fo r the last master that acce ssed the slave. in fact , at the end o f t he current transfer, if no other maste r request is pending, th e slave re mains connected to the last master that performed the access. other non pri vi l eged maste r s stil l get one l a tenc y c ycl e if they wan t to acce ss t he sam e slave. this te chnique can b e use d fo r master s tha t mainl y pe rf orm sing le accesses. 19.5.2.3 round-robin arbitratio n with fixed default master thi s is anothe r bi ase d rou nd-robi n algo rithm . it allows the bus matrix arbite rs to remove the one latency cycle for the fixed defau lt master per slave. at t he end of the current acce ss, the slave rema ins connect ed to its fixed defaul t master . every request attempte d by this fi xed default mas- ter will not ca use any latency wh ereas other non privil eged masters w ill still get one latency cycle. this techniqu e ca n b e used fo r masters that main ly perform singl e accesses. 19.5 .3 fixe d priority arbitration t his algorithm allo ws t h e b u s m at ri x arb i ters t o di spa tch t he r eques ts fro m diff e r ent mas te rs to t he sa me slave by using t h e fixed priorit y def ine d by th e user . i f t wo or mor e maste r req uests are active at t he same time , the master with the highest priority numb er is serviced firs t. if two or mor e master req uests with the sam e priority are active at the same time, the maste r with the highest number is se rviced first. for e ach slave, the priority of each master may be defin ed throug h th e priority registers for slaves (pras and prbs). 19.6 sla ve and master assignation the in dex numbe r assigned to bus matr ix slaves an d masters a re describe d in memories cha pter. 32058k avr32-01/12 136 at32uc3a 19.7 u ser interface tabl e 19-1. register mapping offset register name access reset value 0x0000 m aster configurati on registe r 0 mcfg0 read/write 0x00000002 0x0004 m aster configurati on registe r 1 mcfg1 read/write 0x00000002 0x0008 m aster configurati on registe r 2 mcfg2 read/write 0x00000002 0x000c master confi gurati on registe r 3 mcfg3 read/write 0x00000002 0x0010 m aster configurati on registe r 4 mcfg4 read/write 0x00000002 0x0014 m aster configurati on registe r 5 mcfg5 read/write 0x00000002 0x0018 m aster configurati on registe r 6 mcfg6 read/write 0x00000002 0x001c master confi gurati on registe r 7 mcfg7 read/write 0x00000002 0x0020 m aster configurati on registe r 8 mcfg8 read/write 0x00000002 0x0024 m aster configurati on registe r 9 mcfg9 read/write 0x00000002 0x0028 m aster configurati on register 10 mcfg10 read/write 0x00000002 0x002c master confi gurati on regi ste r 11 mcf g 11 rea d / w r ite 0x 0 0 000 002 0x0030 m aster configurati on register 12 mcfg12 read/write 0x00000002 0x0034 m aster configurati on register 13 mcfg13 read/write 0x00000002 0x0038 m aster configurati on register 14 mcfg14 read/write 0x00000002 0x003c master confi gurati on regi ste r 15 mcf g 15 rea d / w r ite 0 x0 0 000 002 0x0040 slave configurati on registe r 0 scfg0 read/write 0x00000010 0x0044 slave configurati on registe r 1 scfg1 read/write 0x00000010 0x0048 slave configurati on registe r 2 scfg2 read/write 0x00000010 0x004c slav e configurati on registe r 3 scfg3 read/write 0x00000010 0x0050 slave configurati on registe r 4 scfg4 read/write 0x00000010 0x0054 slave configurati on registe r 5 scfg5 read/write 0x00000010 0x0058 slave configurati on registe r 6 scfg6 read/write 0x00000010 0x005c slav e configurati on registe r 7 scfg7 read/write 0x00000010 0x0060 slave configurati on registe r 8 scfg8 read/write 0x00000010 0x0064 slave configurati on registe r 9 scfg9 read/write 0x00000010 0x0068 slav e configurati on register 10 scfg10 read/write 0x00000010 0x006c slav e configurati on register 11 scfg11 read/write 0x00000010 0x0070 slav e configurati on register 12 scfg12 read/write 0x00000010 0x0074 slav e configurati on register 13 scfg13 read/write 0x00000010 0x0078 slav e configurati on register 14 scfg14 read/write 0x00000010 0x007c slav e configurati on register 15 scfg15 read/write 0x00000010 0x 00 80 p r i orit y reg ist er a fo r s lav e 0 p ras0 r e a d / w r i te 0x 0 00 0 0000 0x 00 84 p r i orit y reg ist er b fo r s lav e 0 p rbs0 r e a d / w r i te 0 x000 0 0000 0x 00 88 p r i orit y reg ist er a fo r s lav e 1 p ras1 r e a d / w r i te 0x 0 00 0 0000 32058k avr32-01/12 137 at32uc3a 0x00 8c pr io ri ty register b fo r s lav e 1 prbs1 r ead/wr ite 0x00 000000 0x00 90 prio r i t y re g ist er a for sl a v e 2 p ras2 read/write 0 x00 0000 00 0x00 94 prio r i t y re g ist er b for sl a v e 2 p rbs2 read/write 0x 0 00000 00 0x00 98 prio r i t y re g ist er a for sl a v e 3 p ras3 read/write 0 x00 0000 00 0x009c pr iori ty register b fo r sl av e 3 prbs3 read/wr ite 0x00 00 0 000 0x00a0 priori ty register a fo r slav e 4 pras4 read/write 0x00000000 0x00a4 priori ty register b fo r slav e 4 prbs4 read/write 0x00000000 0x00a8 priori ty register a fo r slav e 5 pras5 read/write 0x00000000 0x00ac priori ty register b fo r slav e 5 prbs5 read/write 0x00000000 0x00b0 priori ty register a fo r slav e 6 pras6 read/write 0x00000000 0x00b4 priori ty register b fo r slav e 6 prbs6 read/write 0x00000000 0x00b8 priori ty register a fo r slav e 7 pras7 read/write 0x00000000 0 x00bc prio r i t y re g ist er b for sl a v e 7 p rbs7 read/write 0x 0 00000 00 0x00c0 priori ty register a fo r slav e 8 p ras8 r ead/wr ite 0 x00 00 0 000 0x0 0c4 priori ty register b fo r slav e 8 p rbs8 r ead/wr ite 0 x00 00 0 000 0x0 0c8 priori ty register a fo r slav e 9 p ras9 r ead/wr ite 0 x00 00 0 000 0 x00cc prio r i t y re g ist er b for sl a v e 9 p rbs9 read/write 0 x00 0000 00 0x0 0d0 priori ty register a fo r slav e 10 pras10 r ead/wr ite 0 x00 00 0 000 0x0 0d4 priori ty register b fo r slav e 10 prbs10 r ead/wr ite 0 x00 00 0 000 0x0 0d8 priori ty register a fo r slav e 11 pras11 r ead/wr ite 0 x00 00 0 000 0x00dc prior ity register b fo r slav e 11 prbs11 read/write 0x00000000 0x00e0 priori ty register a fo r slav e 12 pras12 read/write 0x00000000 0x00e4 priori ty register b fo r slav e 12 prbs12 read/write 0x00000000 0x00e8 priori ty register a fo r slav e 13 pras13 read/write 0x00000000 0 x00ec prio r i t y re g ist er b for sl a ve 13 prbs13 read/write 0 x00 0000 00 0 x00 f0 prio r i t y re g ist er a for sl a ve 14 pras14 read/write 0 x0 00000 00 0 x00 f4 prio r i t y re g ist er b for sl a ve 14 prbs14 read/write 0 x00 0000 00 0 x00 f8 prio r i t y re g ist er a for sl a v e 15 pras15 read/write 0x000 00000 0x0 0 fc prio r i t y regist e r b fo r slav e 15 prbs15 r e a d / w r i te 0x 0 00 00000 0x 01 00 m aster remap co ntr o l register mr cr r ead/wr ite 0x0 0 00 0 000 0x01 04 - 0x010c reserved ? ? ? 0x0110 special function re gister 0 sfr0 read/write ? 0x0114 special function re gister 1 sfr1 read/write ? 0x0118 special function re gister 2 sfr2 read/write ? 0x011c special function re gister 3 sfr3 read/write ? 0x0120 special function re gister 4 sfr4 read/write ? tabl e 19-1. register mapping (continued) offset register name access reset value 32058k avr32-01/12 138 at32uc3a 0x0124 special function re gister 5 sfr5 read/write ? 0x0128 special function re gister 6 sfr6 read/write ? 0x012c special function re gister 7 sfr7 read/write ? 0x0130 special function re gister 8 sfr8 read/write ? 0x0134 special function re gister 9 sfr9 read/write ? 0x0138 special function re gister 10 sfr10 read/write ? 0x013c special function re gister 11 sfr11 read/write ? 0x0140 special function re gister 12 sfr12 read/write ? 0x0144 special function re gister 13 sfr13 read/write ? 0x0148 special function re gister 14 sfr14 read/write ? 0x014c special function re gister 15 sfr15 read/write ? 0x0 150 - 0x01f8 reserved ? ? ? tabl e 19-1. register mapping (continued) offset register name access reset value 32058k avr32-01/12 139 at32uc3a 19.7.1 bus m atri x mast er configurati on registers register name: mcfg0...mcfg15 acces s type: read/write ? u lbt : undefine d l eng t h b urs t type 0: infinit e lengt h burst n o predicte d en d of burs t is generated an d therefor e incr bursts coming from this master cannot be broken. 1: sin g le access the undefined length burst is treated as a succession of single accesses, allowi ng re-arbitration at each be at o f the incr burst. 2: four beat burst th e undefined lengt h burst is split in to a four-bea t burs t, allowin g re-arbitratio n at each four-bea t burst end. 3: eight beat burst th e undefine d leng th bu rst is sp lit in to an eig ht -be at burst , allowin g re-arbitration a t eac h eigh t-be a t b urs t en d. 4: sixteen beat burst th e undefined length bu rst is sp lit int o a sixteen-beat burst, allowin g re-arbitration at each sixteen-beat burst end. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ulbt 32058k avr32-01/12 140 at32uc3a 19.7.2 bus m a trix sla ve confi gura ti on registers register name: scfg0...scfg15 acces s type: read/write ? sl o t_cy cle: maximu m number of allowed cycles fo r a burst whe n the slot_cyc le limit is r eache d f or a bu rst , i t may be b roke n by anothe r master tryin g t o acces s thi s slave. th is limit ha s been placed to avoid lockin g a very slow slav e when ve ry long bur sts ar e used. this limi t must no t be very small . un reasonably small values br eak every burst and th e bus matr ix arbitr ates withou t per- formin g an y data transfer. 16 cycle s is a reasonable valu e fo r slot_cycle. ? d efmstr_type: default master type 0: no default master at t he end of th e current slav e access , if no othe r maste r request is p ending, th e slave is disconnected from all m asters. this results in a one cy c le latency for the first acce ss of a b urst transfer or for a single access. 1: last default master at th e en d o f t he current slav e access, if no othe r master request is pending , the slave st ays connected to th e last master ha v in g acc es s ed it. this resu lts in no t having one cyc le latenc y when t he last ma ste r tries to access th e slav e again. 2: fixe d default master at t h e end of t he current slav e ac cess, if no ot her master r equest is pendin g, th e slave connec ts to t he fixed maste r the number th at ha s be en wr itten i n th e f i xed_defmst r fi eld. this result s i n not havin g one cycle lat ency when the fi xed master tr ies t o acce ss th e sl ave again. ? fi xed_defmstr: fixed defaul t master this is the number of the defa ult master for this slave. onl y used if defmstr_ type is 2. specifying the number of a mas- ter wh ic h is not connected to the selected slave is equivalen t to setting defmstr_ type to 0. ? arbt: arbitration type 0: round-robin arbitration 1: fixed priority arbitration 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? arbt 23 22 21 20 19 18 17 16 ? ? fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 slot_cycle 32058k avr32-01/12 141 at32uc3a 19.7 .3 bu s matrix priority registers a for sl aves register name: pras0...pra s15 acces s type: read/write ? mxpr: master x pri ority fixe d priori ty of master x f or accessing the select ed slave. th e highe r th e n u mb er, t he highe r th e priori ty. 31 30 29 28 27 26 25 24 m7pr m6pr 23 22 21 20 19 18 17 16 m5pr m4pr 15 14 13 12 11 10 9 8 m3pr m2pr 7 6 5 4 3 2 1 0 m1pr m0pr 32058k avr32-01/12 142 at32uc3a 19.7 .4 bu s matrix priority registers b for sl aves register name: prbs0...prb s15 acces s type: read/write ? mxpr: master x pri ority fixe d priori ty of master x f or accessing the select ed slave. th e highe r th e n u mb er, t he highe r th e priori ty. 31 30 29 28 27 26 25 24 m15pr m14pr 23 22 21 20 19 18 17 16 m13pr m12pr 15 14 13 12 11 10 9 8 m11pr m10pr 7 6 5 4 3 2 1 0 m9pr m8pr 32058k avr32-01/12 143 at32uc3a 19.7.5 bus m a trix mast er rema p contr ol reg ister register name: mrcr acces s type: read/write reset: 0x0000_0000 ? rcb : remap command bit fo r master x 0: disab le remappe d add r ess de coding fo r t he selec ted master 1: enable remappe d addre ss decodin g for t he selected master 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rcb 15 r cb1 4 rcb 13 rcb12 rcb11 r cb10 rcb9 rc b8 7 6 5 4 3 2 1 0 rcb 7 rcb 6 rcb 5 rcb 4 rcb 3 rcb 2 rcb 1 rcb0 32058k avr32-01/12 144 at32uc3a 19.7. 6 bu s matr ix sp ec ial fun c tion registe rs register name: sfr0...sfr15 acces s type: read/write reset: ? sfr : s p e ci al fu nc ti on regis t er fi e lds th e bitfi elds of th ese register s ar e described in the peripher als chapter. 31 30 29 28 27 26 25 24 sfr 23 22 21 20 19 18 17 16 sfr 15 14 13 12 11 10 9 8 sfr 7 6 5 4 3 2 1 0 sfr 32058k avr32-01/12 145 at32uc3a 20. external bus interface (ebi) re v: 1.0.0.1 20.1 features ? pres ent only on at32uc3a0512 and at32uc3a0256 ? optimized fo r application memory space s upport ? integrat e s tw o external memory controllers: ? s tatic me mo r y contr oller ? s dram cont roller ? op timiz ed ex t ern a l bus : ?16-bit data bus ? 24 - bit a ddres s b u s , u p to 1 6 -m b y te s a ddr essab le ? o pti mize d pin mu lt ip lexing to re duce latencies on external me mories ? 4 sram chip select s, 1 sdram chip sele cts: ? s tatic memory controller on ncs0 ? s dram cont roller or st atic memory contro ller on ncs1 ? s tatic memory controller on ncs2 ? s tatic memory controller on ncs3 20.2 description the ex t ernal bus interf ace (ebi) is designed to ensure t he successf ul da ta transf er between severa l external devices and the at32uc3a device. t he stat ic memo ry an d sdram control- lers are a ll featured external memo ry controllers on th e ebi . these external memo ry controllers are capable o f handlin g several typ es of exte rnal memory an d peripheral devices, s u ch as sram, prom, ep r om, eeprom, flash, and sdram. t he ebi handles data transfers wit h up to fiv e e xter nal de vices, ea ch assigned to five a ddress spaces defin ed by th e embedded memo ry co ntroller. da ta tr ansfers are perform ed through a 16-b it dat a bu s, a n address bus of up to 24 bits, up to four ch ip se lect lines (ncs[3:0]) and sev- eral control pi ns that ar e generally multip lexed between the diff erent ex t ernal memor y controllers. 32058k avr32-01/12 146 at32uc3a 20.3 block diagram 20.3 .1 external bus int erface figure 20-1 sho ws t h e organiza ti on o f th e e xte rna l b us inte rface. figur e 20-1. organizatio n of the extern al bus interface 32058k avr32-01/12 147 at32uc3a 20.4 i /o lines description depending on th e memo ry controller in use , all signals are not connected direct ly through the mu x logic. table 20-2 on pag e 147 de tails the connecti ons between t he two memory cont rollers and the ebi pins. tabl e 20-1. eb i i /o line s descript ion name function type acti ve level ebi d0 - d15 data bus i/o a0 - a23 address bus output nwait external wa it signal input low smc ncs0 - ncs3 c hip sele ct lines output low nwr0 - nwr3 wr ite signals output low noe o utput enab le outp ut low nrd r ead signal output low nwe wri te enable output low nbs0 - n bs3 byte mask signals output low sdram cont roller sdck sdra m clock output sdcke sdr am clock enable output high ba0 - ba1 bank select output sdwe sdram wr ite enable output low r a s - cas r o w a n d c o l u m n s ign al o u t p ut l ow nwr0 - nwr3 wr ite signals output low nbs0 - n bs3 byte mask signals output low sda10 sdram address 10 line output tabl e 20-2. ebi pins a n d memo ry controllers i/o line s connections ebi pi ns sdramc i/ o l ines sm c i/ o l ines nwr1/nbs1 nbs1 nwr1/nub a0/nbs0 no t supported smc_a0/nlb a1/nbs2/nwr2 not supported smc_a1 a[11:2] sdramc_a[9:0] smc_a[11:2] sda10 sdramc_a10 not s upported a12 not supported smc_a12 a[14:13] sdramc_a[12:11] smc_a[14:13] 32058k avr32-01/12 148 at32uc3a 20.5 a pplication example 20.5 .1 hardwa re interface ta ble 20- 3 on pa ge 148 detai ls the connection s t o be applie d betwee n the ebi pins a nd the external devices fo r eac h memory controller. notes: 1. nwr1 enab les upper by te writes . nwr0 enables lower by te writes. 2. nw rx e n a b l e s c o r r e spond ing byt e x w rites . ( x = 0,1, 2 o r 3) 3. nbs0 an d nbs1 enable respectively lowe r an d upper by tes of the lowe r 16-bit word. 4. nbs2 an d nbs3 enable respectively lowe r an d upper by tes of the up per 16-bit word. 5. bex: byt e x ena b le (x = 0, 1,2 or 3) a[22:15] no t supported smc_a[22:15] a[23] no t supported smc_a[23] d[15:0] d[15:0] d[15:0] tabl e 20-2. ebi pins a n d memo ry controllers i/o line s connections ebi pi ns sdramc i/ o l ines sm c i/ o l ines tabl e 20-3. ebi pins a n d external stat ic devices connections signals pins of the interfa c ed device 8-bit st atic device 2 x 8- bit static devices 16-b it static device controller smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 d8 - d15 ? d8 - d15 d8 - d15 a0/nbs0 a0 ? nlb a1/nwr2/nbs2 a1 a0 a0 a2 - a22 a[2:22] a[1:21] a[1:21] a23 a[23] a[2 2] a [22] ncs0 cs cs cs ncs1/sdcs0 cs cs cs ncs2 cs cs cs ncs3 cs cs cs nrd/noe oe oe oe nwr 0/ n we we we (1) we nwr1/nbs1 ? we (1) nub nwr3/ nbs3 ? ? ? 32058k avr32-01/12 149 at32uc3a tabl e 20-4. ebi pins a n d externa l sdram d e vices con nectio ns signals pins of th e interfaced device sdram contr oller sdramc d0 - d15 d0 - d15 a0 /nbs0 dqm0 a1/nwr2/nbs2 dqm2 a2 - a10 a[0:8] a11 a9 sda10 a10 a12 ? a13 - a14 a[11:12] a15 ? a16/ba0 ba0 a17/ba1 ba1 a18 - a23 ? ncs0 ? ncs1/sdcs0 cs[0] ncs2 ? ncs2 ? ncs3 ? nrd/noe ? nwr0/nwe ? nwr1/nbs1 dqm1 nwr3/nbs3 dqm3 sdck clk sdcke cke ras ras cas cas sdwe we nw ait ? 32058k avr32-01/12 150 at32uc3a 20.5.2 connectio n examples figure 20-2 shows an exa mpl e of connecti ons betwee n th e ebi an d exter nal devices. figur e 20-2. ebi connections t o memor y devices ebi d0-d15 a2-a15 ras cas sdck sdcke sdwe a0/nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 ncs1/sdcs d0-d7 d8-d15 a16/ba0 a17/ba1 a18-a23 a10 sda10 sda10 a2-a11, a13 ncs0 ncs2 ncs3 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 a2-a11, a13 sda10 a16/ba0 a17/ba1 nbs0 nbs1 nrd/noe nwr0/nwe 128k x 8 sram 128k x 8 sram d0-d7 d0-d7 a0-a16 a0-a16 a1-a17 a1-a17 cs cs oe we d0-d7 d8-d15 oe we nrd/noe a0/nwr0/nbs0 nrd/noe nwr1/nbs1 sdwe sdwe 32058k avr32-01/12 151 at32uc3a 20.6 p roduct dependencies 20.6.1 i/ o li nes th e pins used for interfacin g th e external bus interfac e may be multiple xed with th e gpio lines. the p rogramm er mus t fi rst program t he gpio controller t o assign th e external bus interface pins to t heir peripheral function. if i/o lines of the external bus inter f ace are not used by th e application, they can be used fo r othe r purposes by t h e gpio controller. 20.6.2 power management th e ebi hsb cl ock and sdramc, sm c an d ecc pb clocks ar e generate d by t he power man- ager. befor e using t he ebi, th e pr ogrammer must ensure that t hese clocks are enabled in the power manager. t o prevent b us errors ebi operatio n mus t b e terminate d b efore enterin g sle ep mode 20.6 .3 interrupt the eb i interface has an inte r rupt line connected to the int errupt controller. handling the ebi interrupt require s programming the interrup t controller befor e configuring the ebi. 20.7 functional description th e eb i tr ansfer s data betwee n t h e in ter nal hsb bus (ha ndle d b y th e hm at rix) a nd th e exte rna l memories or peripheral d e vices. it controls the waveform s and the paramet ers of t he external address, dat a and contro l busses an d is compose d o f the follo wing elements: ? the static memory c ontrolle r ( sm c) ? t he sd ram controller (sdramc) ? a chip sele ct assignment featur e th at assign s an hsb address spac e to the external devices ? a multiple x controller circui t that shares t he pins between t he different memory controllers 20.7.1 bus m ultiplexing the ebi offers a c o mplete set of control sig nals th at share the 1 6-bit data lines, the addres s lines of up t o 2 4 bits an d th e contro l si gn als th roug h a multip le x lo gi c o perati ng i n fu ncti on o f the memory are a re ques ts. mul tiplexing is s pe cif ical ly o rganized i n o rder t o guarant ee th e mainte nance of t he add ress and outpu t control lines a t a stable stat e while no ex ternal access is being performed. mult iplexing is also d esigned to respec t t he data float times defi ned in the memory controllers. furthermore, ref resh cycles of t he sdram ar e execut ed independent ly by t he sdram controlle r without delaying th e other external memory controller accesses. 20.7 .2 pull- up control a s pecif ic hmatri x_sfr register in the matr ix user interf ace permit enabli ng of on-chip pull-up resistor s on t he dat a bus lines not multip lexed with the gpio controlle r lines. for deta ils on this register, refer to t he peripher als section. the pull-up resist ors are enable d after reset. setting th e ebi_dbpuc bit di sables the pull-up resistor s on li n es not muxed with gpio. enabling th e pull-up r esistor on lines multiplexed with gpio lin es can be perf o rmed by programming the appropriate gp io controller. 32058k avr32-01/12 152 at32uc3a 20.7 .3 static memory controller fo r informatio n on the static memo ry controller, refer to th e stat ic memory controlle r section. 20.7.4 s dr a m co ntroll er for information on the sdr a m controller, refer to th e sdram section. 32058k avr32-01/12 153 at32uc3a 21. p er ipher al dma controller (pdca) r ev: 1.0.0.0 21.1 features ? generates transfer s to/from peripherals such as usart, ss c an d spi ? tw o a d dr ess po in te rs/ c oun ter s pe r chan nel allowin g double buffering 21.2 overvi ew th e peripher al dma controlle r (pdca) transfers data between on- chip periphera l modules such as usar t, spi , ssc an d on- and off-chip memories. using the pdca avoi ds cpu in tervention fo r da ta transfer s, improving t he performanc e of the microcon troller. th e pdca can transfer data fr om memory t o a peripheral o r fro m a peripheral t o memory. t h e p dc a con sist s o f a n umbe r of dma c ha nnels. e ac h cha nne l h as: ? a 32 - bi t memory po inter ? a 16-bit transfer counter ? a 32-bit memory pointe r reload value ? a 16-bit transfer counte r reload value the pdca c ommunicate s with t he peripher al modules over a number of h a ndshake interfaces. the peripheral signals to the pdc a wh en it is re ad y to rece ive or t r ansm i t data . t he pdc a acknowledges th e request when the tran smission ha s started. th e number of handshake-interf aces may be higher than the number of dma channels. if th is is t he case, th e dma channe l must be programmed to use th e desire d interface. when a t ransm it buffer is empty or a r e ceive buffer is full, an interrupt request ca n be signalled. 32058k avr32-01/12 154 at32uc3a 21.3 block diagram 21.4 functional description 21.4.1 configuration each channel i n the pdca h a s a set of confi guration registers. am ong these a re the memory addres s register (mar), th e periphera l select register (psr ) and th e transfer counte r regis- ter (tcr). the 32-bi t memory address register must be programmed with the star t ad dress of the memor y buffer. the register w ill be automatically updated aft e r each transfer to point to th e next location in me mory . the peripheral select register must be programm e d to select the desired p eripheral/handsha ke interface. the tra nsf er count er regist er det ermines th e number of data items to be tra nsf erred. the c ounter will be decreased by one for ea ch data item that ha s bee n tr ansferred. both the memory address r e gister and th e transfer counter registe r can be read at any time to che ck th e progress of the transfer. each chann el has also reloa d register s fo r the memory a d dress regist er an d the transfer counte r register. when t he tcr reac hes zero, the valu es in th e reload register s ar e loaded into ma r an d tcr . i n this w ay, the p dca ca n o perate o n tw o buffers for each channel . 21.4.2 memory pointer ea ch cha nnel h a s a 32- bit me mor y point e r r eg ister (mar) . this r egi ste r hold s th e mem o ry addr ess fo r the ne xt transfer to be performed. the register is automa tically update d afte r each hs b to pb bridge peripheral dma controller (pdca) peripheral 0 bus matrix hands h ake i nterfac es peripheral bus irq hsb hsb interrupt controller peripheral 1 peripheral 2 peripheral (n-1) 32058k avr32-01/12 155 at32uc3a transf er. the addr ess will be in creased by eithe r 1, 2 or 4 depending on the size of t h e dma transfer (byte, half-word or word). th e memo ry addr ess register ca n be read at any ti me dur- in g transfer. 21.4.3 transfer counter each cha nnel has a 1 6-bit transfer counter register (tcr). th is regist er must be p rogrammed wit h t he number o f transferre d to be performed. tcr should contain the number of data items to be transferr ed independently of the transf er size. th e transfer counter regist er ca n be read at any tim e du ring tran sfe r to see t he n umb er of re main ing tran sf ers. 21.4.4 reload registers b ot h th e mem o ry addr es s r egi st er and t he tr ansfe r counter regis t er hav e a r e l o a d r egiste r , res pectively memo ry addr ess reload re gister (marr) an d transfer counter relo ad register (tc rr). these registers provide the possibility for the pdca to w o rk on two memory buffers for each channel. when one buffer has completed , mar and tcr will be r e loaded with the values in mar r and t c rr. the reload logic is alway s enabled and will trigger if the t c r re ache s zero while tcrr holds a non- ze ro value. 21.4.5 peripheral selection the peripheral select register decides w h ich peripheral should be co nnected to the pdca channel. configuring psr will both select t he dire ction of the trans f er (memory to peripheral or peripheral to memory), which handshak e interface to use, and the address of th e peripheral holdin g register. 21.4.6 transfer size the tran sfer size ca n be set individually for each channel to be either by t e, half-w ord or word (8-bit, 16-b it or 32-bit respectively). transfer size is se t by programm ing th e size bit-fi eld in the mo de register (mr). 21.4.7 enabling an d disabling each dma channel is enabled by writing ?1? to the transfer enable bit (ten) in the control reg- ister (cr) a n d disa bl e d by writin g ?1 ? to th e tra nsfer disa b l e bi t (t dis). t h e curre nt statu s can b e read from the status registe r (sr). 21.4 .8 interrupts int err upt s ca n be enab led by w riting t o the interrup t en abl e re giste r (ier) an d disa bl ed by writ- ing to int e rrupt disabl e register (idr). th e in terrupt ma sk register (imr) can be r ead to see whether an i nt e rrupt is en abl ed o r not. the current s tat us of an interru pt source can b e read through the interrupt stat us registe r (isr). th e pdca has thre e interrupt sources: ? r elo ad counte r zer o - the transfer counter reload register is zero. ? transf er finish ed - both the transfe r counte r register and transfe r counte r reloa d register are zero. ? transfe r error - an e rro r ha s occurred in accessi n g memory. 32058k avr32-01/12 156 at32uc3a 21.4.9 p riori ty if mor e th en one pdca ch anne l is req uesting tran sfer at a give n time , th e pdca channels are prioritized by their channel number. channels w i th lower numbers have priority over channels with highe r numbers, giving channe l 0 th e highest priority. 21.4.10 err or handling i f the m emor y ad dre ss i s s et to p oin t t o a n i nval id l ocatio n i n mem ory , an er r or wil l o cc u r w hen th e pdca tries t o perfo rm a transfer. when a n error occurs , t he transfer erro r flag (terr) in t he interrup t stat us regist er will be set and t he dma chann el that caused t h e err or will be stop ped . i n orde r t o res tart th e ch a nne l, t he us er must pro gra m t he me mo ry a ddr ess re gist er t o a v a lid addr ess a nd t h en writ e th e erro r clea r bit (e clr) in the control regist er (cr) to ? 1 ?. a n interr upt can option ally be trigge red on e rrors by writing the terr -bit in t he interr upt enable regist er (ier ) to ?1?. 21.5 u ser interface 21.5.1 memor y m ap overview no te: the n umber of chan nel s i s imp l e m e n t a ti on sp ecific. see part documentation fo r details. 21.5.2 channel memor y map tabl e 21-1. register ma p overview addre ss ra n ge contents 0x00 00 - 0x003f dma c hann el 0 configuratio n registers 0x00 40 - 0x007f dma c hann el 1 configuratio n registers 0x008 0 - 0x00bf dma c hann el 2 configuratio n registers 0x00 c0 - 0x00ff d ma ch ann el 3 configuratio n r e gisters 0x01 00 - 0x013f dma c hann el 4 configuratio n registers - - - d ma channel n-1 confi guration registers offset register register na me access reset 0x00 memory addr ess register mar read/write 0x00000000 0x04 peri pheral sele ct register psr read/write * 0x08 transf er counte r register tcr read/write 0x00000000 0x0c memory addre ss reloa d register marr read/write 0x00000000 0x10 transf er coun ter reload register tcrr read/write 0x00000000 0x14 c o ntro l r egister cr write- on ly - 0x18 mode register mr read/write 0x00000000 0x1c status r egister sr read-only 0x00000000 0x20 interr upt enable register ier write-only - 32058k avr32-01/12 157 at32uc3a 0x24 interrup t disab le register idr write-only - 0x28 interrup t mask register imr read-only 0x00000000 0x2c interrup t status register isr read-only 0x00000000 offset register register na me access reset 32058k avr32-01/12 158 at32uc3a 21.5.3 pdca mem ory addre ss register name: mar acces s type: read/write ? maddr: memo ry address address of memory buffer. maddr s hould be programmed to poin t to the start of the memory buffer when configuring the pdca. du ring transfer, mad dr will point to the next memory location to be read/written. 31 30 29 28 27 26 25 24 maddr 23 22 21 20 19 18 17 16 maddr 15 14 13 12 11 10 9 8 maddr 7 6 5 4 3 2 1 0 maddr 32058k avr32-01/12 159 at32uc3a 21.5.4 pdc a pe ripher a l s elect register name: psr acces s type: read/write ? pid: peripheral identifier the p eri pheral identif ier select s which peripheral should be connected to th e dma channel. programming pid will select bo th which handshake in terf ace t o use, th e directio n of the transf er an d also the addres s of t he receive/transf er holding register for the peripher al . the pi d values for the different p erip hera l m odule s are i mpl e m en t ati on specif ic . see t he part spec ific documentation for details. the width o f th e pi d bitfield is i mplementation specif ic and dependent on the number of peripheral modul es in the microcontroller. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 pid 32058k avr32-01/12 160 at32uc3a 21.5.5pdca transf er count er regi ste r name: tcr acces s type: read/write ? t c v : tr ansf e r coun t e r valu e number of data items to be transferred by pdca . tcv must be programmed with the total numbe r of transfers to be made. during transfer, tcv cont ains th e number of remaining transfer s t o be done. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 tcv 7 6 5 4 3 2 1 0 tcv 32058k avr32-01/12 161 at32uc3a 21.5 .6 pdca memory address reload register name: marr acces s type: read/write ? marv : memory ad dress reload value reload value for the memory address re gister (mar). this value will be load ed into mar wh en tc r reaches ze ro if the tcrr ha s a non-zero value. 31 30 29 28 27 26 25 24 marv 23 22 21 20 19 18 17 16 marv 15 14 13 12 11 10 9 8 marv 7 6 5 4 3 2 1 0 marv 32058k avr32-01/12 162 at32uc3a 21.5.7 pdca transf er counter reload register name: tcrr acces s type: read/write ? tcrv: transfer counter reload value reload va lue for the transfer counter re gister (tcr). wh en tcr reache s ze ro, it will be reloaded with tc rv if tc rv has a positi ve value. if tc r v is zero, no more transfers will be performed for the c hannel. when tcr is re aloaded, the transfer counter reload regi st er is cleared. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 tcrv 7 6 5 4 3 2 1 0 tcrv 32058k avr32-01/12 163 at32uc3a 21.5 .8 pdca control register name: cr acces s type: write-only ? eclr: er ro r clear 0 = no effect. 1 = c lear tr a nsf e r e rror (ter r ) flag i n the status regist er (s r). clearing the transfer error flag will allow the channel t o transm it data. th e memory address mu st first be set to point t o a valid location. ? ten: transfer enable 0 = no effect. 1 = e nab le transfer fo r dma channel. ? tdis: transfer disable 0 = no effect. 1 = disa ble transfer fo r dma channel. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - eclr 7 6 5 4 3 2 1 0 - - - - - - tdis ten 32058k avr32-01/12 164 at32uc3a 21.5 .9 pdca mode register name: mr acces s type: read/write ? size: si ze of trans fer 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - size size size of transfer 0 0 byte 0 1 half-word 1 0 word 1 1 reserved 32058k avr32-01/12 165 at32uc3a 21.5.10 pdc a status register name: sr acces s type: read ? ten: transfer enabled 0 = tr ansfer is disabled for the dma cha nnel 1 = transfer is e nable d for the dm a channel. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ten 32058k avr32-01/12 166 at32uc3a 21.5.11 pdc a inte rrupt enable register name: ier acces s type: write-only ? terr: transfer error 0 = n o e ffect. 1 = e nab le transfer erro r interrupt. ? trc: t ransfer complete 0 = n o e ffect. 1 = e nab le transfer complete interrupt. ? rcz: r e load counter zero 0 = n o e ffect. 1 = e nab le reloa d counte r zer o interrupt. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - terr trc rcz 32058k avr32-01/12 167 at32uc3a 21.5.12 pdc a interrupt disable register name: idr acces s type: write-only ? terr: transfer error 0 = n o e ffect. 1 = disa bl e transfer erro r interrupt. ? trc: t ransfer complete 0 = n o e ffect. 1 = disa bl e transfer complete interrupt. ? rcz: r e load counter zero 0 = n o e ffect. 1 = disa bl e reloa d count e r zero interrupt. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - terr trc rcz 32058k avr32-01/12 168 at32uc3a 21.5.13 pdc a inter r upt mas k reg is t er name: imr acces s type: read-only ? terr: transfer error 0 = transfer error interrup t is disabled. 1 = transfer error interrup t is enabled. ? trc: t ransfer complete 0 = t ransfer complete interrup t is disabled. 1 = t ransfer complete interrup t is enabled. ? rcz: r e load counter zero 0 = r eload counter zer o interrupt is disabled. 1 = r eload counter zer o interrupt is enabled. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - terr trc rcz 32058k avr32-01/12 169 at32uc3a 21.5.14 pdc a inte rrupt stat us register name: isr acces s type: read-only ? terr: transfer error 0 = n o transfer errors ha ve occurred. 1 = a transfer error ha s occurred. ? trc: t ransfer complete 0 = th e tra nsfe r counte r registe r ( tcr) a nd/o r t h e tran sfe r counte r relo ad re giste r (tcrr) hold a non -ze r o valu e. 1 = b oth th e tr ansfer co un ter regist er (tcr ) a nd th e transfer coun te r reloa d registe r ( tcrr) are zer o. ? rcz: r e load counter zero 0 = th e tra nsfe r counte r relo ad regis te r ( tcrr) hold s a non-zero va lue. 1 = th e tra nsfe r counte r relo ad regis te r (tcrr) is zer o. 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - terr trc rcz 32058k avr32-01/12 170 at32uc3a 22. general-purpose input/ output contro ller (gpio) re v. 1.1.0.2 22.1 features each i/o line of th e gpio features: ? configurabl e pin-change, rising-edge or falling-edge interrupt on an y i/o line. ? a glit ch filter prov iding reject ion of pulses sho r ter than one clock cycle. ? ope n drain m od e ena bling s ha r ing of an i/o line betwee n the mcu and extern al components. ? input visibility and output control. ? multiplexin g of up to fo ur peripheral function s per i/o line. ? programmabl e intern al pull-up resistor. 22.2 overvi ew the g ener al purpos e input/output mana ges the i/o pins of th e m icrocontroller . ea ch i/o line ma y b e dedicate d as a g eneral-purpose i/o o r be assigned t o a functi on of a n embedde d periph- eral. this assures effective optimization o f th e pi ns of a p roduct. tabl e 22-1. o verview of the gpio system 22.3 pr oduct dependencies 22.3.1 module configuration most o f the features o f the gpio are configurable for each p roduct. th e programmer mus t refer to th e periphera ls section for th ese settings. product specific settings includes: inte rrupt controller p o we r ma n ag er embedded peripheral general purpose input/output - gpio gpio interrupt request gpio clock pin cont rol s i gnals pin pin pin pin pin mcu i/o pins pb a co nfi g urat i on interface 32058k avr32-01/12 171 at32uc3a ? number of i /o pins. ? function s implemente d on eac h pin. ? peripheral function(s) multiplexed on each i /o pin. ? rese t state of registers. 22.3.2 interrupt lines th e g pi o interrup t line s ar e co nn ect ed to t h e interru pt con tro lle r. usi ng th e g pio inte rru pt requires t he interrupt controller t o b e programmed first. 22.3.3 po wer an d cloc k management the clock for the gpio is con trolle d by the power mana ger. the programmer must ens u re that th e gpio clock is e nabled in th e power manage r before using the gp io. the clock must be enable d in order to access t he configuration register s o f the gpio and when interrupts are ena bled . afte r con figur ing t h e gpi o , th e cloc k c a n b e di sabled if i n ter rup ts ar e no t en able d. 22.4 functional description the gpio contro ls the i/o lines o f the microcontroller. th e contro l logic associated wit h each pin is r epresente d in th e figure below: figur e 22-1. overview o f th e gpi o pa d connections 22.4 .1 pull- up resist or control each i/o lin e is designed with an embedded pull-up resistor . th e pull- up resistor ca n be enabled or disabled by acc essing t he corresponding bit in puer (pull-up enable r egister) . contro l of the pull-up resistor is p ossible whether an i/o li ne is contro lled by a peripher al or th e gpio. 0 1 gpio_odmer 0 1 0 1 g p io_gper 1 0 gpio_ovr gpio_oder gpio_pmr1 peri ph. a output en able peri ph. b output en able pe rip h . c ou t pu t en ab le pe rip h . d ou t pu t en ab le pe rip h. a output da ta pe rip h. b output da ta pe ri ph . c ou t put da ta pe ri ph . d ou t put da ta pad g p io_pu er peri ph . a i n put da ta peri ph . b i n put da ta peri ph. c input data peri ph. d input data gpio _ pvr 0 1 glit ch fi l ter gpio_gfer edge d etect or 1 0 interru pt request gpio_imr1 gpio_pmr0 gpio_imr0 gpio_ier 32058k avr32-01/12 172 at32uc3a 22.4.2 i/o li ne or periphe ral func tion selection when a pin is multiplexe d wit h o ne or more peripheral functions, th e select ion is controlle d with t he register gper . if a bit in t he register is s et , t he corr esponding pin is con tro lle d by th e gpio. if a bi t is cleared, th e correspondin g pi n is controlle d by a peripher al function. 22.4.3 peripheral selection th e gpio provides multiplexin g of up to four peripheral function s on a si ngl e pin. t he selection is perfor m ed by acc ess ing p mr 0 ( p er i phera l mu x register 0) an d pmr1 (peripheral mu x regis- te r 1). 22.4.4 output control when the i/o line is assi gned to a periphera l function, i.e. th e corresponding bit in gper is at 0, t he dr ive of the i/o line is co ntrolle d by th e periphera l. th e periphera l, depending on t he value in pmr 0 and pmr1 , determines whethe r th e pin is driven o r not. whe n the i/o line i s contr olled b y t h e gpi o , th e v al ue o f od er (o utpu t d rive r e nab le r e gister) determ ines i f the pin is d r iven or not. when a bit in this register is at 1 , th e correspondin g i/ o line is drive n b y th e gpio. whe n th e b it is at 0, th e gpio does not drive the line. th e level dr iven o n an i/o lin e can b e determined by w riting ov r (outpu t valu e register). 22.4.5 op en drai n mode each i /o lin e can be independently programmed to operate in open drain mode . th is feature perm its severa l drivers to be c onnected on the i/o line. the driver s should on ly acti vely drive the line l ow. an ext e rnal pull- up resist or (o r en ablin g th e intern al one ) is gen e rally r e quire d to guar- ante e a high level o n th e line when no driver is ac tive. th e o p en drai n featur e is con tro lled by od mer (ope n drai n m od e ena b le reg is ter) . the open drain m ode can b e selected whether the i/o lin e is controlled by t h e gpio or assigne d to a peripheral function. 22.4.6 inputs th e level on each i/o line can b e read through pvr (p in value register). th is regist er indicates t he leve l of the i/o lines regard less of whether t he lin es ar e driven by the gpio or by an external component. note that due t o power saving measures, pv r register ca n only be read when gper is se t f o r th e corresponding pi n or if interrupt is en abled for the pin. output line timings the figure below shows t h e timing o f the i/o line whe n setting a nd clearing the output value register by accessing ovr. t he same ti ming appl ies when performing a ?set? o r ?clear? access i.e. writing to ovrs or o v rc. th e timi ng of pvr (pin value register) is also show n. 32058k avr32-01/12 173 at32uc3a figur e 22-2. output line timings 22.4 .7 interrupts th e gpio can be programmed t o gene rate an interr upt when it de tects an input change o n an i/o lin e. th e module can b e configured to signa l an interrupt whenever a pin cha n ges valu e or only to trigger on ri si ng edges or falling edges. interrupt is enab led on a pin by setting the corre- sponding bi t in ier (interrupt enable register). the i nterrupt mode is se t by accessing imr0 (interrupt mo de registe r 0) an d imr1 (interrupt mod e register 1). interrupt ca n be enabled on a pin, regardless of t he configuration the i/ o line, i. e. controlled by the gpio or assigned to a peripher al func tion. in every port there are four interrupt lines connected to the interrup t controller. ever y eigt h inter- rup ts in th e por t ar e ored together to form an interrupt line. when an inte rrupt ev ent is detected on a n i/o line, a nd the correspondin g bit in ier is s e t, the gpi o inte r rupt reques t l ine i s asserted. a nu m be r o f i nte rr upt s ig n al s are o red- wir ed toge t h er to generat e a sing le interrupt signal to th e interrupt controller. if r (interrupt flag register) c an by read by s oftware to determin e which pin(s) caused th e inter- rupt. t he interrupt flag must be manua lly cleare d by writing to ifr. gpio interrupt s ca n only be triggere d when the gpio clock is e nabled. 22.4. 8 inpu t g litc h fil t er optional inpu t glitch filters c an b e enab led o n each i/o line . wh en th e glit ch filte r is enabled, a glitch with dur a t ion of less than 1 clock cycle is auto matically rejected, wh ile a pulse with dura- ti on of 2 clock cycles o r mo r e is acce p ted . for pulse duration s betwee n 1 cloc k cycle and 2 cloc k cycles, the pulse may or may not be taken into account, depend in g on the preci se timing of its occurrence. thus for a p ulse to be guarante ed visible it must exceed 2 clock cycl e s, whereas for a gli t ch t o be reliably filtered out, its du ration mu st no t excee d 1 clock cycl e . the filter introduces 2 clock cy c les latency. th e glitch filters ar e controlled by the register gf er (glitch filter enable register). when a bi t is set in gfer , th e glitch filter on th e corresponding pin is e nabled. the glitch filter affects only interrup t inputs . inputs t o peripherals or the value read through pv r are not affected by the glitch filters. 22.4.9 in terrup t tim i ngs the figure belo w shows the timing for rising edge (or pin-change ) interrup ts when the glitch filter is disabled. for t he pulse t o b e registered , it must be sam p led at th e risin g edg e of t he clock. in this example, this is no t th e cas e for the first p ulse . t h e secon d puls e is however sample d on a risi ng edge and will trigge r an inter r upt request. pba access pba access clock wr ite gpio _ ovr t o 1 wr ite gpio _ ovr t o 0 gpio_ovr / i /o line gpio_pvr 32058k avr32-01/12 174 at32uc3a figur e 22-3. interrup t timing wi th glitch filter disabled the figure belo w shows the timing for rising edge (or pin-change ) interrup ts when the glitch filter is ena ble d. for t he pulse t o be registered , it must be sam pled o n two subsequent rising edg es. in th e example , the first pulse is r eje cted while the second pulse is acc epte d a nd causes an interrupt request. figur e 22-4. interrup t timing wi th glitch filter enabled cl ock pi n level gpio_ifr clo ck pi n level gpio_ifr 32058k avr32-01/12 175 at32uc3a 22.5 g eneral purpose input/output (gpio) user interface the gpio controls all the i/o pins on t he avr32 microcontroller. t he pins are managed as 32- bi t port s that are configurable through an pb interface. eac h por t has a se t of configuration reg- isters. th e over all memo ry ma p of th e gpio is shown b e low. t h e nu mbe r o f pi ns an d he nce th e number of port s is product specific. in th e pe riph eral muxin g tabl e in the peri pher als ch apter eac h gp io lin e h a s a uniq ue numb er. note that th e pa , pb, pc and px por ts do not directly correspon d to the gpi o ports . to fi nd the correspondin g port an d pin the following formulas ca n be used: gpio port = floor((gpio number ) / 32), example: floor((36)/32 ) = 1 gpio pin = gp io number mo d 32, example: 36 mo d 32 = 4 the tabl e below shows the configurat ion registers for one port. addres ses shown ar e relati ve to the port addres s offset. the specif ic add ress of a con figuration regist er is foun d by adding the register offset and the port offse t to the gpio start addr ess. one bit i n each of th e configuration register s corresponds t o an i/o pin. port 0 configuration registers port 1 configuration registers port 2 configuration registers port 3 configuration registers port 4 configuration registers 0x0000 0x0100 0x0200 0x0300 0x0400 tabl e 22-2. gpio register map offset register function name access reset value 0x00 gpio en able register read/write gper read/write 1b fo r each implemented gpio p in in port 0x04 gpio en able register set gpers write-only 0x08 gpio en able register clear gperc write-only 0x0c gpio en able register toggle gpert write-only 0x10 periphera l mu x re gister 0 read/write pmr0 read/write 0x00000000 32058k avr32-01/12 176 at32uc3a 0x14 periphera l mu x re gister 0 set pmr0s write-only 0x18 periphera l mu x re gister 0 clear pmr0c write-only 0x1c periphera l mu x re gister 0 toggle pmr0t write-only 0x20 periphera l mu x re gister 1 read/write pmr1 read/write 0x00000000 0x24 periphera l mu x re gister 1 set pmr1s write-only 0x28 periphera l mu x re gister 1 clear pmr1c write-only 0x2c periphera l mu x re gister 1 toggle pmr1t write-only 0x30 reserved - - - 0x34 reserved - - - 0x38 reserved - - - 0x3c reserved - - - 0x40 outp ut driv er enab le register read/write oder read/write 0x00000000 0x44 outp ut driv er enab le register set oders write-only 0x48 outp ut driv er enab le register clear oderc write-only 0x4c outp ut driv er enab le register toggle odert write-only 0x50 ou tp ut v alu e register read/write ovr read/write 0x00000000 0x54 ou tp ut v alu e register set ovrs write-only 0x58 ou tp ut v alu e register clear ovrc write-only 0x5c ou tp ut v alu e register toggle ovrt write-only 0x60 pin value register read pvr read-only dependi ng on pin states 0x64 pin value register - - - 0x68 pin value register - - - 0x6c pin value register - - - 0x70 pull -up enab le register read/write puer read/write 0x00000000 0x74 pull -up enab le register set puers write-only 0x78 pull -up enab le register clear puerc write-only 0x7c pull -up enab le register toggle puert write-only 0x80 op en drain mod e en ab l e re giste r re a d/wri te odmer re ad/w ri te 0x00 000000 0x84 op en drain mod e en ab l e re giste r set o dme rs wr ite-on ly 0x88 op en drain mode enable register clear odmerc write-only 0 x8c o p en drai n mo d e enable reg is te r tog g le o dmert w r i t e- on ly 0x90 interr upt enable register read/write ier read/write 0x00000000 0x94 interr upt enable register set iers write-only 0x98 interr upt enable register clear ierc write-only 0x9c interr upt enable register toggle iert write-only tabl e 22-2. gpio register map offset register function name access reset value 32058k avr32-01/12 177 at32uc3a 22.5.1 access types each configuratio n register ca n be accessed in four different ways. the firs t addr ess location can b e used t o write the register directly. th is addre ss can also be use d to re a d the register value. the following addre ss es fac ilitate three different types of wr ite access to th e register. per- forming a ?set? ac cess , all bits wr itten to ?1? will be set. bit s written to ?0? will be un ch anged by the operation. perfo r ming a ?clear? access , all bits written to ?1? will be cleared. bits written to ?0? wil l be unchanged by the operation. finall y , a toggle access will to ggle the value of all bits written t o ?1?. again all bit s written to ? 0? rema in unchanged. not e that fo r som e registers (e.g. ifr), not all access method s are permi tted. no te that fo r p orts with less than 32 bits, t he correspo nding cont rol regist ers will have unused bits . this is also th e case for features that are n ot imple mented for a specific pin. writing to an unused bit will have n o ef fec t. r ead i ng unus ed bit s w ill always return 0. 0xa0 interr upt mo de register 0 read/write imr0 read/write 0x00000000 0xa4 interr upt mo de register 0 set imr0s write-only 0xa8 interr upt mo de register 0 clear imr0c write-only 0xac interr upt mo de register 0 toggle imr0t write-only 0xb0 interr upt mo de register 1 read/write imr1 read/write 0x00000000 0xb4 interr upt mo de register 1 set imr1s write-only 0xb8 interr upt mo de register 1 clear imr1c write-only 0xbc interr upt mo de register 1 toggle imr1t write-only 0xc0 gl itch filt er enab le register read/write gfer read/write 1b fo r each implemented gpio p in in port 0xc4 gli tc h fil t e r ena b l e r eg iste r set g fers w r i t e -o n ly 0 x c8 gli tc h fil t e r ena b l e r eg iste r cl ear g ferc wr i te-only 0xcc gl itch filt er enab le register toggle gfert write-only 0xd0 interr upt flag register read ifr r ea d-o nly 0x00000000 0xd4 interr upt flag register - - - 0xd8 interr upt flag register clear ifrc write-only 0xdc interr upt flag register - - - 0xe0- 0 xff reserved - - - tabl e 22-2. gpio register map offset register function name access reset value 32058k avr32-01/12 178 at32uc3a 22.5.2 gpio enable register name: gper acces s : read , write, set, clear, toggle ? p0-p31: gpio enable 0 = a peripher al function controls the correspondin g pin. 1 = th e gpio contro ls th e corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 179 at32uc3a 22.5.3 peripheral mux register 0 name: pmr0 acces s : read, write , set, cl ear, togg le ? p0-31: peripheral multiplexe r select bit 0 22.5.4 peripheral mux register 1 name: pmr1 acces s : read, write , set, cl ear, togg le ? p0-31: peripheral multiplexe r select bit 1 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 {pmr1, pmr 0} selected pe ripheral function 00 a 01 b 10 c 11 d 32058k avr32-01/12 180 at32uc3a 22.5.5 outpu t driv er enable register name: oder acces s : read, write , set, cl ear, togg le ? p0-31 : output driv er enable 0 = th e output driver is dis abled for th e correspondin g pin. 1 = th e o utput driver is enabled fo r th e corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 181 at32uc3a 22.5.6 ou tpu t value register name: ovr acces s : read, write , set, cl ear, togg le ? p0-31 : output value 0 = th e valu e t o b e d rive n on t h e i /o line is 0. 1 = th e valu e t o b e d rive n on t h e i /o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 182 at32uc3a 22.5.7 pin v alue r egister name: pvr acces s : read ? p0-31 : pin value 0 = the i/o line is at le ve l ?0?. 1 = the i/o line is at le ve l ?1?. note that th e level of a pi n ca n only b e read when gp er is set or interrup t is enabled for th e pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 183 at32uc3a 22.5 .8 pull- up enab le register name: pu er acces s : read, write , set, cl ear, togg le ? p0 -31 : pull - up enable 0 = th e intern al pull-u p resist or is disabled for the corresponding pin. 1 = th e intern al pull-u p resist or is enabled for t he corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 184 at32uc3a 22.5.9 op en drai n mod e enabl e register name: odmer acces s : read, write , set, cl ear, togg le ? p0-31 : open drai n mode enable 0 = op en dr ain mode is disa bled for the corresponding pin. 1 = op en dr ain mo de is en a ble d fo r t he corr esp ond in g p in. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 185 at32uc3a 22.5.10 interr up t enabl e r egister name: ier acces s : read, write , set, cl ear, togg le ? p0-31: interrup t enable 0 = i nterrup t is disable d for t he correspondin g pin. 1 = i nterrup t is enabled for th e correspond ing pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 186 at32uc3a 22.5.11 interrup t mode register 0 name: imr0 acces s : read, write , set, cl ear, togg le ? p0-31: interrupt mode bi t 0 22.5.12 interrup t mode register 1 name: imr1 acces s : read, write , set, cl ear, togg le ? p0-31: interrupt mode bi t 1 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 {imr1, imr0} interru pt mode 00 pin ch ange 01 ri sing edge 10 falli ng edge 11 reserved 32058k avr32-01/12 187 at32uc3a 22.5.13 glitch filt er enable register name: gf er acces s : read, write , set, cl ear, togg le ? p0 -31 : glitch filter enab le 0 = gli tch filter is disabled for th e corresponding pin. 1 = gli tch filter is enabled for the corresponding pin. note! the va lue o f t h is registe r shou ld o n ly b e ch ange d whe n ie r is ?0?. upda tin g th is gf er while interrup t o n th e corr e- sponding pin is en abled ca n cause an unintentional interrup t to be triggered. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 188 at32uc3a 22.5.14 interr up t fl a g r egis t er name: ifr acces s : read, clear ? p0-31: interrup t flag 0 = a n interrupt conditio n has been detecte d on th e correspond ing pin. 1 = n o interrup t conditi on ha s bee n detecte d o n th e correspondin g pin. the n u mber of interr upt request line s is dependant on the n u mber o f i /o pins on the mcu. refer to t he product specific data for details . not e also that a bi t in the interrupt flag re gist er is only va lid i f the corr espo ndi ng bit in ier is se t. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 32058k avr32-01/12 189 at32uc3a 22.6 p rogrammi ng examples 22.6.1 8-bit led-chaser // set r0 to gpio base address mov r0, lo(avr32_gpio_base_address) orh r0, hi(avr32_gpio_base_address) // enab le gpio control of pin 0-8 mov r1, 0xff st.w r0[avr32_gpio_gpers], r1 // set initial value of port mov r2, 0x01 st.w r0[avr32_gpio_ovrs], r2 // set up toggle value. t wo pins are toggled // in e ach round. the bit that is currently set, // and t he next bit to be set. mov r2, 0x0303 orh r2, 0x0303 loop: // only change 8 lsb mov r3, 0x00ff and r3, r2 st.w r0[avr32_gpio_ovrt], r3 rol r2 rcall delay rjmp loop it is ass umed in th is example that a sub routine "delay " exists that return s after a give n time. 22.6.2 configurat ion of usar t pins th e example be low show s how to configure a p eripheral module to control i/o pins. it assumed in this example that the usart receive pin (rxd) is connected to pc16 and tha t th e usart tra nsmit pin ( tx d ) i s c o nn ecte d t o pc17 . f o r both pins , t he usart is p eripher al b . in this example, the s ta te of the gpio regi sters is assu med to be unknown. t he two usart pins are the ref or e firs t se t to be con trolled by th e gpio wit h output driver s disabled . the pi ns can the n be assured to be tri-stat ed while changing t he peripher al mux registers. // set up pointer to gpio, portc mov r0, lo(avr32_gpio_base_address + portc_offset) orh r0, hi(avr32_gpio_base_address + portc_offset) // disa ble output drivers 32058k avr32-01/12 190 at32uc3a mov r1, 0x0000 orh r1, 0x0003 st.w r0[avr32_gpio_oderc], r1 // make the gpi o control the pins st.w r0[avr32_gpio_gpers], r1 // sele ct peripheral b on pc16-pc17 st.w r0[avr32_gpio_pmr0s], r1 st.w r0[gpio_pmr1c], r1 // enab le peripheral control st.w r0[avr32_gpio_gperc], r1 32058k avr32-01/12 191 at32uc3a 23. serial peripheral interface (spi) re v: 1.9.9.3 23.1 features ? suppor ts communication with serial ex ternal devices ? four ch ip selects with e x ternal decoder sup po r t allow co mm u nic atio n wit h up t o 15 peripherals ? serial me mories, such as dataflash and 3-wire eep roms ? s erial peripherals, such as adcs, dacs, lcd controllers, can cont roller s and sensors ? e xter nal co-processors ? maste r or sl a v e serial pe riphe r al bus interface ? 8 - to 16-bit programmabl e data length p er chip select ? p rogrammabl e pha se and polarity pe r chip select ? programmable tr ansfer delays between conse cutive transfer s and be tween clock and data pe r chip select ? p rogrammabl e delay betwee n consecutive transfers ? s elect ab l e mode fa ult de tection ? connection to p dc channe l capabi litie s optimize s da ta transfers ? o ne channel fo r th e receiver , o n e channel fo r the transmitter ? nex t buff er support 23.2 description th e serial peripheral interface (spi) circui t is a synchron ous serial data link t hat provides com- munica tion with extern al device s in maste r or slave mode . it also enable s communication betwe en processors if an external processor is con nected to th e system. t he serial periph eral interface is esse n tially a shift regi ster tha t se rially transm its da ta bits to othe r spi s. during a data transfer, o ne spi system acts as the ?master? ' which controls the data flow, while th e othe r de vices act as ?sla ves'' whic h hav e dat a shifte d int o an d ou t by t he master. different cpus ca n take turn being master s (multip le master protocol opposite to sing le master prot ocol where one cpu is always the master while all o f th e others ar e always slaves) an d one master ma y simultaneo usly shift data int o mult ip l e sla ves. h owever, on ly on e slave may dr ive its output to writ e dat a ba ck to th e maste r at any give n time. a sl ave device is s elected when th e master assert s it s nss signal . if multip le slave devices exist, t he master generat es a separat e slav e select signal fo r ea ch slave (npcs). th e spi syst em consists of tw o data lines an d two contro l lines: ? master out slav e in (mosi): this data line supplie s th e outpu t data from th e master shifted into th e input(s) o f the slave(s). ? maste r i n sla v e o u t (mis o): this d ata line suppli es t he outp ut dat a fro m a sl a v e t o th e inp ut of t he master. ther e ma y b e no more th an one slav e transmittin g da ta during any particular transfer. ? seria l clock (spck): th is contro l line is driven by the master and regulates t he flow o f the data bits. th e master may transm it dat a at a variet y of baud rates; t he spck line cycles once for each bi t that is transmitted. ? slave se lect (nss ): this control line allows slaves t o be turned on an d off by hardware. 32058k avr32-01/12 192 at32uc3a 23.3 block diagram figur e 23-1. blo ck diagram spi interface interrupt control pio pdc power manager mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 div npcs3 eral bus mck 32 (1) 32058k avr32-01/12 193 at32uc3a 23.4 a pplication bloc k diagram figur e 23-2. applicatio n block diagram: sing le master/multiple slav e implementation spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3 32058k avr32-01/12 194 at32uc3a 23.5 s ignal description tabl e 23-1. signa l descr ipti on pi n name pi n description type master slave miso master i n slav e out input output mosi master ou t slav e in output input spck se r ial cl o ck o u t p ut inp ut npcs1-npcs3 perip heral chip selects output unused npcs0/nss perip heral chip select/slave select output input 32058k avr32-01/12 195 at32uc3a 23.6 p roduct dependencies 23.6.1 i/ o li nes th e pi ns used fo r int erfacin g th e comp lia nt external devices ma y be multip lexed wit h pio lines. th e programmer must first program the pio controllers to assign the spi pins to their peripheral functions. to use the loca l loop back function the s pi pins mu st b e con trolle d by t he spi. 23.6.2 power management th e sp i cloc k is ge ner ate d b y t he powe r m ana ger . be for e usi n g th e sp i, t h e p ro gra mme r must ens ur e tha t the spi cloc k is ena ble d i n th e powe r m ana ger. in th e spi description, master clock (mc k ) is th e clock of th e per ipheral bus to wh ich the spi is connected. 23.6 .3 interrupt the sp i interface has an inte r rupt line connected to the int errupt controller. handling the spi interrupt require s programming the interrup t controller befor e configuring the spi. 32058k avr32-01/12 196 at32uc3a 23.7 functional description 23.7.1 mo des of operation th e sp i o pe rate s i n ma ster mode o r i n s lave mo d e. operatio n i n mas te r mo d e is p ro gr a mmed b y writ ing at 1 th e ms t r bi t in th e mo de regist er. the pins npcs 0 to npcs3 are al l configured as outputs , th e spck pin is driven , the miso line is wi r ed on th e receive r input an d th e mosi li ne d r iven as a n output by t h e tr an smitter . if t h e mstr bit is written at 0, the spi operates in slave m o de. th e miso line is driven by t he trans mi tter output, the mos i line is wir e d on the r e ceiver input , the spck pin is dr iven by the transmitte r to synchr onize th e receiver. the npcs0 pin b ecome s an inpu t, and is us ed as a slave s e lect signal (nss) . th e pins npcs1 to npcs3 are not driven a nd can be used for other purposes. t he da ta transfers a re iden tica lly pr ogrammab le fo r bot h mo d es of o per ati o ns. th e ba ud rate generato r is acti v ate d on ly i n master mo de. 23.7.2 data transfer four combinations o f po larity and phas e ar e availa ble fo r da ta transfers. the clock p o larity is programmed with t he cpo l bi t in t he chip se lect register. th e clock p hase is programmed with t he ncpha bit. these two pa rameters determine the edge s of th e clock signa l on wh ich data is dr iven and sampled. each o f the two parameters ha s two possible states, resultin g in four possi- ble combinations that ar e incompatib le with on e another. thus, a master/slave pair must use the same parameter pair valu es to communicate. if multiple slaves are used and fixed in differen t configurations , t he mast er must reconfigure itself each ti me it n eeds to communicat e with a d if- ferent slave. ta ble 23-2 show s the fou r modes a nd corresponding parameter settings. figure 23-3 and figur e 23-4 sh ow exampl es of data transfers. tabl e 23-2. spi bus protocol mode spi mode cpol ncpha 0 0 1 1 0 0 2 1 1 3 1 0 32058k avr32-01/12 197 at32uc3a figur e 23-3. spi transfer format (ncpha = 1, 8 b i ts pe r transfer) figur e 23-4. spi transfer format (ncpha = 0, 8 b i ts pe r transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2 3 4 5 7 8 6 * spck (cpol = 0) spck (cpol = 1) 1 2 3 4 5 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6 32058k avr32-01/12 198 at32uc3a 23.7.3 mast er mod e operations whe n con figured in mast er mode , t he spi us es th e in ter na l prog ram mabl e b aud rat e ge ne rato r as clock source . it fully controls th e data transfe rs to and from th e slave(s) connected to t he spi bu s. the spi drives the ch ip select lin e to t h e slav e a nd th e serial cloc k signal ( sp ck). th e s pi featur e s two holdi ng register s, th e tra nsmit data register an d th e receive d at a r egi s- te r , an d a si ngle shift registe r . t h e holdin g re gisters maintai n th e dat a flow a t a c o nstan t rate . afte r enabling t he spi, a da ta transfer begins when th e processo r writes to the t dr (transmit data register). the w ritten data is imme diat ely transferred in t he shift register and transfer on t he spi b u s star ts. wh ile t he data in t h e shift regist er is shi fte d on t he mos i line, the mi so line is s ample d and shifted in th e shif t register . transmission cannot occur without reception. before writing the tdr, th e pcs fi eld must be set in order to se lect a slave. if n e w dat a is writ ten in t dr durin g th e transfer , it st ays in it un til the curre nt transfer is co m- pleted. then, the receive d data is tran sf erred from the shift re gister to rdr, the data in td r is loaded in the sh ift registe r and a ne w transfer starts. the tran sfer of a data writte n in tdr in th e s hift register is i ndicate d by th e tdre bit (transmit data register empt y) in t he st at us register (sr). wh en new data is w ritte n in tdr , th is bit is cleared. the tdre bi t is used to trigge r th e tran smit pdc channel. th e end of transfer is indica te d by the txempty fl ag in t he sr register . if a transfer de lay (dly- bct ) is greater than 0 for th e last transfer, tx empty is set after the co m pletion of said delay. the master clock (mck) can be s witched of f at this time. the transfe r of received dat a from t he shif t regist er in rdr is indicat ed by th e rdrf bit (receive d ata register full) in the status r egister (sr). when the rec e ived data is read, the rd rf bi t is cleared. if th e rdr (r eceive data register ) ha s not been rea d befor e new dat a is received, the overrun error bit (ovres) in sr is set . when this bit is se t the spi will c ontinue t o upda te rdr when data is received, overwriting t he previously received data. th e user has to read the status regis- te r to clea r th e ovres bit. figur e 23- 5 o n pag e 199 shows a b lock diagram of t he spi whe n operat ing in maste r mode. fig- ur e 23- 6 o n pa ge 200 shows a flow chart describ ing how transf ers ar e handled. 32058k avr32-01/12 199 at32uc3a 23.7.3.1 m aste r m od e bloc k d iagr am figur e 23-5. master mod e block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits 0 1 fdiv mck mck/n baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr 32058k avr32-01/12 200 at32uc3a 23.7.3.2 master mode flow diagram figur e 23-6. master mod e flow diagr am s spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0. 32058k avr32-01/12 201 at32uc3a 23.7.3.3 clock generation t he spi bau d rate cloc k is generated by dividin g the master clo ck (mck ) or th e master clock d ivi d e d b y 32 , b y a v alu e b etwe e n 1 an d 2 5 5. th e selectio n bet we en mast er cl oc k o r ma st e r clock divide d by 32 is d o ne by t he fdiv valu e set in th e mode register this allows a maximu m operat ing ba ud rate at up to master clock a nd a minimum operatin g baud rat e of mck divided by 255*32. programming t he scbr field at 0 is forbidden . triggering a transfer while scbr is at 0 c a n lead to unpredictabl e results. at reset, scbr is 0 and the user has to pro g ram it at a valid valu e be fore p erforming the first transfer. the divisor can be defin ed independent ly for ea ch chip select, as i t ha s to be programmed in the scbr fi eld of th e chip se lect registers. this allows the spi to automa tically adap t the baud rat e fo r each interface d peripher al without reprogramming. 23.7.3.4 transfe r delays figure 23-7 shows a c h ip selec t transfer chan ge and consecut ive transfer s on th e same chip selec t. thre e delays ca n b e programme d t o modify th e transfer waveforms: ? the dela y between ch ip selects, programmable only o nce for a ll th e chip selects by writing the dl ybcs fiel d in th e mo de register. allo ws insert ion of a delay between release of o ne chip select an d before assert ion of a new one. ? the delay before spck, independent ly programmable fo r each chip select by writing the field dlybs. allo ws th e star t of spck to be d elaye d after t he chip sele ct ha s bee n asserted. ? the dela y between consecutive transfers, independently programmable for each chi p select by writing t he dlybct field. allo ws insertio n of a d ela y between two transf ers occurr ing on the same ch ip select these dela ys allo w the sp i t o be a dapte d to th e interfaced p eriphera ls an d their spee d an d b us releas e time. figur e 23-7. prog r am m ab l e d ela ys dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck 32058k avr32-01/12 202 at32uc3a 23.7.3.5 periphera l selection the se rial peripher als are selected t hrough th e assert ion of th e npcs0 t o npcs3 signals. by default, all the npcs si g nals ar e high befor e an d afte r ea ch transfer. the periphe r al s electi o n can b e performe d i n tw o different ways: ? fixed peripher al select: spi exchanges data wi th on ly on e peripheral ? variable peripheral select: data ca n be exchange d wit h mor e than o ne peripheral fixed peripheral select is ac ti vated by writing t he ps bit t o zero in mr (mode register). in this case, t he current peripher al is defined by the pcs field in mr a nd t he pcs fiel d in tdr ha ve no effect. variab le peripher al select is activated by se tting ps bi t t o one. t he pcs fiel d in tdr is us ed to select th e current periph eral. this m e a n s th a t th e periphe ra l se lectio n ca n b e d e fin ed for eac h ne w data. the fix ed pe r i phera l s electi on a llo ws b u ffer transfer s wit h a single periphera l. usi n g t he p d c i s an optimal means, as the size of th e data transf er between t he memory and t he spi is either 8 bit s or 16 bi ts . howev er, c han gin g th e pe riphe ra l sel ecti o n re q u ires th e mod e regi ste r to be reprogrammed. th e variab le peripher al selectio n allows buffer transfers with mult iple periphera ls without repro- gramming the mo de register . data writte n in td r is 32 bits wid e a nd defines th e real data to be transmitted and the peripher al it is d estined to. using the pd c in this m ode requir es 32-bit wide buf fers, wit h the dat a in th e ls bs an d the pcs an d lastxf er fie lds i n th e msb s, howeve r t he spi still controls the number of b its (8 to16) to be t r an sf er r ed t hro ugh mi s o and m o si line s wit h t he ch ip se lect configuration register s. this is no t the optimal mean s in te rm of memory size for the buffers, b u t it provides a very ef fective m eans to exchan ge data with severa l peripherals without an y interventio n of th e processor. 23.7.3.6 p e riphe ra l chip selec t de c oding the user can pr o gram the spi to o perate with u p to 15 p erip h erals by deco d ing the fo ur chip select lines, npcs0 to npcs 3 with an exter nal logic. this can b e en abled by writ ing the pcs- d e c bit at 1 i n t he mod e re giste r (mr). when operating without decoding , the spi make s sure that in any c as e o nly on e ch ip se lect line is activa ted, i.e. dr iven lo w at a time . if two bits are defin ed lo w in a pcs field, only t he lowest numbered ch ip selec t i s d riv en low . when operatin g wi t h de c oding , t he sp i d i rectly outputs t he value def ined by t he pcs fiel d of either the mode registe r or the transm it data registe r (dependi ng on ps). as the spi se ts a default va lue of 0xf o n the ch ip select lines (i.e. a ll ch ip select lin es at 1) when no t processin g a ny t ra nsfer, only 1 5 p er iphera ls can b e de code d. th e spi has only fo ur chip select registers, not 15. as a re sult, when decoding is activated, ea ch chip select defines t he characteristics of up to four peripherals. as an exam ple, crs0 defines the characteris t ics o f t he ext ernally decoded peripheral s 0 t o 3, corresp onding to the pcs values 0x0 to 0x3. thus, the user has t o make sure t o connect compatible peripherals o n t he de code d chip select lines 0 to 3 , 4 to 7, 8 t o 1 1 a nd 12 t o 1 4. 32058k avr32-01/12 203 at32uc3a 23.7.3.7 periphera l deselection when operating nor mally, as soon as the tr ansfer of the last d a ta written in t dr is completed, t he npcs lines all rise . this might lead to runt ime erro r if t he processor is too lo ng in responding to an interrupt, and thus migh t lead t o difficultie s fo r interfacing with some seri al peripherals requiring the chip sele c t line t o rema in activ e durin g a full set of transfers. to facilitate interfacing with such devices, the chip select regi ster ca n be prog rammed with the csaa t bit (c hip select active after transfer ) at 1. th is allows th e chip select lines to remain i n thei r cur ren t stat e (lo w = active) unti l tra nsfer t o a n other p er iphera l is req uired. figure 23-8 shows different peripheral deselection cases and the effect of the csaat bit. figur e 23-8. per i phera l des election a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct a a csaat = 0 dlybct a a csaat = 1 a 32058k avr32-01/12 204 at32uc3a 23.7.3.8 m o de f aul t dete ction a m ode fault is detected when the spi is p rogrammed in mas ter mo de an d a low l e vel is driven by an exter nal mast er on the npcs0/ nss signa l. npcs0, mosi, mi so an d spck must be con- figured in open-drain through the pi o controller, so that external pull up resistors are need ed to guarantee high level. whe n a mod e f aul t is d e tecte d, th e mo df bit in t h e sr is set until t he sr is rea d an d t he sp i is automati cally disabled until re-enabled by writing the spie n bit in the cr (contro l register ) at 1. by de fault, the mode faul t detection circuitr y is enabled . the user can disabl e m ode fault det e ctio n b y s ettin g th e mo dfdis bi t in the s pi mod e reg ister (mr). 23.7.4 spi sl a ve mode when operatin g in slave mode, the spi pr ocesses data bi ts on the clock provided on the sp i clock pin (spck). th e sp i w ait s f o r ns s t o g o a cti v e b e f o re rec ei v ing th e s e r i al clock fro m a n ex tern al maste r. when nss falls , th e cl ock is validate d on th e serializer, which processes th e number of bits defined by t he bits fiel d o f the chip s elect regist er 0 (csr0). these bits are processed follow- in g a phas e a nd a polari ty defined respectively by t he ncpha and cpo l bi ts o f th e csr0. note that bits, cpol an d ncpha o f the othe r ch ip select register s hav e no effect when the spi is programmed in s l ave mode. th e bi ts are shifte d o ut o n th e mis o li n e a n d samp le d o n th e mosi line. whe n all th e bit s a re process e d, th e r eceive d d a t a is t ra nsf erre d i n th e receive dat a regi st e r and the rdrf bit rises. if rdrf is already high w h en the data is transf err ed , t he overru n b i t rise s and t he data transfer to rdr is ab orted. when a transfe r starts, th e dat a shifte d o ut is t he da ta prese nt in t he shift register. if n o data ha s be en writte n in the transm it dat a registe r (tdr) , th e las t dat a received is transferred . if no data ha s been received since t he last reset, a ll bits are transmitte d low, as t he shift register resets at 0. when a first da t a is writ ten in tdr, it is transferr ed immediately in t he shif t register and th e tdre bit rises. if new data i s writ ten, it remains in td r until a transfer occurs, i.e. nss fa lls and ther e is a va lid clock on the spck pin. when the transfer occurs, the last dat a writte n in td r is transferred in the shift regist er an d th e tdre bit rises. this enab les frequen t update s of critical variables wit h single transfers. then, a n ew da t a is load ed in t he shif t register from t he tra nsmit data register. in case n o character is r ead y to be transmitted, i.e. no character has been written in tdr si nce t he last load from tdr to th e shif t register , th e shift register is n o t modified and the last received character is retransmitted. figure 23-9 shows a block dia gra m o f the spi when operating in slave mode. 32058k avr32-01/12 205 at32uc3a figur e 23-9. slave m o de functiona l bloc k diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits fload spien spidis miso 32058k avr32-01/12 206 at32uc3a 23.8 serial peripheral inte rface (spi) user interface tabl e 23-3. spi regis te r mapping offset register register name access reset 0x00 control re gister cr write-only --- 0x04 mo de register mr read/write 0x0 0x08 receiv e data register rdr read-only 0x0 0x0c tr ansmit data register tdr write-only --- 0x10 status re gister sr read-only 0x000000f0 0x14 interrup t enable register ier write-only --- 0x18 interrup t disable register idr write-only --- 0 x 1c i nt er ru p t ma sk re g is t er imr r ea d -only 0x0 0x 20 - 0x2c reserved 0x30 chip sele ct re gister 0 csr0 read/write 0x0 0x34 chip sele ct re gister 1 csr1 read/write 0x0 0x38 chip sele ct re gister 2 csr2 read/write 0x0 0x3c chip sele ct re gister 3 csr3 read/write 0x0 32058k avr32-01/12 207 at32uc3a 23.8.1 spi cont r o l r egister name: cr acces s type: write-only ? spien: spi ena ble 0 = n o e ffect. 1 = e nables the spi to transfe r an d re ceive data. ? spidis: s p i disable 0 = n o e ffect. 1 = disa bl es th e spi. as s oo n a s sp dis is set, spi fi nish es its transfer. all pins a r e set in inpu t mo de an d n o data is receive d or transmitted. if a t ransfer is i n progress, th e transfer is finished before the spi is dis abled. i f bo t h sp ie n an d spid i s ar e equal to on e whe n th e control register is w ritt en, th e spi is disab le d. ? swrst: spi software rese t 0 = n o e ffect. 1 = r eset the spi . a software-trigger ed hardwar e reset of th e spi interf ace is performed. the sp i is i n sl ave mode afte r a software rese t. pdc channels are no t affected by softwar e reset. ? lastxfer : last transfer 0 = n o e ffect. 1 = the current n p cs will be deass erted afte r the ch aracter writ ten in td has been transferred. when csa a t is set, thi s allows to close the communication with the current serial periphe r al by ra isin g th e corr esp onding npcs line as s oo n as td transfe r has completed. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? lastxfer 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 swrst ? ? ? ? ? spidis spien 32058k avr32-01/12 208 at32uc3a 23.8.2 spi mo de r egister name: mr acces s type: read/write ? mstr: maste r/sla ve mode 0 = sp i is in slav e mode. 1 = s pi is in master mode. ? ps: pe ripheral select 0 = fixed pe ripheral select. 1 = v ariable peripher al select. ? pcsdec: chip selec t deco de 0 = th e chip se lects ar e dire ctly connected to a pe riphera l device. 1 = th e four chip sel ect lines ar e connected to a 4 - to 16-bit decoder. when pcs dec eq ua l s one, u p t o 15 chip select sig n als ca n b e generate d wit h the four lines using a n exter nal 4- to 16-bit decoder. the chip select registers define the characterist ics of th e 15 chip select s according to the following rules: csr0 d efin es peripheral chi p select signals 0 to 3. csr1 d efin es peripheral chi p select signals 4 to 7. csr2 d efin es peripheral chi p select signals 8 to 11. csr3 de fines periphera l chip se lect signals 12 to 14. ? fdiv: cloc k selection 0 = th e spi operates at mck. 1 = th e spi operates at mck/32. ? modfdis: mode fa ult detection 0 = mo de fault detection is en abled. 1 = mo de fault detection is disabl ed. ? ll b: local loopbac k enable 0 = local l oopback path disabled. 1 = local l oopback path enabled. llb co ntr ol s t h e local loopba c k on t he da t a ser i alizer for t estin g in master m ode on ly. miso is internally conn ected to mosi. 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ? ? ? ? pcs 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 llb ? ? m o dfdis fdi v pc sdec ps m str 32058k avr32-01/12 209 at32uc3a ? pcs: peripher al chip select this field is only use d if fixed peripher al select is active (ps = 0 ). if pcs d ec = 0: pcs = x xx0 npcs[3:0 ] = 1110 pcs = x x01 npcs[3:0 ] = 110 1 pcs = x 011 npcs[3:0 ] = 1011 p c s = 01 11 npc s [3:0] = 0 111 pcs = 1 111 forbidden (n o periphera l is selected) ( x = do n? t ca r e) if pcs d ec = 1: npcs[3:0 ] output sig nals = pcs. ? dl ybcs: dela y betwee n chip selects th is fiel d defin e s th e de lay fr om npcs ina c tive t o t he activation of another npcs. th e dlybcs ti me guarantee s non-over- lappin g chi p se lects an d s o lves bu s c onten tio ns in c as e of peripherals h aving lon g data flo a t time s. if dlybcs is less than o r equal to six, six m c k periods (or 6*n mc k periods if fdiv is set) w ill be inserted by default. otherwise, the following equa tio n determines t he delay: if fdiv is 0: if fdiv is 1: de lay between chip selects dlybcs mck ------------------ ------ = de lay between chip selects dlybc s n mck --------------------------------- = 32058k avr32-01/12 210 at32uc3a 23.8 .3 spi receiv e data register name: rdr acces s type: read-only ? rd: rec eiv e data dat a received by the spi i nterface is stored in th is registe r right-justified. unuse d bits read zero. ? pcs: peripher al chip select in master mode only, th ese bits indicate th e valu e on th e npcs pi ns a t the end of a transfer. otherwise, these bits read zero. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? pcs 15 14 13 12 11 10 9 8 rd 7 6 5 4 3 2 1 0 rd 32058k avr32-01/12 211 at32uc3a 23.8 .4 spi transmit data register name: tdr acces s type: write-only ? td: transmit data data t o be transmitte d by t he spi interf ace is stor ed in t his register. information t o be transmitted must be w ritten t o the transm it dat a register in a right-justified format. pc s: per ipher a l ch ip select this field is only use d if variable pe rip her al select is acti ve (ps = 1). if pcs d ec = 0: pcs = x xx0 npcs[3:0 ] = 1110 pcs = x x01 npcs[3:0 ] = 110 1 pcs = x 011 npcs[3:0 ] = 1011 p c s = 01 11 npc s [3:0] = 0 111 pcs = 1 111 forbidden (n o periphera l is selected) ( x = do n? t ca r e) if pcs d ec = 1: npcs[3:0 ] output sig nals = pcs ? lastxfer : last transfer 0 = n o e ffect. 1 = the current n p cs will be deass erted afte r the ch aracter writ ten in td has been transferred. when csa a t is set, thi s allows to close the communication with the current serial periphe r al by ra isin g th e corr esp onding npcs line as s oo n as td transfe r has completed. this field is only use d if variable pe riphe r al sel ect is acti ve (ps = 1). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? lastxfer 23 22 21 20 19 18 17 16 ? ? ? ? pcs 15 14 13 12 11 10 9 8 td 7 6 5 4 3 2 1 0 td 32058k avr32-01/12 212 at32uc3a 23.8.5 spi stat us register name: sr acces s type: read-only ? rdr f : r ece iv e d a ta r e g i ster fu ll 0 = n o d ata ha s bee n received since the la st rea d of rdr 1 = data has been received and the recei v ed data has been transferred from the serial i zer to rdr si nce the la st read of rdr. ? tdre: tr ansmit data register empty 0 = d at a h as bee n written t o tdr an d no t ye t transferre d to th e serializer. 1 = th e last da ta writte n in the transm it data registe r has been transferre d to th e serializer. tdre equa ls zero when th e spi is disabled o r at reset. th e spi enable comman d sets th is bi t to one. ? modf : mode fault error 0 = n o mod e fault ha s been detecte d since th e las t rea d of sr. 1 = a m ode fault occurred since the last read of t he sr. ? ovr es: overrun erro r status 0 = no overru n has bee n detecte d sinc e th e last read of sr. 1 = a n ove rru n ha s o ccur red si nce the last rea d of s r. an ov err un occurs when rdr is loaded at least twi c e from the serializer sinc e the last read of th e rdr. ? endrx: end of rx buffer 0 = the receive counter register ha s not reach ed 0 since the la st wr ite in rcr o r rncr. 1 = the receive counter register has reached 0 si n c e th e la s t writ e i n rcr o r rn cr. ? endt x: en d of tx buffer 0 = the transm it counter register ha s not reache d 0 since the last write in tcr o r tncr. 1 = the transm it counter register ha s reache d 0 since th e last write i n tc r o r tncr. ? rx bu ff: r x buff er full 0 = r cr o r rncr has a val u e other th an 0. 1 = both r cr and rnc r has a value of 0. ? txb u fe : tx b uff er em pty 0 = tcr o r tncr has a valu e o ther th an 0. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? spiens 15 14 13 12 11 10 9 8 ? ? ? ? ? ? txempty nssr 7 6 5 4 3 2 1 0 txbufe rxbuff endtx endrx ovres modf tdre rdrf 32058k avr32-01/12 213 at32uc3a 1 = bo th tcr a n d t ncr ha s a valu e o f 0. ? nssr: nss risin g 0 = n o ri sing edg e de tected on nss pin since last read. 1 = a rising ed ge occurred on nss pi n since last read. ? txempty: transmissi on register s empty 0 = as soon as data is writte n in tdr. 1 = tdr an d inte r nal shi fte r ar e empty . i f a tra nsfe r de lay has be en defined, txempty is se t afte r th e comp leti on of such delay. ? spien s: spi ena ble st atus 0 = sp i is disa bled. 1 = sp i is enabled. 32058k avr32-01/12 214 at32uc3a 23.8 .6 spi interrupt enable r egister name: ier acces s type: write-only ? rdrf: receiv e data register full in terru pt enable ? t dre: spi transmit da ta regist er empty interrupt enable ? modf : mode faul t erro r inte rrupt enable ? ovr es: overrun erro r interrupt enable ? endrx: end of receive bu ffer inte rrupt enable ? endtx: end of tr ansmit buff er interrupt enable ? rxbuff: receive buffer full int e rrupt enable ? txbufe: transmit buffer em pty inte r r upt enable ? txempty: transmissi on register s empty enable ? nssr: nss rising interrup t enable 0 = n o e ffect. 1 = e nables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? txempty nssr 7 6 5 4 3 2 1 0 txbufe rxbuff endtx endrx ovres modf tdre rdrf 32058k avr32-01/12 215 at32uc3a 23.8 .7 spi interrupt disable register name: idr acces s type: write-only ? rdrf: receiv e data register full interru pt disable ? tdre: spi transmit data regist er empty interrupt disable ? modf : mode faul t erro r inte rrupt disable ? ovr es: overrun erro r interrupt disable ? endrx: end of receive buffer inte rrupt disable ? endtx: end of transm it buffer interr upt disable ? rxbuff: receive buffer full int e rrupt disable ? txbufe: transmit buffer em pty interrupt disable ? txempty: transmissi on register s empty disable ? nssr: nss rising interrup t disable 0 = n o e ffect. 1 = disa bl es th e co rr espo ndi ng interru pt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? txempty nssr 7 6 5 4 3 2 1 0 txbufe rxbuff endtx endrx ovres modf tdre rdrf 32058k avr32-01/12 216 at32uc3a 23.8 .8 spi interrup t mask register name: imr acces s type: read-only ? rdrf : re ceiv e dat a r e gi ste r fu l l int err up t ma sk ? tdre: spi transmit data regist er empty interrup t mask ? modf : mode faul t erro r inte rrupt mask ? ovr es: overrun erro r interrupt mask ? endrx: end of receive buffer inte rrupt mask ? endtx: end of tr ansmit buff er interrupt mask ? rxbuff: receive buffer full int e rrupt mask ? txbufe: tr ansmit buf fer em pty interrupt mask ? txempty: transmissi on register s empty mask ? nssr: n s s ris ing in t err up t ma sk 0 = th e corresponding interrup t is not enabled. 1 = th e corresponding interrup t is enabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? txempty nssr 7 6 5 4 3 2 1 0 txbufe rxbuff endtx endrx ovres modf tdre rdrf 32058k avr32-01/12 217 at32uc3a 23.8.9 sp i c h ip se lec t register name: csr0... csr3 acces s type: read/write ? cpol: clock polarity 0 = th e i n activ e stat e v alu e o f s pc k is l o gic l evel zero. 1 = th e in active stat e valu e of spck is logic level o ne . cpol is us ed t o determine th e inactive st ate value o f t he seri al clock (spck) . it is used wi t h ncpha to prod uce the required clock/dat a relationshi p betwee n master an d slave devices. ? ncp ha: clock phase 0 = d ata is cha n ged on t he leading ed ge o f spck a n d c aptu r ed on th e f ollowin g e d ge of spck. 1 = d ata is cap ture d on t he leadin g edg e of spck and changed on th e followin g edge of spck. ncpha determi n es which e dge of spck causes data to chang e and w h ich edg e causes data t o be captured. ncpha is used with cpol to produce t he required clock/dat a relationshi p betwee n master an d sl ave devices. ? csnaat: chip se lect not ac tive after transfer 0 = th e peripher al chip select line rise s as so on as th e las t tr ans fe r is ach eived 1 = th e peripher al chip select line rises a fte r every transfer csnaat can be use d to force th e periph e ral chip sele ct line to go i nactive after eve ry tran sfer. th is allo ws successful interfacing to spi slave devices that require th is behavior. ? csaat : chip select active after transfer 0 = th e peripher al chip select line rises as s o on as th e las t tr ansfer is achi eved. 1 = t h e peripher al chip select does not rise after t he las t transfer is achi eved. it rema ins active unt il a new transfer is request ed o n a different chip select. ? bits: bits per transfer the bits fi eld det ermines the number of dat a bits transferred. reserved values should no t be used, see table 23-4 o n pag e 218. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 7 6 5 4 3 2 1 0 bits csaat csnaat ncpha cpol 32058k avr32-01/12 218 at32uc3a . ? scb r: serial clock ba ud rate in master mode, th e sp i interfac e uses a modulus counter t o derive the spck ba ud rate from th e master clock mck. the baud rate is sel ected by writing a value from 1 t o 25 5 in th e scbr field. the follo wing equations determine t he spck baud rate: if fdiv is 0: if fdiv is 1: note: n = 32 programming the scbr fiel d at 0 is f orbidden. triggerin g a trans fer while sc br is at 0 can l e ad to unpredict able results. at reset, scbr is 0 a n d th e user has t o p rogra m it at a vali d valu e befor e performing the firs t transfer. ? d lybs: dela y befo re spck this fiel d defines t he delay from npcs va lid to the fir st valid spck transition. when dlybs equa ls zero , th e npcs va lid to spck t ransition is 1 /2 t he spck clock period. tabl e 23-4. bits, bits per transfe r bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved spck baudrate mck scbr ------------ ---- = spck bau drate mck n scbr u ------------------------------ = 32058k avr32-01/12 219 at32uc3a otherwise, the following equations determine t he delay: if fdiv is 0: if fdiv is 1: note: n = 32 ? dlybct: dela y betwee n consecutive transfers this fi eld defines t he delay between two consecutive tr ansf ers wit h t he same peri p heral withou t removing t he chip select. th e de lay is always inserted afte r each transfe r an d before removing the ch ip select if needed. when dl ybct equa ls zero, n o dela y betwee n consecutive transfer s is inserted an d th e cloc k keep s it s du ty cycle over the characte r transfers. otherwise, the following equa tio n determines t he delay: if fdiv is 0: if fdiv is 1: n = 32 de lay bef ore spc k dlybs mck -------------- ------ = de lay bef ore spc k n dlybs u mck ------------------------- ----- = de lay betwe en consecut ive transfers 32 dlybct u ------------------------------------ scbr mck 2mck -------------- ---- + = de lay betwe en consecut ive transfers 32 n u dlybct u mck --------------------------------------------- --- n scbr u 2mck ------------------------- + = 32058k avr32-01/12 220 at32uc3a 24. two-wire in terface (twi) 2.1.1.0 24.1 features ? compatibl e wi th atmel two-wir e interfac e serial memor y an d i2c compatibl e devices (1) ? one, tw o or three bytes for sla ve address ? sequen tial read-w rite operations ? maste r , multi- m aste r an d sl a ve mode opera t ion ? bit rate: up to 400 kbits ? ge n er al cal l su pp or te d i n s lav e mode ? connectio n to periphera l dma cont ro lle r (pdc) channel ca pa bi lities optimiz es data tr ans fe r s in maste r mode only ? o ne channel fo r th e receiver , o n e channel fo r the transmitter ? nex t buff er support note: 1 . see tab le 24-1 below fo r details on compatibi lity with i2c sta ndard. 24.2 overvi ew th e atme l two-wire interf ace (twi ) interconne cts componen ts on a unique two-wire bus, made up of o n e clock lin e a nd on e d ata line with spee ds of up to 40 0 kb its per seco nd, based on a byte-oriented transfe r forma t. it can b e us ed wit h an y atmel tw o-wire inte rface bus serial eeprom and i2c com p atible device such as real time cloc k (rtc), dot matrix/g raphic lc d controlle rs and te mpe ratu r e se nsor , to nam e bu t a fe w. th e twi i s pro gra mm a ble as a master or a sla v e with se quential or single-byte access . mu ltiple master capability is supported. arbitra- tio n of t he bus is perfo rmed intern ally and puts the twi in slav e mode au tomatical ly if th e bus arbitrat ion is lost. a co nfigurable ba ud rate generato r permits the output data rate t o be adapted to a wi de ran ge of core clock frequencies. below, tabl e 24-1 lists the compatibility le ve l of the atme l two-wire interface in mast er mode and a full i 2 c compatible device. note: 1 . start + b000000001 + ac k + sr tabl e 24-1. atmel twi compatibility with i 2 c s tandard i2c s tan da rd atmel t wi standa rd mo de spee d (1 00 khz) supported fast mode spee d ( 40 0 khz) s up ported 7 or 10 bits sl ave ad dr essing suppo rted star t byte (1) not suppo rted repeated star t (sr) condition supported ac k an d na ck management supported slop e control an d i nput filterin g (fas t mode) no t supported clock stretching supported 32058k avr32-01/12 221 at32uc3a 24.3 list of abbreviations 24.4 block diagram figur e 24-1. block diagram tabl e 24-2. abbreviations abbreviation description twi two -wire interface a acknowledge na non a cknowledge p stop s start sr repe ated start sadr slav e add ress adr any address e xcept sadr r read w write peripheral bus bridge pm mck two-wire interface pio intc twi interrupt twc k twd 32058k avr32-01/12 222 at32uc3a 24.5 a pplication bloc k diagram figur e 24-2. applic ation block diagram 24.6 i /o lines description 24.7 p roduct dependencies 24.7.1 i/ o li nes b oth twd a nd twck ar e bidi rect iona l line s, c o nne cted to a p ositive supply voltag e vi a a current sourc e or pu ll- up r es is t or ( see f i gure 24-2 on page 22 2) . w hen t he bus is free , bo t h l ines a r e high. the ou t put st ages of devices connec t ed to the bus must have an open-dr ai n or open-col- lecto r t o per form th e wir ed-a nd fun ction. twd an d twck pi ns ma y be multiplexed with gpio lines. to enable t he tw i, th e programmer must perfor m th e following steps: ? program th e gpio controlle r to: ? dedicate tw d and twck as pe riphera l lines. ? define twd an d tw ck as open-drain. 24.7.2 power management the twi cloc k is generated by t h e powe r manag er (pm). befo re using the twi, t he programmer must ensure that t he twi cloc k is enab led in the pm. in th e twi description, master clock ( mck) is th e clock of t he peripher al bus to which t he twi is connected. tabl e 24-3. i/o line s descripti on pin name pin description type twd two -wire seri al data input/output twck two-wire seri al clock input/output host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp 32058k avr32-01/12 223 at32uc3a 24.7 .3 interrupt t he tw i in terfac e has an in t err upt li n e c onnec t ed t o t he int errupt c ont r oll er (intc ). i n or de r t o hand le interrupts, the in tc must be programmed befor e configuring t he twi. 24.8 functional description 24.8.1 transfer format th e dat a pu t on t he twd lin e mu st be 8 bi ts long. da ta is tr ans ferr ed msb fi rst; each byte must be f ollowed by an acknowledgement. the number of by tes pe r transf e r is unlimite d (se e figure 24-4). each t ransfe r begi ns wit h a start co ndition and terminat es with a stop condition (see figure 24-3). ? a high-to-lo w tr ansition on the tw d line while tw ck is high defines the s tar t condition. ? a lo w-to-high tr ansition on the tw d line while tw ck is high defines a s t op condition. figur e 24-3. star t and stop conditions figur e 24-4. transfer format 24.9 m odes of operation th e twi ha s six mod e s of operations: ? ma ste r tran smitt er mode ? master receiv er mode ? multi-maste r transmitte r mode ? multi-maste r receive r mode ? slav e transmitt er m ode ? slave receiv er mode th ese mode s are describ ed in the follo wing chapters. twd twck start stop twd twck start address r/w ack data ack data ack stop 32058k avr32-01/12 224 at32uc3a 24.10 master mode 24.10. 1 de f ini ti on th e master is t h e de vice which starts a transfer, generate s a clock and st ops it. 24.10.2 applicati on bloc k diagram figur e 24-5. master mode typical ap plic ation block diagram 24.10.3 programmi ng mast er mode th e followin g registers have t o be programme d befor e enterin g master mode: 1. d a dr (+ i a drs z + iad r i f a 1 0 bi t de vic e is a dd ressed): th e devic e ad d r ess is used to access sl av e de vices in read or wr ite mod e. 2. ckdiv + ch div + cldiv: clock waveform. 3. svdis : disable th e sla v e mode. 4. msen: en able th e maste r mod e. 24.10.4 master transmitte r mode after t he master initiates a star t condition when writing into the transmit holding regi st er, thr, it send s a 7-bi t slave add ress , co nfig ure d in th e master mod e re gister (dadr in mmr ) , t o noti fy t he sl av e d ev ic e. t h e bi t f oll owing t he s la v e add r e s s indicat es th e transfe r direction, 0 in this case (m r ead = 0 in mm r ). the tw i transfer s require th e slave to acknowled ge eac h received byte. during the acknowl- edge clock pulse (9th pulse), th e maste r rele ases th e data lin e (high) , enabling t he slave to pull it down in order to generate t he acknowledge. t he mast er polls the data line during t his clock pu lse an d sets th e nack in t he status register if th e slave does not acknowledge the byte. as with the othe r stat us bits, an interrupt can be generated if enabled in t he interrupt enable register (ier). if the slav e acknowledges th e byte, th e da ta written in the thr, is t hen shifte d in th e inter- nal shif ter and transferred. whe n an acknowledge is de tected, t he txrdy bit is set until a new writ e in th e thr. when n o mor e dat a is writt en into t he thr, th e master generate s a stop condi- tion to end the transfer. th e en d o f t he complete transfer is marked by t h e txcomp bit set to one. see figur e 24-6, figure 24-7 , a nd figur e 24- 8 o n pag e 225. txrdy is used as t ransmit ready for the pdc transmit channel. host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp 32058k avr32-01/12 225 at32uc3a figur e 24-6. master writ e with o ne dat a byte figur e 24-7. ma ster write wi th mult ipl e dat a b yte figur e 24-8. master writ e with o ne byte internal address a nd multip le dat a bytes 24.10.5 mast er receiv er mode the read seque nce begins by settin g th e start bit. after t he start condition ha s been sen t, the master sends a 7- bit slav e addres s t o notify th e slave device . th e bi t following t he slave address indicate s th e transfe r direction, 1 in this ca se (mread = 1 in mm r). during the ack nowledge clo ck pulse (9th pulse) , the master releases the data lin e (high) , enabling the slav e t o pu ll it do wn in order to generate t he acknowledge. the master polls the data line during th is clock pu lse and sets th e nack bit in th e status register if th e slav e does not acknowledge t he byte. if an ack nowled ge is received , the master is the n read y t o receive data fr om th e slave. after data has been received , the mast er se nds an acknowledge condition t o notify th e slave that th e data ha s bee n received except for th e last data, after the st op condition. see figur e 24-9. wh e n the txcomp txrdy wr ite thr (data) stop sent automaticaly (ack receiv ed and txrdy = 1) twd a data a s dadr w p a data n a s dadr w data n+5 a p data n+x a txcomp txrdy wr ite thr (data n) wr ite thr (data n+1) wr ite thr (data n+x) last data sent stop sent automaticaly (ack receiv ed and txrdy = 1) twd a iadr(7:0) a data n a s dadr w data n+5 a p data n+x a txcomp txrdy twd wr ite thr (data n) wr ite thr (data n+1) wr ite thr (data n+x) last data sent stop sent automaticaly (ack receiv ed and txrdy = 1) 32058k avr32-01/12 226 at32uc3a rxrdy bi t is se t in the status register , a characte r ha s been rece ived in th e receive-holding reg- ister ( r hr). the rxrd y bit is reset wh en reading the rhr. when a single data byte read is pe rformed, with or without internal address (iadr) , the start an d stop bits m ust be set at th e same time . see figure 24-9 . when a m u ltip l e da t a byt e r ead is performed, with or without iadr, th e stop bit must be set after the next - to-last data received. see figur e 24-10. f or inte rnal a ddress u sag e see ?internal address ? on pag e 226. figur e 24-9. master read wit h on e data byte figur e 24-10. master read wit h multiple da ta bytes rxr dy is used as re ceiv e ready for t he pdc re ceive channel. 24.10.6 interna l address th e twi interface can perfo rm various transfer formats: transfers with 7-bit slave address device s an d 10-bit slave a ddres s devices. 24.10.6.1 7-bit slave addressing when add ressing 7-bi t slave de vices, th e inte rnal address by tes are used to p erform random address ( read or write ) acce sses to re ach one or mo re data bytes, wi t hin a me mory pag e loca- ti o n i n a seri a l mem ory, for examp le. whe n p erforming read operations wit h an i nte r n al ad dress , th e twi perfo rms a w rit e op e rati on t o s e t th e inter n al ad dres s in to th e s lav e d e v ice , an d t hen swit ch to maste r rece iver mode. note that th e second start conditio n (after sending the iadr) is sometimes called ?repeat ed st art? (sr) in i2c f ully-compatible devices. see f igur e 24- 12 . se e fig ur e 24-11 and figure 24.11 fo r master writ e operatio n with intern al address. th e thre e internal address byte s ar e configurable through t he master mod e register (mmr). a s dadr r data n p txcomp write start & stop bit rxrdy read rhr twd n a s dadr r data n a a data (n+1) a data (n+m) data (n+m)-1 p twd txcomp write start bit rxrdy write stop bit after next-to-last data read read rhr data n read rhr data (n+1) read rhr data (n+m)-1 read rhr data (n+m) 32058k avr32-01/12 227 at32uc3a if th e slave device suppor ts on ly a 7- bit address, i.e. no intern al address, iadrsz must be se t to 0. n th e figures below the followin g abbreviation s ar e used:i figur e 24-11. master writ e with one, two or thr ee bytes inter nal addres s an d one data byte figur e 24-12. maste r rea d wit h one , tw o o r th re e byte s inte rn al addr ess a nd o ne data by te ?s start ?sr repeate d start ?p stop ?w write ?r r ead ?a acknowledge ?n not a cknowledge ? dadr de vice address ?iadr interna l address s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p sr dadr r a sr dadr r a data n p sr dadr r a data n p twd twd twd three bytes internal address two bytes internal address one byte internal address 32058k avr32-01/12 228 at32uc3a 24.10.6.2 10-bi t slav e addressing for a slave a ddres s higher tha n 7 bits , th e user must configure the addr ess size (iadrsz ) and se t the othe r s lave ad dre ss bi ts i n th e inte rnal addre ss reg iste r (iadr) . th e tw o re mainin g inter- na l addr ess bytes, iadr[15:8] and iadr[23:16] can be us ed th e same as in 7-bit slave addressing. example: addres s a 10-bit device: (10-bit device addr ess is b 1 b 2 b 3 b 4 b 5 b6 b 7 b8 b9 b10) 1. progra m iadr sz = 1, 2. progra m da dr wit h 1 1 1 1 0 b1 b2 (b1 is t he msb of t h e 10- bit address, b 2, et c.) 3. program ia dr wit h b3 b 4 b5 b 6 b7 b 8 b9 b1 0 (b10 is th e lsb of th e 10-bit address) figur e 24.11 below sh ow s a byt e write t o an atmel at24lc512 eeprom. this d emonstrates the us e of internal addre sses to access t he device. 24.11 intern al addr ess usage using the pe ripheral dma contro ller (pdc) th e use of th e pdc significant ly redu ces th e cpu load. t o a ssur e correct i mple me ntati o n, respect th e fo llowin g p rogra mmi ng seq uen ces: 24.11.1 data transmit with th e pdc 1. initializ e the tr ansmit pd c (memory pointers, size , etc.). 2. c on figure t he m aste r mo d e (dadr, ckdiv, e tc. ). 3. start the transfer by s ettin g th e pdc txten bit. 4. wait for t he pdc en d tx flag. 5. dis able the pdc by setting the pdc tx dis bit. 24.11. 2 dat a receiv e with th e pdc 1. initiali z e the receive p dc (memor y pointer s, siz e - 1 , etc.). 2. c onfigure t he m aste r mo de (dadr, ckdiv, e tc. ). 3. start the transfer by s ettin g th e pdc rxten bit. 4. wait for t he pdc en d rx flag. 5. dis able the pdc by setting the pdc rxdis bit. s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p 32058k avr32-01/12 229 at32uc3a 24.11.3 read-wri te flowcharts the followin g flowchar ts shown in figure 24-13 to figure 24-1 8 on page 234 give exam ples for rea d and write operatio ns. a pollin g or interrup t method ca n be used to check th e status bits. th e in terr up t met ho d re quir es th a t the i nter rup t ena b le r e gister (i er) be co nfigu re d fi rst. figur e 24-13. twi wri t e operation with single data byte without internal address. set twi clo ck (cldiv, chdiv , ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished yes yes begin no no 32058k avr32-01/12 230 at32uc3a figur e 24-14. twi wri t e operation with single data byt e and internal address begin set twi clo ck (cldiv, chdiv , ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - internal address size (iadrsz) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished set the internal address twi_iadr = address yes yes no no 32058k avr32-01/12 231 at32uc3a figur e 24-15. twi wri t e operat ion wit h multip le data bytes wit h or without interna l address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send read status register txrdy = 1? data to send? read status register txcomp = 1? end begin set the internal address twi_iadr = address yes twi_thr = data to send yes yes yes no no no set twi clo ck (cldiv, chdiv , ckdiv) in twi_cwgr (needed only once) 32058k avr32-01/12 232 at32uc3a figur e 24-16. twi read operat ion wit h single data byte without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - transfer direction bit read ==> bit mread = 1 start the transfer twi_cr = start | stop read status register rxrdy = 1? read status register txcomp = 1? end begin yes yes set twi clo ck (cldiv, chdiv , ckdiv) in twi_cwgr (needed only once) read receive holding register no no 32058k avr32-01/12 233 at32uc3a figur e 24-17. tw i r ead o perati on with si ng l e dat a b yt e and in ternal a ddress set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (iadrsz) - transfer direction bit read ==> bit mread = 1 read status register txcomp = 1? end begin yes set twi clo ck (cldiv, chdiv , ckdiv) in twi_cwgr (needed only once) yes set the internal address twi_iadr = address start the transfer twi_cr = start | stop read status register rxrdy = 1? read receive holding register no no 32058k avr32-01/12 234 at32uc3a figur e 24-18. twi read operat ion wit h multiple data byte s wit h or withou t internal address internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 1? last data to read but one? read status register txcomp = 1? end set the internal address twi_iadr = address yes yes yes no yes read receive holding register (twi_rhr) no set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit read ==> bit mread = 1 begin set twi clo ck (cldiv, chdiv , ckdiv) in twi_cwgr (needed only once) no read status register rxrdy = 1? yes read receive holding register (twi_rhr) no 32058k avr32-01/12 235 at32uc3a 24.12 multi-master mode 24.12. 1 de f ini ti on mor e than o ne master ma y handl e the bus at t he s a me time without data corruption by using arbitration. arbitratio n starts as so on as two or more master s place information on the bu s a t the same time, an d stop s (arbitration is l ost) for the master that intends to send a logical one while the other master sends a logical zero. as s o on as arbitratio n is lost by a m aster, it s top s sendin g data an d listens to the bus in order to det e ct a s top . when the st op is detected, th e ma ste r who h a s los t ar bitra t ion m a y pu t its da t a on the bus by respectin g arbitration. arbitration i s illustrated in figur e 24-2 0 o n pa ge 236. 24.12.2 different multi-mast er modes two m ulti-master modes may be distinguished: 1. twi is co nsidered as a maste r only and will n eve r be addressed. 2. twi may be either a m aster or a slav e an d ma y be addressed. note: arbitration is s upported i n bo th multi-master modes. 24.12.2 .1 tw i a s ma ste r on ly in this mode, tw i is conside r ed as a master o nly (msen is always at one) and mus t be drive n like a m aster with t he arblst (arbitration lost) flag i n addition. if arbitrat ion is lost (arblst = 1 ), t he programme r must reinitiate th e data transfer. if th e user star ts a transfe r (ex.: dadr + start + w + w rite in thr ) and if th e bu s is bu sy, the twi aut omatically waits f or a stop conditi on on the bus t o initiate the transfer (see fig ure 24- 1 9 o n page 236). no te: the st a te o f t he b u s (busy or free) is not ind icate d in the user interface. 24.12.2 .2 tw i a s ma ster or sla ve th e au tomatic reve rsal fr om ma ster to slav e is no t su ppo rt ed in case of a los t ar bitratio n. th en, i n t he case whe r e twi may b e eith er a master or a slav e , the programmer mu st man age t he pse ud o multi-ma ste r mo de d escr ib e d in th e ste ps below. 1. progra m t w i in sl av e m od e (sad r + ms dis + sve n) an d perform slav e acce ss (if tw i is a ddressed ). 2. if twi h as to be se t in maste r mode, wa it un til txcomp flag is at 1. 3. progra m master mode (dadr + svdi s + mse n) and star t the transfer (e x: star t + wr ite in thr). 4. as s oon as the maste r mode is enabled, twi scans the bu s in order to detect if it is busy or fre e. wh en t he bu s is co nside r ed as f ree , twi initi ates the tra nsf er. 5. as s oo n as the transfe r is initiate d an d un til a st op conditio n is sen t, th e arbitration beco mes relevant and the user must monitor th e arblst flag. 6. if th e arbitratio n is lost (arblst is set to 1), the user must program t he twi in slave mode in th e case wher e th e master that won th e arbitration wanted to access the twi. 32058k avr32-01/12 236 at32uc3a 7. if twi has to be se t in slav e mode, wait unt il txcomp flag is at 1 a nd th en program the slave mode. note: i n th e case w here the arbitrati on is lost a nd tw i is ad dressed, twi will not a cknowledge even if it is progr amm e d in sl ave mod e as s oo n as ar bls t is set to 1. the n , the master must re peat sadr. figur e 24-19. programmer sends da ta wh ile the bus is busy figur e 24-20. arbitratio n cases the flowchart sh own in figure 24-21 on page 237 gives an examp l e of re a d a n d writ e oper ati on s in multi- m ast er mode. twck twd data sent by a master stop sent by the master start sent b y the twi data sent b y the twi bus is busy bus is free a transfer is programmed (d adr + w + star t + wr ite thr) transfer is initiated twi data transfer transfer is kept bus is considered as free twck bus is busy bus is free a transfer is programmed (d adr + w + star t + wr ite thr) transfer is initiated twi data transfer transfer is kept bus is considered as free data from a master data from twi s 0 s 0 0 1 1 1 arblst s 0 s 0 0 1 1 1 twd s 0 0 1 1 1 1 1 arbitration is lost twi stops sending data p s 0 1 p 0 1 1 1 1 data from the master data from the twi arbitration is lost the master stops sending data transfer is stopped transfer is programmed again (d adr + w + star t + wr ite thr) twck twd 32058k avr32-01/12 237 at32uc3a figur e 24-21. multi-master flowchart programm the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? wr ite in twi_thr need to perform a master access ? program the master mode d adr + svdis + msen + clk + r / w read status register arblst = 1 ? mread = 1 ? txrdy= 0 ? wr ite in twi_thr data to send ? rxrdy= 0 ? read twi_rhr data to read? stop transfer read status register txcomp = 0 ? general call tre atment yes yes yes yes yes yes yes yes yes yes yes yes yes yes start 32058k avr32-01/12 238 at32uc3a 24.13 sl a ve mode 24.13. 1 de f ini ti on the slave mode is defined as a mode where the device receives the clock and the addre ss from anothe r dev i ce ca lle d th e master. in t his mode , t he device never initiates and never completes t he transmission (start, repeated_start a nd stop condit ions ar e always provide d by t he master). 24.13.2 applicati on bloc k diagram figur e 24-22. slave m o de typica l application bloc k diagram 24.13.3 programmi ng slav e mo de the follo wi ng fi elds mu st b e pro gramme d b efor e entering s lav e mod e: 1. sa dr (smr ): t h e slav e d evic e ad dre ss is use d i n o rder t o b e accesse d by m ast er devices in read or w r ite mode. 2. msdis (c r): disab le the master mode. 3. sven (c r): enab le the slav e mode. as th e de vice receives the clock, valu es writte n in cwgr ar e not taken into account. 24.13.4 receivi ng data after a start or repe ated start conditio n is detected and i f t he addres s sent by th e master matches with the slave addr e ss programmed in the sad r (slave address) fiel d, svacc (slave acces s) flag is se t an d svread (slave read) indicate s the directio n of the transfer. svacc r ema ins hig h un til a stop co nd ition o r a rep eated start is de t ected. when such a condit ion is detected, eosacc (end of slave access) flag is s et. 24.13.4.1 rea d sequence in the case of a r e ad sequence (s vread is high), twi t ransfer s dat a written in the thr (tw i transmit ho lding register) until a stop condition or a repeated_ star t + an addre ss d iffer- ent fro m sadr is detected. note that a t t he en d of th e re ad sequence txco mp (transmission complete) flag is set and svac c reset. host with twi interface twd twck lcd controller slave 1 slave 2 slave 3 r r vdd host with twi interface host with twi interface master 32058k avr32-01/12 239 at32uc3a as so o n as dat a is writt en in the thr, txrdy (tr ansmit holdin g regist er ready) fl ag is reset, an d it is s e t wh en th e shift register is e mpt y and the sent data acknowledged or not. i f the data is not acknowledged, th e nack fl ag is set. note that a stop or a repeated star t always follows a nack. see figur e 24-2 3 on pag e 240. 24.13.4.2 writ e sequence in th e ca se of a write sequenc e ( svread is low), the rxrdy (receive holding registe r r ead y ) fl ag i s s et as soon a s a cha racte r h as been re ceived in the rhr (twi receive holdin g register). rx rdy is rese t whe n rea din g th e rhr. twi continues receiving data until a stop c o ndition or a repeated _start + an address dif- ferent from sadr is detected . no te th at at the en d o f the write seque nce txcomp flag is set and sva c c reset. see figur e 24-2 4 on pag e 241. 24.13.4.3 clock synchronization sequence in the ca se where thr or rhr is not written/read in time, twi p e rforms a clock synchronization. clock s tretching informatio n is given by th e sclws (clock wait state) bit. see figur e 24-2 6 on pag e 242 and figur e 24-2 7 o n pa ge 243. 24.13.4.4 gener al call in th e case wher e a genera l cal l is p erfo r med, gac c (general call access ) flag is set. afte r gacc is se t, it is u p to th e p rogram mer to interp ret the meaning of the general cal l and t o de code th e ne w a ddress progra mmin g s equence . see figur e 24-2 5 on pag e 241. 24.13.4 .5 p dc as i t is imp ossible to kn ow th e exact number of data to receive/send, the use o f pdc is n o t rec- ommended in sl ave mode. 32058k avr32-01/12 240 at32uc3a as i t is imp ossible to kn ow th e exact number of data to receive/send, the use o f pdc is n o t rec- ommended in sl ave mode. 24.13.5 data transfer 24.13.5.1 rea d operation th e re ad mo de is define d as a data requirement from th e master. after a start or a repeat ed start condition is detected, the decoding of the addres s starts. if t he slave address (sadr) is deco ded, sv acc is se t and s vread indicates the direc- tion of the transfer. u n til a s t op o r repeate d start conditio n is de tect ed, twi continu es sending dat a loaded in the thr register. if a stop conditi on or a r epeated start + an addres s different fr om sadr is detected, svac c is reset. figur e 24-2 3 o n pa ge 24 0 descr ib es t h e writ e ope rati on. figur e 24-23. re ad access order ed by a master notes : 1. w hen sv a cc is lo w, the st at e of svread be comes irrel ev ant. 2. txrd y is reset whe n d at a h a s bee n tr an smitte d from thr to t h e sh ift regi ster an d se t when th is data has bee n acknowledge d or n on acknowledged. 24.13.5.2 writ e operation the writ e mode is d efined as a d ata transmission from th e master. after a start or a repeate d star t, the decodi ng of the address starts . if the slave address is d ecoded , svacc is set a nd svread indicates t he directio n o f the transfer (svread is l o w in this case). unti l a stop or repeated start condition is det ected, twi st ores the re ceived data in the rh r register. if a stop conditi on or a r epeated start + an addres s different fr om sadr is detected, svac c is reset. figur e 24-2 4 o n pa ge 24 1 de scri bes th e writ e ope rat ion. wr ite thr read rhr svread has to be taken into account only while svacc is active twd txrdy nack svacc svread eosvacc sadr s adr r na r a data a a data na s/sr dat a na p/s/sr sadr matches, twi answers with an ack sadr does not match, twi answers with a nack ack/nack from the master 32058k avr32-01/12 241 at32uc3a figur e 24-24. writ e acce ss ordered by a m aster notes : 1. w hen sv a cc is lo w, the st at e of svread be comes irrel ev ant. 2. rxrd y is set wh en data has be en transmitted from the shif t re gister to the rh r an d reset when th is da ta is re a d. 24.13.5.3 gener al call th e gener al call is performe d in order to chang e th e addres s of th e slave. i f a general call is d ete cted, gacc is se t. after the detect ion of general call, it is up to the programmer to decode t he command s which com e afterwards. i n case of a wri t e command , th e programmer has to decode th e programmin g seque nce and program a ne w sa dr i f th e programmin g sequence ma tches. figur e 24-2 5 o n pa ge 24 1 descri bes th e gener al call access. figur e 24-25. master per fo rms a g ene r al call note: 1. t his method allo ws th e user to crea te an ow n programming sequence by choosin g th e pro- gramming by tes an d the number of them. the pro grammi ng sequ ence ha s to be provid ed to the master. rxrdy read rhr svread has to be taken into account only while svacc is active twd svacc svread eosvacc sadr does not match, twi answers with a nack sadr s adr w na w a dat a a a data na s/sr dat a na p/s/sr sadr matches, twi answers with an ack 0000000 + w gggeeennneeerrraaalll cccaaallllll p s a reset or write dadd a new sadr data1 a data2 a a new sadr programming sequence txd gcacc svacc reset command = 00000110x write command = 00000100x reset after read 32058k avr32-01/12 242 at32uc3a 24.13.6 clock synchronization in both r e ad a nd write m odes, it m ay ha p pen th at thr/rhr buffer is not filled / e mptie d b efo re the e mission / rec ep tio n o f a n e w c h a ra cter . i n th is case , to avoi d sending/receiving undesired dat a, a cl o ck s tretchi n g mechanis m is im ple mente d. 24.13.6.1 clock sync hronization in read mode the clock is tied low if the shi ft re gist er i s e m pty and if a stop or repeated star t condition was no t detected. it is ti ed low un t il th e shift register is lo aded. figur e 24-2 6 o n pa ge 24 2 descri bes th e clock synchronization in r e ad mode. figur e 24-26. clock synch ron izatio n in read mode notes: 1. txrdy is reset whe n da ta has been writte n in the th to the sh if t register a nd set when this data ha s bee n acknowledged or no n acknowledged. 2. at th e e nd of th e read sequence, txcomp is s e t after a st op or afte r a repeated_star t + a n a ddress differen t from sadr. 3. sclw s is automatica lly set wh en th e cloc k synchronizati on mechan ism is started. data1 the clock is stretched after the a ck, the state of twd is undefined during clock stretching sclws svacc svread txrdy twck twi_thr txcomp the data is memoriz ed in twi_thr until a new value is written twi_thr is transmitted to the shift register ack or nack from the master dddaaatttaaa000 data2 1 2 1 clock is tied low b y the twi as long as thr is empty s sadr s r data0 a a data1 a data2 na s xxxxxxx 2 wr ite thr as soon as a start is detected 32058k avr32-01/12 243 at32uc3a 24.13.6.2 clock synchronization in writ e mode th e cl o ck i s t ied low i f th e sh i ft r e giste r an d the rhr is full . if a stop or repeated_start condit ion was not detected, it i s ti ed lo w unti l rhr is re ad. figur e 24-2 7 o n pa ge 24 3 descri bes th e clock synchronization in r e ad mode. figur e 24-27. clock synch ron izatio n in writ e mo de notes: 1. at th e e nd of th e read sequence, txcomp is s e t after a st op or afte r a repeated_star t + a n a ddress differen t from sadr. 2 . sc lw s is aut omatically se t w h e n the c loc k synchronization mechanism is star ted an d automaticall y rese t wh en the mecha- nism is fi nished. rd data0 rd data1 rd data2 svacc svread rxrdy sclws txcomp data1 data2 scl is stretched on the last bit of data1 as soon as a start is detected twck twd twi_rhr clock is tied low b y the twi as long as rhr is full data0 is not read in the rhr adr s sadr w a data0 a a data2 data1 s na 32058k avr32-01/12 244 at32uc3a 24.13.7 reversal aft er a repeat ed start 24.13.7.1 rever sal of read t o write th e master initiates t he communication by a r ead command an d finish es it by a write command. figur e 24-2 8 o n pa ge 24 4 descri bes th e repeat ed start + reversal fr om rea d to writ e mode. figur e 24-28. repeated start + r eversal from read t o writ e mode 1. txcomp is onl y set at the en d o f the transmissio n becaus e after the repeated start, sadr is detected again. 24.13.7.2 rever sal of write t o read the master initia tes the communicatio n by a write co mmand a nd finishes it by a r ead com- mand.figure 24-2 9 on page 244 describes th e repeat ed star t + reversal fr om write t o read mode. figur e 24-29. re pea ted sta rt + r eversa l fro m wri t e t o re ad mo de notes: 1. in this c ase , if thr ha s no t be en wr itten at th e e nd of th e read command , th e clock is automatically stretched before the ack. 2. txcomp is only set at the en d o f the transmissi on because af ter th e repeate d star t, sadr is detected again. s sadr r a data0 a data1 sadr sr na w a data2 a data3 a p cleared after read data0 data1 data 2 data 3 svacc svread twd twi_thr twi_rhr eosacc txrdy rxrdy txcomp as soon as a start is detected s sadr w a data0 a data1 sadr sr a r a data2 a data3 na p cleared after read data0 data2 data3 data 1 txcomp txrdy rxrdy as soon as a start is detected read twi_rhr svacc svread twd twi_rhr twi_thr eosacc 32058k avr32-01/12 245 at32uc3a 24.13.8 rea d writ e flowcharts the flowchart sh own in figure 24-30 on page 245 gives an exampl e of re a d a n d writ e oper ati ons in s lave mode. a polling or interr upt method can be used to check the status bits. the interrupt method requires that t he interrupt enable register (i er) be configured first. figur e 24-30. read write flowchar t in slave mode set the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? w rite in twi_thr end general call treatment 32058k avr32-01/12 246 at32uc3a 24.14 t wo-wi re interface (twi) user i nterface 24.14.1 register mapping note: 1. val ues in the version register vary wit h the versio n of the ip block implementation. 24.14.2 twi control register name: cr access: write-only reset value: 0x00000000 ? start: send a star t condition 0 = n o e ffect. 1 = a fram e beginning wit h a start bit is transmitte d according to the features defined in th e mode register. tabl e 24-4. twi us er interface offset register name access reset 0x00 contro l register cr write-only n / a 0x04 master m o de register mmr read-write 0x00000000 0x08 slav e mo de register smr read-write 0x00000000 0x0c i nt ern a l ad dres s r e g i st er i adr r ea d-w r ite 0x0000 0000 0x10 clock waveform generator register cwgr read-write 0x00000000 0x20 status register sr read-only 0x0000f009 0x24 interrup t enab le register ier write-only n / a 0x28 interrupt disab le register idr write-only n / a 0x2c interrup t mask register imr read-only 0x00000000 0 x30 r eceiv e hol d i n g r e g i s ter rhr r e ad -only 0x 000 0 00 00 0x34 transmit holding register thr write-only 0x00000000 0x38 - 0xf8 reserved ? ? ? 0xfc versio n register twi_ver read-only 0x00000000 (1) 0x38 - 0xfc reserved ? ? ? 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 swrst ? svdis sven msdis msen stop start 32058k avr32-01/12 247 at32uc3a th is acti on is necessar y when the twi periphera l wants to re ad data from a slave. when configured in maste r mode with a write operation, a fram e is sent as soon as the user writes a cha racter in th e transmit holding register (thr). ? stop: se nd a st op condition 0 = n o e ffect. 1 = s t op conditio n is sent just afte r completing the current byte transmission i n master rea d mode. ? m sen: twi maste r m od e e n abled 0 = n o e ffect. 1 = i f msdi s = 0, t he master mod e is enabled. note : switching from sl ave to mast er mode is on ly permitted w hen txco mp = 1. ? msdis : twi mast er mod e disabled 0 = n o e ffect. 1 = th e master mode is disabled, all pe nding data is transmitted. th e shifte r and holdin g characters (if it contai ns data) are transmitt ed in case of write o peration . in read operatio n, the characte r being transferre d must be completely received before disabling. ? sven : twi sla ve mode enabled 0 = n o e ffect. 1 = i f svdi s = 0, th e slav e mode is e nabled. note: switching from m aster to sl ave mode is on ly permitte d w hen txco mp = 1. ? svdis: t w i slav e mode disabled 0 = n o e ffect. 1 = t h e slave mode is disabled. the shifter an d holdin g character s (i f it conta in s da ta ) are transmitte d in ca se of re ad op e r- ation . i n writ e op eration , th e cha r act er bein g t ra nsferre d m u st b e complete ly r eceive d b efor e disablin g. ? swrst : software reset 0 = n o e ffect. 1 = eq uivalent to a sys tem reset. - i n sing le data byt e mas ter r ead , th e start and st op mu st bot h be se t. - i n m ultipl e data bytes master read, the stop must be se t after the la st data received bu t one. - in master re ad mode, if a nack bi t is received , the stop is automati cally performed. - in multip le data writ e operation, when both th r an d shift regist er ar e empty, a stop condit ion is automatica lly sent. 32058k avr32-01/12 248 at32uc3a 24.14.3 twi master mo de register name: mmr access: read-write reset value: 0x00000000 ? iad rsz: internal de vice ad dress size ? mread : master read direction 0 = master write dire ction. 1 = mas ter read direction. ? d adr: de vice ad dress th e de vice addr ess is used to access slave d evice s in read or wri t e mode . th ose bi ts are only use d in m aste r mo de. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? dadr 15 14 13 12 11 10 9 8 ? ? ? mread ? ? iadrsz 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? iadrsz[9:8] description 0 0 no inte rn al de vice address 0 1 one-by te interna l devic e address 1 0 two-byte intern al de vice address 1 1 three-by te internal devi ce address 32058k avr32-01/12 249 at32uc3a 24.14.4 twi slav e mod e r egister name: smr access: read-write reset value: 0x00000000 ? sad r: slav e address th e slav e device addr ess is us ed in slave mod e in order to be accessed b y maste r device s i n read or write mo de. sadr m us t be progra mm ed befor e ena bling the s lav e mod e o r a fter a g e nera l call . wri te s at o the r ti mes ha ve n o effec t. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? sadr 15 14 13 12 11 10 9 8 ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? 32058k avr32-01/12 250 at32uc3a 24.14.5 t wi interna l addres s register name: iadr access: read-write reset value: 0x00000000 ? i a d r: int e rnal a d dress 0, 1, 2 o r 3 byte s dependin g on iadrsz. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 7 6 5 4 3 2 1 0 iadr 32058k avr32-01/12 251 at32uc3a 24.14.6 twi clock wavef orm generator register name: cwgr access: read-write reset value: 0x00000000 cwgr is o n ly used in mas ter mode. ? cldiv: cloc k lo w divider th e scl low peri od is define d as follows: ? chdiv : cloc k high divider th e sc l hig h peri od is defin e d as fo llows: ? ckdiv: cloc k divider th e ckdi v is used to increas e both sc l hig h a nd lo w periods. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ckdiv 15 14 13 12 11 10 9 8 chdiv 7 6 5 4 3 2 1 0 cldiv t low cldiv ( 2 ckdiv ( ) 4 ) + t mck = t high chdiv ( 2 ckdiv ( ) 4 ) + t mck = 32058k avr32-01/12 252 at32uc3a 24.14.7 tw i stat us regi st er name: sr access: read-only reset value: 0x0000f0 09 ? txcomp: transmission completed (automaticall y set / reset) txco mp us ed in maste r m ode: 0 = d urin g th e lengt h of th e current frame. 1 = when bot h holding and shifte r register s ar e emp ty and st op conditio n ha s been sent. txcomp behavio r in master mod e ca n be see n in figur e 24- 8 o n pag e 225 an d in figur e 24-1 0 on pag e 226. txcomp us ed in sla ve mode: 0 = as soo n a s a star t is detected. 1 = afte r a stop or a r epeated star t + an addre ss differen t from sadr is detected. txcomp behavior in slave mode can be s e en in figure 24 - 26 on page 242, figure 24 - 27 on page 243, figure 24 - 28 on pag e 244 and figure 24-2 9 o n pa ge 244. ? rxrdy : receiv e holding register read y (automatically set / reset) 0 = n o chara cte r ha s bee n rece ive d s i nce th e last rhr r ea d operation. 1 = a byt e has been received in t h e rhr since th e last read. rxrdy b ehavior in mas te r mode can be see n in figur e 24-1 0 o n pag e 226. rxrdy behavio r in slave mo de can be see n in figure 24-24 on page 24 1, figure 24-27 on page 24 3, figure 24-28 o n pag e 244 and figure 24-2 9 o n pa ge 244. ? txrdy: transm it holding register read y (automatically set / reset) txrdy u s ed in master mode: 0 = th e transmit holdin g register has no t been transferred into shift register. se t to 0 wh en writ ing into thr r egister. 1 = as s o on as a data byte is transferred from thr to internal shifte r or if a nack error is detected, txrdy is set at th e s ame time a s t x comp and n ack. txrd y is also se t when msen is s e t (ena ble twi). tx rdy behavior i n maste r mode can b e se en in figur e 24- 8 on pag e 225. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc sclws arblst nack 7 6 5 4 3 2 1 0 ? o vre g acc sv acc svrea d txrd y rxrdy tx c omp 32058k avr32-01/12 253 at32uc3a t xr dy used in s lav e m o de: 0 = as soon a s data i s written in the t h r, until this data has b een transmitte d an d acknowledged (ack or nack). 1 = i t indicates that t he thr is empt y an d that dat a has been transmitted a nd acknowledged. if txrdy is hig h a nd if a nack h a s bee n detected , th e tra nsmission will be stopp ed. thus wh en trdy = nack = 1, the programmer must not fill thr to a v oid losing it. t xrd y b ehavior i n slave m od e c a n be see n i n figu re 24 -23 on page 240, figure 24-2 6 on pa g e 242, figu re 24 -28 on pag e 244 and figure 24-2 9 o n pa ge 244. ? svre ad : sl a ve read (a u to mat icall y se t / reset) th is bi t is only us ed in slave mode . when svacc is low (n o slav e acce ss ha s bee n detected) svread is ir relevant. 0 = i ndicate s that a write acce ss is performe d by a master. 1 = i ndicate s that a read access is pe rformed by a m aster. svread b ehavio r ca n be seen in figure 24-23 on pag e 240, figur e 24-2 4 on page 241, figur e 24-2 8 o n page 244 and figur e 24-2 9 o n pa ge 244. ? svacc: sla ve access (automaticall y set / reset) th is bi t is only us ed in slave mode. 0 = twi is not addressed. sva c c is automatically cleared af ter a na c k or a stop condition is detected. 1 = in di cate s th a t th e ad dres s d ec o di ng seq uen ce ha s m atche d ( a maste r ha s s en t sa dr). sva c c rem ai n s high un t il a nack o r a stop c onditio n is detected. sva c c behavior can be seen in figur e 24-2 3 on page 240, figure 24-24 o n page 241, figure 24-28 o n page 244 and fig- ur e 24-2 9 o n pag e 244. ? gacc: genera l call acces s (cle ar on read) th is bi t is only us ed in slave mode. 0 = n o genera l call ha s bee n detected. 1 = a genera l call h a s been det ect ed . a f ter th e de te ction of ge nera l ca ll, th e progra mm e r de coded th e command s tha t f ol- low a n d th e programming sequence. gacc be havior can be see n in figur e 24- 25 o n pag e 241. ? o vre: overrun erro r (c lear on read) this bi t is only used in mast er mode. 0 = r hr has not been loaded wh ile rx rdy was set 1 = r hr has been loaded while r xrdy was set. reset b y read in sr when txcomp is set. ? na ck: not acknowledg ed (c lear on read) nac k used in master mode : 0 = e a ch data byt e has been corr ectly receive d by th e far-en d sid e twi slave co mponent. 1 = a data byte has no t be en acknowledge d by th e slave component. set at the same tim e a s txcomp. 32058k avr32-01/12 254 at32uc3a na ck use d in s lav e rea d m ode: 0 = e a ch data byt e has been corr ectly receive d by th e master. 1 = in re ad mode, a data byte ha s no t be en acknowledged by t he master . when nack is se t t h e programme r must no t fill thr even if tx r d y i s set, because i t means that the m a ster will stop the data tra n sfer or re initiate it. note that in slave writ e mo de all data ar e acknowledged by the twi. ? arblst: arbitrat ion los t (clear o n read) this bi t is only used in mast er mode. 0 = arbitra tio n wo n. 1 = a rbitrat ion lost. another maste r of t he twi bus has won the multi-master arbitration . txcomp is se t at th e same time. ? scl ws: clock wait stat e (automatically set / r eset) th is bi t is only us ed in slave mode. 0 = th e clock is n o t stretched. 1 = the clock is stretched. thr / r h r buffe r is not filled / emptied before the emissi on / reception of a new ch aracter. sclw s be havio r c a n b e see n in figu re 24-2 6 o n page 242 and figur e 24-27 on page 243. ? eosacc: end of slav e acces s (cle ar on read) th is bi t is only us ed in slave mode. 0 = a slave access is b e ing performing. 1 = th e slav e access is finished. en d of slave acces s is automatically se t as soo n as s vacc is reset. eosacc beha vior ca n be seen in figur e 24-2 8 on pag e 244 and figur e 24-2 9 o n pa ge 244 ? end rx: end of rx buffer this bi t is only used in mast er mode. 0 = th e receive counter register ha s not reach ed 0 since t he last writ e in rcr or rncr. 1 = th e receive counter register has reache d 0 since the last write in r cr or rncr. ? endtx : end of tx buffer this bi t is only used in mast er mode. 0 = th e t ra nsm it c ounte r r eg i ster ha s not reached 0 si nc e th e last writ e i n tcr or tncr . 1 = th e transm it counter register ha s reache d 0 since th e last write in tc r or tncr. ? rxbuff: rx buf fe r full this bi t is only used in mast er mode. 0 = rcr or rncr have a valu e other tha n 0. 1 = b ot h rcr and rncr h av e a va lue of 0. ? txbufe: tx buf fer empty this bi t is only used in mast er mode. 0 = tcr o r tncr have a valu e other tha n 0. 32058k avr32-01/12 255 at32uc3a 1 = b ot h tcr an d tncr hav e a va lue of 0. 24.14.8 t wi interrupt enable register name: ier access: write-only reset value: 0x00000000 ? t xcomp : tr ansmissi on comple te d in terrupt en able ? r xrdy : r eceiv e ho ld i ng registe r rea d y inter rup t enable ? t xrdy : transm it holding re giste r read y inte rrupt enab le ? svacc: sla ve access interrupt enable ? gacc: genera l call access interrupt enable ? o vre: overrun erro r interrupt enable ? nack: not acknowledge interrupt enable ? arblst: arbitrat ion los t interrupt enable ? s cl_ws: clock wait stat e interrupt enab le ? eosac c: end of slave access interrupt enable ? endr x : e n d o f r eceiv e b uffe r i nterr u p t e nable ? endtx : end o f t ran sm it b uffer i nte rrup t enable ? r xbuff: receive buff er full interrupt enable ? txbufe: transmi t buff er empt y interrupt enable 0 = n o e ffect. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 7 6 5 4 3 2 1 0 ? ovre gacc svacc ? txrdy rxrdy txcomp 32058k avr32-01/12 256 at32uc3a 1 = e nables the corresponding interrupt. 24.14.9 tw i interrupt disable register name: idr access: write-only reset value: 0x00000000 ? txc omp : t ransmiss i o n co mple te d interr upt disable ? rxrdy : r eceiv e h oldin g regist er ready interrupt disable ? t xr dy : tra nsm i t ho ldi ng regis ter r eady inte rrupt disable ? svacc: sla ve access interrupt disable ? gacc: general call access inte rrupt disable ? o vre: overrun erro r interrupt disable ? na ck: not acknowledg e interrupt disable ? arblst: arbitrat ion los t interrupt disable ? s cl_ws: clock wait stat e interrupt disable ? eosacc: end of slav e access interru pt disable ? endrx: en d of receiv e buffer interrupt disable ? endtx : end o f t ran sm it b uffer i nte rrup t di sable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmi t buff er empt y interrupt disable 0 = n o e ffect. 1 = disa bl es th e co rr espo ndi ng interru pt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 7 6 5 4 3 2 1 0 ? ovre gacc svacc ? txrdy rxrdy txcomp 32058k avr32-01/12 257 at32uc3a 24.14.10 tw i interrup t mask register name: imr access: read-only reset value: 0x00000000 ? txcomp: transmission complete d interrup t mask ? rxrdy : r eceiv e h oldin g regist er read y in ter rup t m ask ? txrdy: transmit holdi ng regist er ready interrup t mask ? svacc: sla ve access interrup t mask ? gacc: general call access interrupt mask ? o vre: overrun erro r interrupt mask ? na ck: not acknowledg e interrupt mask ? arblst: arbitrat ion los t interrupt mask ? scl _w s: cloc k wait state int err upt mask ? eosacc: end of slav e access interru pt mask ? end rx: end of receive buff er interrupt mask ? endtx : end o f t ran sm it b uffer i nte rrup t m a sk ? r xbuff: receive buff er full interrup t mask ? txbufe: transmi t buff er empt y interrupt mask 0 = th e correspondin g interrupt is disabled. 1 = th e corresponding interrup t is enabled. 24.14.11 tw i receiv e ho ldi ng reg ister name: rhr 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 7 6 5 4 3 2 1 0 ? ovre gacc svacc ? txrdy rxrdy txcomp 32058k avr32-01/12 258 at32uc3a access: read-only reset value: 0x00000000 ? rxd at a: m ast er or sl a v e rece iv e hold in g da ta 24.14.12 twi transmi t holdin g register name: thr access: read-write reset value: 0x00000000 ? txdata : master or slave transmit holdin g data 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 rxdata 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 txdata 32058k avr32-01/12 259 at32uc3a 25. synchro nous serial controll er (ssc) re v: 3.0.0.2 25.1 features ? provides serial synchronous communicatio n lin ks used in audi o and telecom applications ? contains an independent re ceive r and tr ansmitter a n d a comm on cloc k d i v i d er ? interfa ced with tw o pdca channels (dma acce ss) to reduce proce ssor overhead ? offer s a configura b le fr ame sync and data length ? rece iver and tr ansmitter can be progra mmed to start automaticall y or on detectio n of different events on the f r ame sync signal ? rece iv er a nd tra ns mit t e r i ncl u d e a data signal, a clock signal and a fr am e synchronization signal 25.2 overvi ew the atmel synchronous serial controller (ss c ) provides a synchro n ous communicati on link wit h external devices . it suppor ts ma ny seri al synchronous communication protocols generally used in au d io an d teleco m applicatio ns suc h as i2s, shor t frame sync, long fram e sync, etc. the ssc co ntains an independen t receive r and transmitter and a common clock divider. the receiver a n d the transmitt er each interface wi t h three signals: the tx_da t a/rx_data signal fo r data, the tx_clock/rx_cloc k signa l for the clock an d the tx_frame_sync/rx_frame_ sync sign al for the fram e sync. the transfer s can be pro- gramme d to start automatica lly o r on differen t events detecte d on th e frame sy nc signal. the ssc?s high-level of programmability and its tw o dedicated pdca channels of up to 32 bit s permit a co ntinuo u s high b it rat e d at a tr an sfer with o ut p rocesso r interv e ntio n. featurin g connection to two pdca c hannels , t he ssc permits interfacin g with low processor overhead to the following: ? codec?s i n m ast er or sla v e m ode ? dac through dedicated seri al interface, particularly i2s ? magnetic card reader 32058k avr32-01/12 260 at32uc3a 25.3 block diagram figur e 25-1. blo ck diagram 25.4 a pplication bloc k diagram figur e 25-2. applic ation block diagram ssc interface pdca peripheral bus bridge high speed bus peripheral bus power manager clk_ssc pio interrupt control ssc interrupt tx_frame_sync rx_frame_sync tx_clock rx_clock rx_data tx_data test management line interface management interrupt manag e ment frame time slot management ssc power man agement codec serial audio os or rtos driver 32058k avr32-01/12 261 at32uc3a 25.5 i /o lines description 25.6 p roduct dependencies 25.6.1 i/ o li nes th e pins used for interfacing t he compliant external device s may be multiplexe d with pi o lines. befo re usin g the ssc r eceiver, the pi o controller must b e configur ed to dedicat e th e ssc receive r i/o l ine s to the ss c per iphe ral mod e. before us ing th e ssc tr ansmitte r, th e pi o c ont roller mu st be co nfi gure d to ded icate th e ssc transmitter i/ o lines to t he s sc pe r iphe ra l m ode. 25.6.2 power management the ssc clo c k is generated by the power manager. before using the ssc , th e programmer must ensure that t he ssc clock is enabl ed in th e powe r manager. in the ssc des cription, master clock ( c lk_ssc) is the bu s clo ck o f the peripher al bu s to which th e s s c i s connect ed. 25.6 .3 interrupt th e ssc interfac e ha s an interrupt lin e connected to th e interrupt controller. handlin g interrupts requires programming th e interrupt controlle r before configuring the ssc. all ssc in terrupt s can be enabled/di sabled conf iguring the ssc interrupt mask regis t er. each pending an d un m as k ed ss c in terr upt w ill as ser t the ss c in t err upt l i ne. t he ssc inte rr upt se r- vice routine can ge t th e interrupt orig in by readin g the ssc interrup t status register. 25.7 functional description th is chapte r contains th e functional description of t h e fo llowing: ssc function al block, clock managemen t, data forma t, start, transmitter, receiver and frame sync. the receiver and transmitter operat e separately. however, they ca n work synchron ously by pro- gramming t he receiver to use t he transmit clock and/o r t o start a da ta transfer wh en transmission starts. alternatively, this can be do n e by programming t he transmitter t o use t he receive clock and/o r to st ar t a data tr ans fer w h en rece pt ion starts. th e transmitter and the receiver ca n b e pro- grammed to operate with t h e clo ck signals provided on either the tx_clo ck or rx_clock pins. t h is allows the ssc t o suppo rt many slave-mo de da ta tran sfers. th e maximu m clock spe e d allowe d o n the tx_clo ck an d rx_clock pi ns is the master clock divi d ed by 2. tabl e 25-1. i/o lin es descr ipti on pin name pin description type rx_frame_sync receiver frame synchro input/output rx_clock receiver clock input/output rx_da ta receiver data in put tx_frame_sync transmitter fr ame synchro input/output tx_clock transmit ter clock input/output tx_data transmitt er data output 32058k avr32-01/12 262 at32uc3a figur e 25-3. ss c f u nctio na l b loc k di agr am 25.7 .1 cloc k management th e transmitter cloc k can b e generat ed by: ? an extern al clock received on the tx_clo ck i/o pad ? the receiver clock ? the intern al clock divider th e receiver clock ca n be generate d by: ? an extern al clock received on the rx_clock i /o pad ? t he transmitte r clock ? the intern al clock divider further more , t he tra n smitte r blo c k can gen er ate an external cloc k o n th e tx_cl o ck i/ o pad, and the receive r bl ock ca n generate an ex ter nal clock on t he rx_clock i/o pad. th is allows t he ssc to support ma ny maste r a nd slave mode data transfers. clock divider user interface peripheral bus clk_ssc interrupt control start selector receive shift register receiv e hold in g register receive sync hold in g reg ister pdca interrupt controller rx_frame_sync rx_data rx_clock frame sync controller clock output controller receive clock controller transmit holding register transmit sync holding register tr ans m it s hi f t r egist er frame sync controller clock output controller transmit clock controller start selector tx_frame_sync rx _frame_sync tx_clock input tr an sm itter tx_pdca load shift rx clock tx clock tx_clock tx_frame_sync tx_data receiver rx clock rx_clock input tx clock tx_frame_sync rx _frame_sync rx_pdca load shift 32058k avr32-01/12 263 at32uc3a 25.7.1 .1 clock divider figur e 25-4. div ided clock block diagram t he ma st e r clo ck d ivide r is d eterm ine d by the 12 -b i t field d iv cou nte r a nd c ompar ato r ( so i ts maximal va lue is 4095) in the clock mode regist er cmr, allowing a master cl ock divisio n by up t o 8 190. the divided clock is provided t o both t he receiver an d transmitter . wh en this fiel d is programmed t o 0, t he clock divider is not us ed an d remain s inactive. whe n di v is se t to a v alue eq ual to or greate r th an 1 , t he divid ed clock has a freque ncy of mas- te r clock divided by 2 ti mes div. each level of the divide d clock ha s a duration of th e master clock mult ip lied by di v. this ensures a 50 % duty cycl e for the divid ed clock regardless o f whether th e div value is e ve n or odd. figur e 25-5. divid ed clock generation 25.7.1.2 transmitter clock management th e transm itter clo ck is generated from th e re ceiver clock or the divider clock or an external clock scan ned on t he tx_clock i/o pad. the transmitter clock is sel ected by the cks fi eld in tcmr (trans mit clock mode registe r). tran smit clock can be inverted indepen dently by the cki bits in tcmr. tabl e 25-2. maximum minimum clk_ss c / 2 c lk_ssc / 8190 cmr / 2 clk_ssc divi ded clock 12-bit c oun ter clock divider master clock divided clock div = 1 master clock divid ed clock div = 3 divid ed clock frequ ency = clk_ssc/2 divided clock f req uency = clk_ssc/6 32058k avr32-01/12 264 at32uc3a the transmitt er ca n al so drive the tx_clock i /o pad contin uously or be limited t o the actual data transfe r. th e clock output is con figured b y t he tcmr register. the tr ansmit clock inver- sion (cki) bits h ave no effect on th e clock outputs . programming the tcmr register to selec t tx_clock pin (c ks field) and a t the same time contin uous transmit clock (cko field ) might lead t o unpredict able results. figur e 25-6. transmitter clo ck management 25.7.1.3 receiver clock management th e receiver clock is g ener ated from the tra n smitter clock or the divider clock or an external cloc k scan ned on the rx_clock i /o pad. the receive cloc k is se lected by the cks field in rcmr (receive clock m ode register). receive cloc ks can be inverted indepen dently by the cki bi ts in rcmr. th e receiver ca n also drive th e rx_clock i/o pad continuo usly o r be limited to th e act ual data t ra n sfer . th e clo c k o utp u t is c o n fi g ured b y th e rcm r re g iste r . th e r e c eive cl o ck inv e rsi on (cki) bi ts hav e no effect on th e clock outp uts. programm ing the rcmr regi ster to select rx_clo ck pin (c ks field) and at t he sam e time continuo us receive clock (cko field) can lead t o unpredict able results. tx_clock(pin) receiver clock divider clock cko data transfer tri-state controller inv mux cks mux tri-state controller cki ckg transmitter clock clock output 32058k avr32-01/12 265 at32uc3a figur e 25-7. receiv e r c lo ck m anage m ent 25.7.1.4 serial clock rati o considerations th e transmitter and t he receiver can be programmed to operat e with the cloc k signa ls provided on ei th er th e tx_clock or rx_clock pi ns. t his allows t he ssc to suppor t many slave-mode data transfers. i n th is case, th e maximu m cloc k spee d allowe d on the rx_clock pi n is: ? m aste r c loc k divided b y 2 if receive r fra me synchr o is i n p ut ? m ast er cloc k divid e d by 3 if receiv e r frame syn chr o is o utp ut in addi ti on, t h e m aximu m clo ck s p e ed allowe d on the tx_clo ck pin is: ? master clock divided by 6 if transmit frame synchr o is input ? master clock divided by 2 if transmit frame synchr o is output 25.7.2 transmitte r operations a tra nsmitte d fra me is triggered by a st a rt even t an d can be followed by sync hronization data before data transmission. th e st art eve nt is con figu r ed by se tting th e transm it clock mod e regi ster (tcmr). see s ection ?25.7.4? on p ag e 267. the f ra me synchronization is config ured sett ing the transmit frame mode register (tfmr). see sectio n ?25.7.5? o n pag e 269. to transm it data , the transmitte r uses a shif t register clocked by t he transmitter clock si g nal and t he start mo de select ed in the tcmr. data is wri tte n by t he applicat ion to the thr r egister then transferre d to the sh ift register accordin g to the data form at selected. when both the thr a nd the transmit shi ft register ar e empty , the status fl ag txempty is set in sr. when t he tr ansmit holding regist er is transferre d in th e transmit shift register, th e status fl ag txrdy is set in sr an d a dditional data ca n be loade d in the holdin g register. divider cl ock rx_clock (pin) transmitter clock mux tri -st ate controller cko data transfer inv mux cki tr i-state controller ckg rec eiver clock clock output cks 32058k avr32-01/12 266 at32uc3a figur e 25-8. transmitter bloc k diagram 25.7.3 receiver operations a rec eived fr am e i s trigg ered by a s tart event an d ca n be foll owed by sync hr onizat io n da ta before data transmission. the star t ev en t is conf igur ed setti n g th e receiv e cl oc k mo d e re gister (rcmr). see section ?25.7.4? on p ag e 267. the fram e synchronization is co nfigur ed setting th e receive frame mode register (rfmr). see sec ti on ?25.7. 5 ? o n page 26 9. the receiver uses a shif t regist er clocked by th e receiver clock signal and the s tart mode selected in t h e rcmr. th e data is transferred from th e sh ift register dependi ng on th e data for- mat selected. when th e receiver shift register is f ull, the ssc transfers th is data in t h e holdin g register, the sta- tus flag rxrdy is se t in sr and t he data can b e read in th e receiver holdi ng register . if another transfer occurs before re a d o f t he rhr register, the s tatus fla g overun is set in sr and the receiver shift regis t er is transferred in t h e rhr register. tfmr.datdef tfmr.msbf 0 1 transmit shift register 0 1 thr tshr tfmr.fslen tcmr.sttdly tfmr.fsden tf m r.dat nb cr.txen cr.txdis sr.txen tx_data tfmr.datlen tcmr.sttdly tfmr.fsden start selector rx_frame_sync tx_frame_sync transmitter clock 32058k avr32-01/12 267 at32uc3a figur e 25-9. receiver bloc k diagram 25.7 .4 start the t ransmitt er and receiver can b oth be progr ammed to star t t heir operatio ns when an event occurs, r especti vely in the tra nsm it start selection (sta rt) fiel d of tc mr an d in th e receive start sele ct ion (start) field of rcmr. under the following conditi ons th e start event is independen tly programmable: ? continuous. in th is case, the tran smission starts as soon as a word is w ritt en in thr and the reception starts as soo n as the receiver is en abled. ? synchrono usly wit h the transmitter/receiver ? o n detection of a falling/risi ng ed ge on tx_frame_sync/rx_frame_sync ? o n detec t ion of a l ow l evel/hi gh l eve l on tx_fram e_sync/r x_ fram e_sync ? o n detection of a l eve l change o r an edg e on tx_frame_sync/rx_frame_sync a star t can be program m ed in the sam e mann er on either side of th e transmit/ receive clock register (rcmr/tcmr). thus, the s tar t co uld be on tx_frame_s ync (transmit ) or rx_frame_sync (receive). mo reover, th e receiver c a n start when data is detected i n the bi t strea m wit h the comp are functions. det ection on tx_frame_sync/rx_frame _sync input/out put is done by the field fs os of t he transmit/r eceive frame mode register (tfmr/rfmr). divider clock rx_clo ck (pin) transm itter clock mux tr i-st ate controller cko d ata tr ans fer i n v mux cki tri-state controller ckg receiver clock clock o utput cks 32058k avr32-01/12 268 at32uc3a figur e 25-10. transmi t s tart mo de figur e 25-11. receive pulse/e dge start modes x b0 b1 b1 b0 b0 b1 b1 b0 b0 b1 b0 b1 b 0 b1 b1 b0 x x x x tx_data (output) x start= any edg e o n tx_frame_sync tx_data (output) start = level c hange on tx_frame _sync tx_data (output) start= rising e dge on tx_frame_sync tx_data (output) start= falling e dge on tx_frame_sync t x _ d ata (out put) start = hi gh level on tx_frame_sync tx_data (output) star t= low level on tx_frame_sync tx_frame_sync (input) tx_clock (input) s t t d ly sttdly s t t d ly sttdly st t d ly st t d ly rx_clock rx_frame_sync (input) rx_data (input) start = high level on r x_frame_sync rx_data (input) start = fa llin g edge on rx_frame_sync rx_data (input) start = r isi ng edge on rx_frame_sync rx_data (input) start = le vel change o n rx_frame_sync rx_data (input) start = any edg e on rx_frame_sync rx_data (input) start = low le vel on r x_frame_sync x x x x x x b0 b0 b0 b0 b0 b0 b0 b1 b1 b1 b1 b1 b1 b1 sttdly sttdly sttdly sttdly sttdly sttdly 32058k avr32-01/12 269 at32uc3a 25.7.5 frame sync the t ransmitte r a nd receive r frame sync p in s, t x _frame _sy n c and rx_frame_sync, can b e programme d to gener ate different kinds o f frame synchronization sign a ls. the frame sync ou t put se lection (fsos) field in the receive frame mode regist er (rfmr) and in the transmit frame mode register (t fmr) ar e used to select the require d waveform. ? programmable lo w or high levels during data transfe r ar e supported. ? programmabl e hig h leve ls before the start of data transfers or toggling are also supported. if a pu lse wavefo rm is selected , t he fram e sync length ( fslen) fiel d in rfmr a nd t fmr pro- grams t he lengt h of th e pulse, fro m 1 bit time up t o 1 6 bit time. the per iodicity o f t he receive and transmit frame sync p ulse output ca n be programmed through t he period divider selectio n (period) field in rcmr an d tcmr. 25.7.5.1 fra me sync data frame sync da ta transm its o r re ceives a specific ta g during the fram e sync signal. during the fram e sync signal , th e rece iver can sample the rx_data lin e a nd s tor e th e data in t he receive sync holdin g register and the transmitte r can transfer transmit sync holdin g reg- ister in t he shif ter register. t he data length to be sampled/shift ed out during the frame syn c sign al is programmed by the fslen field in rfmr/tfmr. concerning the receive frame sync data operatio n, if the frame sync leng th is equa l to or lower t h an th e delay between t he start eve nt an d the act ual data reception, th e dat a sampling operation is p erforme d in the rece iv e s yn c holding register th r ough the receiv e shift register. the transmit f rame sync operation is performe d b y t h e t ransmi t ter onl y if th e bi t fra me sy nc dat a enable (fsden) in tfmr is set. if the f r ame sync lengt h is equal to or lower than the de lay betwe en th e start eve nt a nd th e ac t ual data transmission, the norma l transmission has pri- orit y an d th e data containe d in th e transmit sync holdin g register is transferred in t h e transmit register , the n shifte d out. 25.7.5.2 f ra m e s yn c edg e detection th e fram e sync ed ge detection is p rogrammed by the fsedge field in rf mr/tfmr. this sets the corr esp ondi n g flags rxsyn/t xsyn in the ssc stat us register (sr) on frame synchr o edg e detectio n (sig nals rx_frame_sync/tx_frame_sync). 32058k avr32-01/12 270 at32uc3a 25.7.6 receive co m p a re mod es figur e 25-12. receive compare modes 25.7.6 .1 compare functions compare 0 can b e one s tart event o f the receiver. i n this case, t he re ceiver compares at each ne w sample th e last fslen bits received a t th e fsle n lowe r bit o f th e data contained in the compar e 0 r e giste r ( rc0r) . w hen t hi s st a rt e v en t i s se lect ed , t he u s er c an p ro g r a m the receiver to start a ne w data transfer either by w rit ing a ne w compar e 0, or by r eceivin g continu- ousl y un til compar e 1 occurs. this selecti on is done wi th the bit (stop) in rcmr. 25.7 .7 data format th e data framing format of both the transmitte r and the receiver ar e programmable through the transmitter f rame mode re gister (tfmr) a nd the receiver f rame mode register (rfmr). in either case, th e user ca n independent ly select: ? the event tha t starts th e data transfe r (start) ? the dela y in numbe r of bi t period s betwee n th e start event and the first dat a bit ( sttdly ) ? t he lengt h of t he data (datlen) ? t he number of data t o be transferre d f o r e ach star t e vent (datn b ). ? the lengt h of synchronizatio n transferred fo r each start even t (fslen) ? the bi t sense: most or lowe st significant bit first (msbf). additiona lly, the transmitter ca n be used to t r ansfer synchronizati on and select the l e vel driven on t he tx_data pin while not in da t a transfer operation. th is is done respectively by the frame sync data enable (fsde n ) and by the data default value (datdef) bits in tfm r. rx_data (input) rx_clock cmp0 cmp1 cmp2 cm p3 start fslen up to 16 bits (4 in th is exa m ple) sttdly ignored datlen b2 b0 b1 32058k avr32-01/12 271 at32uc3a figur e 25-13. transm it an d re ceive fr am e form at i n edge/ pulse star t mo des note: 1. e xample of inpu t on fallin g edge of tx_frame_sync/rx_frame_sync. tabl e 25-3. dat a frame reg iste rs transmitter receiver field length comment tfmr rfmr datlen up to 32 size of word tfmr rfmr datnb up to 16 nu m b er of w or ds trans m i tt ed in f r ame tfmr rfmr msbf most s ignifica nt bi t first tfmr rfmr fslen up to 16 size of sy nc hro data register tfmr datdef 0 o r 1 dat a default va lue ended tfmr fsden enable send tshr tcmr rcmr period up to 512 fr am e s i ze tcmr rcmr sttdly up to 255 size of transmit sta rt delay datnb datlen data data data data data data default default sync data sync data ignored from datdef s t a rt f rom dat d ef dat len to rhr to rhr from thr from thr from thr from thr from datdef from datdef ignored default default sync data to rshr from tshr fslen s ta rt tx_f ra m e _sync / rx _ fr ame_ sync tx_data (if fsden = 1) tx_data (if fsden = 0) rx_data sttdly sync data period (1) 32058k avr32-01/12 272 at32uc3a figur e 25-14. transmit frame format in continuo us mode note: 1 . sttdl y is set to 0. in this example, thr is load ed twice. fsden valu e has no effe ct on the transmission . syncdata can not be outpu t in continu ous mode. figur e 25-15. receive f rame format in continu ous mode note: 1 . sttdl y is set to 0. 25.7.8 loo p mode the rece iv er can b e program med t o r ece iv e tran smission s f rom th e transmitt er. thi s is d on e by setti ng the loop mo de (loop ) bi t in rfmr . i n th is case , rx_dat a is connected to tx_data, rx_frame_sync is connec t ed to tx_fra me_sync and rx_clock is connected to tx_clock. 25.7 .9 interrupt most bi ts in sr have a c orrespondin g bit in interrupt management registers. th e ssc can be programmed t o generat e an interrupt wh en it detect s an event. t he interrupt is controlled by writing ier (inter rupt enab le reg ister) an d idr ( inte rru p t disab l e re gister) these registers enable and di sable, respectively, the correspo nding interru pt by setting and clearing the corresp o nding bit in imr (interru pt m ask register), wh ich controls the ge neration of inter- rupt s by asserti ng th e s sc in terrup t lin e c onnecte d t o th e interru p t co ntroll er. start data data datlen f rom t hr datlen tx_data s tart: 1. txempty set to 1 2. write into t he thr from thr default data data to rhr to rhr datlen datlen rx_data start = enable receiver 32058k avr32-01/12 273 at32uc3a figur e 25-16. interrup t block diagram 25.8 s sc application examples t h e s sc ca n supp o r t sever a l se r i al c omm unicati on mode s used in audio or high spee d serial links. so m e stand ard applications are sh own in t he fo llowin g figures. all s erial link applications supporte d by th e ssc ar e no t list ed here. figur e 25-17. audi o applicatio n block diagram i mr ier i dr clear set i nterr up t c ontr ol ssc int e rr upt txrdy txempty txsync transmitter endtx txbu fe pdca rxbuff endrx receiver rxrdy ovrun rxsync clock sck word select ws data sd msb left channel lsb msb right channel data sd word select ws clock sck ssc tx_clock tx_frame_sync tx_data rx_data rx_frame_sync rx_clo ck i2s receiver 32058k avr32-01/12 274 at32uc3a figur e 25-18. code c app licatio n block diag ram figur e 25-19. time slot application block di agram ssc seria l d at a c l o ck (s cl k) fr a m e sync (fsync) ser i a l da t a o ut s er i a l data in s e r i a l d at a c l o ck (sc lk) frame sync (fsync) seria l da ta out s erial d ata in dsta rt dend first time slot codec tx_clock tx_frame_sync tx_data rx_data rx_frame_sync r x _ clo ck codec first time slot codec se cond time slot dat a in da ta o ut fsync s c lk serial data clock (sclk) fram e sy n c (f sync) serial data out serial data in dsta rt first time slot second time slot dend s sc tx _c lo ck tx_frame_sy nc tx_data rx_data rx_frame_sync rx_clock 32058k avr32-01/12 275 at32uc3a 25.9 u ser interface tabl e 25-4. register mapping offset register register name access reset 0x0 co ntrol register cr write ? 0x4 cloc k mo de register cmr read/write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive cloc k mode register rcmr read/write 0x0 0x14 receive fram e mo de register rfmr read/write 0x0 0x18 tran smit clock mode register tcmr read/write 0x0 0x1c transmit fram e mode register tfmr read/write 0x0 0x20 receive holdi ng register rhr read 0x0 0x24 tran smit holdin g register thr write ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 recei ve sync. hol d ing regi ster rshr read 0x0 0x34 tran smit sync. holdi ng register tshr read/write 0x0 0x38 receive co mpare 0 register rc0r read/write 0x0 0x3c receive co mpare 1 register rc1r read/write 0x0 0x40 status reg ister sr read 0x000000cc 0x44 interrupt enab le register ier write ? 0x48 inter rup t dis a b le re gister idr write ? 0x4c interrup t mask register imr read 0x0 0x50-0xfc reserved ? ? ? 32058k avr32-01/12 276 at32uc3a 25.9.1 contro l register name: cr acces s type: write-only offset: 0x00 reset value: - ? swrst : software reset 0: no e ffect. 1: perfo rms a software reset. has p riori ty on any other bi t in cr. ? txdis: transm it disable 0: no e ffect. 1: disables transmi t. if a character is c urren tly being transmitted, disables a t en d of curren t character transmission. ? txen: transmit enable 0: no e ffect. 1: enables transmit if txdis is not set. ? r xdis: receiv e di sab le 0: no e ffect. 1: disab les receive. if a characte r is current ly being received , disables at en d o f cur ren t cha ract e r rece ptio n. ? rxen: receive enable 0: no e ffect. 1: enables re ceive if rxdi s is not set. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 swrst ? ? ? ? ? txdis txen 7 6 5 4 3 2 1 0 ? ? ? ? ? ? rxdis rxen 32058k avr32-01/12 277 at32uc3a 25.9.2 cloc k mode register name: cmr acces s type: read/write offset: 0x04 reset value: 0x00000000 ? div: cloc k divider 0: th e cl oc k di vid e r i s not active. any o the r value: the divide d clock equals th e master cloc k divide d by 2 time s div. th e maximu m bit rate is clk_ssc /2. th e minimu m bit rate is clk_ssc/ 2 x 4 0 95 = clk_ssc/8190. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? div 7 6 5 4 3 2 1 0 div 32058k avr32-01/12 278 at32uc3a 25.9.3 receive cloc k mode register name: rcmr acces s type: read/write offset: 0x10 reset value: 0x00000000 ? per iod: receive period divide r selection this fiel d select s the divider to app ly to th e selected receive clock in orde r to generate a new f rame sync sign al. if 0, no perio d sign al is generated . if not 0, a perio d sig nal is generat ed each 2 x (perio d+1) receive clock. ? sttdly : receiv e start delay if st td ly is no t 0, a d e lay of sttdly clo ck cycles is ins erted between th e star t even t and the actual star t of reception. when th e receiver is p rogrammed to start synchronou sly with the transmitter, th e delay is also a pplied. note : it is ve ry importan t th at sttdly be se t care fully. if sttdly mu st be se t, it shou ld b e done in relation to ta g (receive sync data ) reception. ? stop: rec ei ve sto p selection 0: a f te r completi o n o f a d ata transfer w he n st arti ng wit h a c ompar e 0 , th e re ceiver sto p s th e data transfe r and w ait s fo r a ne w compar e 0. 1: after starting a r eceive with a compar e 0, th e receiver operates in a c ontinuous mode until a compar e 1 is detected. ? sta rt : re ce iv e s t ar t selectio n 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ? ? ? stop start 7 6 5 4 3 2 1 0 ckg cki cko cks start receiv e start 0x0 con tinuo u s , a s soon a s the rec e i ve r is e n ab led , a n d i mmed iatel y a fte r t he e n d of transfer of the pr evious data. 0x1 tr ansmit start 0x2 detectio n o f a l o w lev e l on rx_fra me_syn c sig nal 0x3 dete cti o n o f a h ig h le ve l o n rx _f ram e_sync sig n al 0x4 detectio n of a fallin g e dge on rx_f rame_sync signal 0x5 detectio n of a rising edg e on rx_frame_syn c signal 0x6 detectio n of an y level change o n rx_f rame_sync signal 0x7 dete cti o n o f a n y e d ge o n rx_f rame _ sync s i g n al 0x8 compar e 0 0x9-0xf reserved 32058k avr32-01/12 279 at32uc3a ? ckg: re cei ve cloc k gati ng selection ? cki: receive clo c k inversion 0: the data inputs (data and frame sync signals) are sample d o n rec eiv e clo ck falli ng edg e . t he f ra me s ync sig na l o ut- put is s hifte d out on receive clock rising edge. 1: the dat a inputs (dat a and fram e sync signals) ar e sample d o n re cei ve cl o ck risin g edge. the fra m e sync sign al out- put is s hifte d out on receive clock fal ling edge. cki a ffect s only the receive clock an d n ot th e output clock si gnal. ? cko : rece ive cloc k outpu t m ode selection ? cks: receiv e cloc k selecti on ckg re c eiv e c lo c k g at i ng 0x0 none , continuo us clock 0x1 receiv e clock enabl ed onl y if rx_frame_sync low 0x2 receiv e clock enabl ed onl y if rx_frame_syn c high 0x3 reserved cko re ceive cloc k outp ut mode rx_c lock pin 0x0 none input-only 0x1 continuou s receiv e clock output 0x2 recei ve clock on ly duri ng data t r an sfers output 0x3-0x7 reserved cks selected receiv e clock 0x0 divi ded clock 0x1 tx_clock cloc k si g n al 0x2 rx_c lock pin 0x3 reserved 32058k avr32-01/12 280 at32uc3a 25.9.4 recei ve fram e mod e register name: rfmr acces s type: read/write offset: 0x14 reset value: 0x00000000 ? fslenhi: receiv e frame sy nc lengt h high part th e fou r msb of t he fsle n bitfield. ? f sedge: frame sync edge detection determines which edge on frame s ync w ill generate the in terrupt rxsy n in the ssc status register. ? fsos: receive fram e sync output selection ? f slen: receive fr ame sync length th is field define s th e length o f the receive fram e sync signal and t he numbe r of bits sampled and stored in t h e receive sync data re gist er. when this mode is selecte d b y th e start field in the receive clock mode re gister, it als o deter- mine s the len gth of the sampled d ata to be compare d to th e comp are 0 or comp are 1 registe r. note: t he four most significant bi ts fo th is bitfield ar e in the fslenhi bitfield. pulse l e ngth is e qual to ({fslenhi,f slen} + 1) receive clock pe riods. t hus, if {f slenhi,fslen} is 0 , th e receive frame sync signal is generate d durin g o ne receive clock period. ? dat nb: data number per frame 31 30 29 28 27 26 25 24 fslenhi ? ? ? fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ? ? ? ? datnb 7 6 5 4 3 2 1 0 msbf ? loop datlen fsedge frame sync ed g e detection 0x0 positive edge detection 0x1 n egative ed ge detection fsos select ed re ceive fr ame sy nc sig nal rx _f rame_sync pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low durin g data transfer output 0x4 driven hi gh dur ing data transfer output 0x5 toggling at each start of da ta transfer output 0x6-0x7 reserved undefined 32058k avr32-01/12 281 at32uc3a this fiel d defines t he numbe r of data words to b e received afte r each transfer star t, whic h is equal t o (d atnb + 1). ? msbf : mos t sig ni f ican t bi t fi r st 0: the lowest sig nificant bi t of th e dat a register is sam pled first in th e bit stream. 1: the most significant bi t of t he data register is sa mpled first in t he bit stream. ? loop: lo op mode 0: norm al operat ing mode. 1: rx_data is driven b y tx_data, rx_frame_sync is drive n by tx_frame_sync and tx_cl ock drives rx_clock. ? da tlen : data l e ngth 0: forbidde n value (1-bit dat a lengt h no t supported). an y other value: the bit stream con tai ns datlen + 1 data bit s . moreov er, i t defines the t rans f e r s ize perf or med b y t he pdca assigned to the receiver . if datl en is lower or equal to 7, data transfers are in bytes. i f datl en is between 8 and 15 (included), half-word s are transferred, and f or any other value, 32-bit word s are transferred. 32058k avr32-01/12 282 at32uc3a 25.9.5 transmit cloc k mod e regist er name: tcmr acces s type: read/write offset: 0x18 reset value: 0x00000000 ? period: transmit perio d div ide r s e lect ion this fi eld selects t he divide r to apply to t he select ed transmit clock to generat e a new fram e sync signal . if 0, no period sign al is generated . if not 0, a p eri od sign al is generate d at ea ch 2 x (period+1) transmit clock. ? sttdly: transmit start delay if st tdly is not 0, a de lay of sttdly clock cycles is inserted between t he start event and the act ual start of transmission of data . whe n th e transmitter is p rogrammed t o start synchronou sly with the receiver, th e delay is also a pplied. note : sttdly must be se t carefully. if sttd ly is too short in respec t to tag (transmi t syn c data) emission, data is emit- ted instea d of th e en d of tag. ? start : tr ansmit start se lec tion 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ? ? ? ? start 7 6 5 4 3 2 1 0 ckg cki cko cks start t ransmit start 0x0 continuous, as so on as a word is written in the thr register (if tran smit is enable d), an d immediately af ter th e end of trans fer of th e prev ious data. 0x1 receiv e start 0x2 detecti on of a l ow leve l on tx_f rame_sync signal 0x3 detecti on of a h igh l evel on tx_frame_sync sign al 0x4 detecti on of a falli ng edg e on tx_frame_sync signal 0x5 detecti on of a ri sing ed ge on tx_frame_sync signal 0x6 detecti on of any leve l chang e on tx_f rame_sync signal 0x7 detecti on of any e dge on tx_frame_syn c signal 0x8 - 0xf reserved 32058k avr32-01/12 283 at32uc3a ? ckg: transmit clock gating selection ? ck i: transm it cloc k inv ersion 0: the data outp u ts (d ata and frame sync signals) are shifted out on t r ansmit clock falling edg e . the frame sync signal input is sample d on transmit clock rising edge. 1: the data output s (data and fram e sync signals) ar e shift ed out on transmit clock rising edge. the fram e sync signal input i s sampled on tra ns mit cloc k fal ling edge. cki a ff ect s o nly th e tran smit clock an d no t the outpu t clock sig nal. ? cko: transmit clock outpu t mod e selection ? cks: transmit cloc k selection ckg tr ansmit cloc k gating 0x0 none , contin uous clock 0x1 tran smit clock enabl ed only if tx_f rame_sync low 0x2 tr an smit clock enabl ed on ly i f tx _ f ram e_sync high 0x3 reserved cko transmi t clock outp ut mode tx_clo ck pin 0x0 none input-only 0x1 continuous transmit clock output 0x2 tran smit clock on ly duri ng data transfers output 0x3-0x7 reserved cks selected transmit clock 0x0 divided clock 0x1 r x_clo ck cloc k si g n al 0x2 tx_clo ck pin 0x3 reserved 32058k avr32-01/12 284 at32uc3a 25.9.6 transmit frame m ode register name: tfmr acces s type: read/write offset: 0x1c reset value: 0x000000 00 ? fslenhi: transmit fr ame sync leng th high part th e fou r msb of t he fsle n bitfield. ? f sedge: frame sync edge detection det ermine s whic h edge on f rame sy nc wil l gen e rate the interrupt tx syn (status register). ? f sde n: fr a m e s y nc data e n able 0: the tx_data li n e is driven with t he default valu e during t he transm it frame sync sign al. 1: tshr val u e is shift ed out during the transmission of th e transmit fram e sync signal. ? fsos: transmit fr ame syn c output selection ? fslen: tran smit frame sy nc length this fi eld defines t he length of the transmit fram e sync signal and the number of bits shi fte d out from the transm it sync data register if fsde n is 1. n ote : th e fou r most significant bi ts fo this bitfiel d are in the fsle nhi bitfield. 31 30 29 28 27 26 25 24 fslenhi ? ? ? fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ? ? ? ? datnb 7 6 5 4 3 2 1 0 msbf ? datdef datlen fsedge frame sync edge detection 0x0 positive ed ge detection 0x1 negative edge d etection fsos sele ct ed tr ansmit fram e sync signal tx_frame_sync pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven lo w durin g d ata trans f er output 0x4 driven hi gh duri ng da ta transfer output 0x5 t o ggli n g a t eac h start o f d a t a transf er output 0x6-0x7 reserved undefined 32058k avr32-01/12 285 at32uc3a pulse le ng th is equ al to ({fsle nhi,fslen} + 1) transmi t clock periods, i.e., the pulse length can range from 1 to 16 transm it clock periods. if {fslenhi,fslen} is 0 , th e transmit frame sync sign a l is generated durin g one transm it clock period. ? dat nb: data number per frame this fiel d defines t he numbe r of data words to be transferre d after each transfer star t, whic h is equal t o (dat nb +1). ? msbf : m os t sig ni f ican t bi t fi r st 0: the lowest significant bi t of th e data register is shift ed ou t first in th e bit stream. 1: th e m o st significa nt bi t o f th e d ata regi ster i s s hifted ou t fir st i n th e bit stream. ? dat def: data default va lue th is bit defi nes th e level driven on the tx_d ata pin wh ile out of transmission . note tha t if th e pi n is defined as mu lti-d ri v e by t he pi o controller, th e pi n is enabled on ly if th e scc tx_data output is 1. ? da tlen : data l e ng th 0: forbidde n value (1-bit dat a lengt h no t supported). an y other value: the bit stream con tai ns datlen + 1 data bit s . moreov er, i t defines the t rans f e r s ize perf or med b y t he pdca assign e d to the transmit . if datlen is lowe r o r equ al to 7, data transfers are bytes, if datlen is b etwee n 8 and 15 (included), half-wor ds ar e transferred, and for any othe r value, 32-b it wor ds ar e transferred. 32058k avr32-01/12 286 at32uc3a 25.9.7 ss c r ec e ive ho l din g regis ter name: rhr acces s type: read-only offset: 0x20 reset value: 0x000000 00 ? r da t: re ceiv e data right aligne d regardles s o f th e number of data bits define d by datl en in rfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 7 6 5 4 3 2 1 0 rdat 32058k avr32-01/12 287 at32uc3a 25.9.8 transmit hold ing register name: thr acces s type: write-only offset: 0x24 reset value: - ? tda t: tr ansmit data righ t aligne d regard les s o f th e n u mb e r of data bits de fined by d a tlen i n tfmr. 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 7 6 5 4 3 2 1 0 tdat 32058k avr32-01/12 288 at32uc3a 25.9.9 rece ive synchronizat ion holdin g register name: rshr acces s type: read-only offset: 0x30 reset value: 0x000000 00 ? r sdat : rec eiv e synchr o n izati on data 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rsdat 7 6 5 4 3 2 1 0 rsdat 32058k avr32-01/12 289 at32uc3a 25.9.10 transmit synchronizatio n holding register name: tshr acces s type: read/write offset: 0x34 reset value: 0x000000 00 ? tsdat: tran smit synchronizat ion data 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 tsdat 7 6 5 4 3 2 1 0 tsdat 32058k avr32-01/12 290 at32uc3a 25.9.11 recei ve compar e 0 register name: rc0r acces s type: read/write offset: 0x38 reset value: 0x00000000 ? cp0 : receiv e compare dat a 0 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 cp0 7 6 5 4 3 2 1 0 cp0 32058k avr32-01/12 291 at32uc3a 25.9.12 recei ve compar e 1 register name: rc1r acces s type: read/write offset: 0x3c reset value: 0x000000 00 ? cp1 : receiv e compare dat a 1 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 cp1 7 6 5 4 3 2 1 0 cp1 32058k avr32-01/12 292 at32uc3a 25.9.13 s tat u s reg is ter name: sr acces s type: read-only offset: 0x40 reset value: 0x000000cc ? rxen: receive enable 0: receive is di sabled. 1: r ece ive is enable d. ? txen: transmit enable 0: tr ansmit is disa ble d. 1: transmit is enabled. ? rxsyn: receive sync 0: an rx sync has not occurred since the last read of t he stat us register. 1: an rx sync has occurr ed since the last re ad of th e stat us register. ? txsyn: tr ansmit sync 0: a tx sync ha s not occurred since the la st rea d of the stat us register. 1: a tx sync ha s occurred since the last read of t he stat us register. ? cp1: compar e 1 0: a c ompare 1 h as not occurr ed since the last re ad of t he stat us register. 1: a c ompare 1 h as occurr ed since t he last read of th e status register. ? cp0: compar e 0 0: a c ompare 0 h as not occurr ed since the last re ad of t he stat us register. 1: a c ompare 0 h as occurr ed since t he last read of th e status register. ? rxbuff: receive buffer full 0: rc r or rncr have a va lue other than 0. 1: both r c r and r ncr have a value of 0. ? endrx: en d of reception 0: data i s written on the receive counter register or receive n e xt counter register. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? rxen txen 15 14 13 12 11 10 9 8 ? ? ? ? rxsyn txsyn cp1 c p0 7 6 5 4 3 2 1 0 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy 32058k avr32-01/12 293 at32uc3a 1: en d of pdca transfer when receive counter register has arrive d at zero. ? ovrun: receive overrun 0: no da ta has been load ed in rhr whil e p revio us dat a has not been read since t h e last read of th e status register. 1: data has b e en loaded in rhr wh ile previous data has n o t yet been read since t he last read of th e status register. ? rxrdy : receiv e ready 0: rh r is empty. 1: data has b een receive d a nd loade d in rhr. ? txbufe: transmi t buff er empty 0: tcr o r tncr hav e a va lue other tha n 0. 1: both tcr a nd tncr ha ve a valu e of 0. ? endtx : end of transmission 0: the register t cr ha s no t reache d 0 sinc e th e last write in t cr or tncr. 1: the r e gist e r t cr ha s r eac hed 0 sinc e the last writ e i n tc r o r tncr. ? txempty: tr ansmit empty 0: data remain s in thr or is curr ent ly transmitte d fr om tsr. 1: last data written in th r ha s be en loade d in tsr and last data loade d in tsr ha s been transmitted. ? t xr dy: transmit rea dy 0: data has b e en loaded in thr a nd is waitin g t o be loaded in t h e transmit shif t registe r (tsr). 1: thr is empty. 32058k avr32-01/12 294 at32uc3a 25.9.14 interr up t enabl e r egister name: ier acces s type: write-only offset: 0x44 reset value: - ? r xsy n: rx sync interrupt ena ble 0: no e ffect. 1: enab les th e rx sync interrupt. ? t xsyn: tx sync interrupt enable 0: no e ffect. 1: enab les th e tx sync interrupt. ? cp1: compar e 1 interru pt enable 0: no e ffect. 1: ena bles th e compare 1 interrupt. ? cp0: compar e 0 interru pt enable 0: no e ffect. 1: ena bles th e compare 0 interrupt. ? r xbuff: receive buff er full interrupt enable 0: no e ffect. 1: enables the receive buffer full i nterrupt. ? e ndrx: en d o f re ce ption inte rru pt en ab le 0: no e ffect. 1: en able s th e e nd of r ecepti on i nterru p t. ? ovrun: receive overrun interru pt enable 0: no e ffect. 1: enab les th e receive overrun interrupt. ? rxrdy : receiv e ready interrupt enable 0: no e ffect. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? rxsyn txsyn cp1 cp0 7 6 5 4 3 2 1 0 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy 32058k avr32-01/12 295 at32uc3a 1: enab les th e receive ready interrupt. ? txbufe: transmi t buff er empt y interrupt enable 0: no e ffect. 1: enab les th e transmit buffer empt y interrupt ? endtx : end of tran smission interru pt enable 0: no e ffect. 1: enab les th e end of transmission interrupt. ? txempty: tr ansmit empty interrupt enable 0: no e ffect. 1: enab les th e transmit empty interrupt. ? txrdy: transm it ready interrupt enable 0: no e ffect. 1: ena bles th e transmit ready interrupt. 32058k avr32-01/12 296 at32uc3a 25.9.15 interrup t disabl e register name: idr acces s type: write-only offset: 0x48 reset value: - ? r xsy n: rx sync interrupt ena ble 0: no e ffect. 1: disables t he rx sync interrupt. ? t xsyn: tx sync interrupt enable 0: no e ffect. 1: disable s the tx s yn c inte rrupt. ? c p1: compare 1 interru pt disable 0: no e ffect. 1: disables t he compar e 1 interrupt. ? c p0: compare 0 interru pt disable 0: no e ffect. 1: disables t he compar e 0 interrupt. ? rxbuff: receive buffer full interrupt disable 0: no e ffect. 1: dis ables the recei ve bu ffer fu ll interrupt. ? endrx: en d of rece ption interru pt disable 0: no e ffect. 1: disable s the en d of reception interrupt. ? ovrun: receive overrun interru pt disable 0: no e ffect. 1: disables t he receive overrun interrupt. ? rxrdy : receiv e ready interrupt disable 0: no e ffect. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? rxsyn txsyn cp1 cp0 7 6 5 4 3 2 1 0 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy 32058k avr32-01/12 297 at32uc3a 1 : d i s able s t h e rec eive read y interrupt. ? txbufe: transmi t buff er empt y interrupt disable 0: no e ffect. 1: disables t he transmit buffe r empt y interrupt. ? endtx : end of tran smission interru pt disable 0: no e ffect. 1: d isa bles th e en d o f t ra n smis si on interrupt. ? txempty: tr ansmit empty interrupt disable 0: no e ffect. 1: disables t he transmit empty interrupt. ? txrdy: transm it ready interrupt disable 0: no e ffect. 1: disables t he transmit ready interrupt. 32058k avr32-01/12 298 at32uc3a 25.9.16 interrup t ma sk register name: imr acces s type: read-only offset: 0x4c reset value: 0x00000000 ? rxsy n: rx sync interrupt mask 0: th e r x sync in terrup t is d i sab l ed. 1: the rx sync interrup t is enabled. ? t xsyn: tx sync interrupt mask 0: the tx sync interrupt is disabled. 1: th e tx sync interrupt is enabled. ? cp1 : compar e 1 int erru pt ma sk 0: the compar e 1 interrupt is disabled. 1: the compar e 1 interrupt is enabled. ? cp0 : com par e 0 int errupt ma sk 0: the compar e 0 interrupt is disabled. 1: the compar e 0 interrupt is enabled. ? r xbuff: receive buff er full interrup t mask 0: the receive buffer full interrup t is disabled. 1: the receive buffer full interrup t is enabled. ? endrx: en d of rece ption interru pt mask 0: th e en d o f rece pt io n in terr upt is disabled. 1: the en d of reception interrupt is enabled. ? ovrun: receive overrun interru pt mask 0: the receive overrun interrup t is disabled. 1: the receive overrun interrupt is enabled. ? rxrdy : receiv e ready interrupt mask 0: the receive re ady interrup t is disabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? rxsyn txsyn cp1 cp0 7 6 5 4 3 2 1 0 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy 32058k avr32-01/12 299 at32uc3a 26. universal synchronous/asynchr onous receiver/tran smitt er (usart) re v. 4.0.0.2 26.1 features ? programmabl e baud rate generator ? 5- t o 9-bit full-duplex synchron ous or asynchronous serial communications ? 1 , 1.5 or 2 stop bits i n asynchronous mode or 1 or 2 st op bi ts in synchronou s mode ? p arity generation and erro r detection ? f raming error de tection, over run erro r detection ? m sb- or lsb-first ? optio nal break generation an d detection ? by 8 or by 16 ove r-s ampling receiv er frequency ? optio nal hard ware handshaking rts-cts ? re c eive r tim e -out an d tr ansmitter time gua rd ? op ti o nal mu l tid r op mo de wi th ad dress ge nerati on an d dete ction ? rs48 5 with drive r contro l signal ? iso7816, t = 0 or t = 1 protocols for interfaci ng wit h smart ca r ds ? nack handling, error counter with repetition an d iteratio n limit ? irda modulation an d demodulation ? commu nication at up to 11 5.2 kbps ? spi mode ? mast er or sl ave ? s erial c lo c k pro gramma bl e phase and pola ri ty ? spi serial cloc k (clk) frequenc y up to intern al clock frequenc y clk_usart/4 ? t est modes ? re m ote l oo pback , local loop back , automati c echo ? suppor ts connection of two periph eral dma contro ller chan nels (pdc) ? offers buffer transfer without p rocessor intervention 26.2 overvi ew the universa l synchrono us asynchron ous receiver transceiver (usart) provides one full duplex univer sal synchronou s asynchron ous serial link. data frame format is widely p rogramma- ble (dat a length, parity, number of stop bits ) to support a m a ximum of standards. the receiver im pleme nts pari ty err or , fra m ing error an d ove rru n erro r detectio n. th e re ceiver time-ou t enables handlin g v a ri able-len gth frame s and t he tr ansm i tt er tim eguard fac ilitat es com mu nica t ion s w ith slow remote devices. multidrop communications ar e also supported thro ugh addres s bit han- dlin g in reception and transmission. th e usart feat ur es thr e e t est mode s : re m ote loopback, lo ca l loo p back an d a utom ati c echo. t he usart supp orts sp ecific operating modes provid ing interfac es on rs48 5 a nd spi buses, with iso781 6 t = 0 or t = 1 sma rt car d slots a nd infrared transceivers. the hardware handshak- ing fe ature en ables an out-of-band flow cont rol by automati c manageme nt o f t he pins rts and cts. th e usart supports th e connection to the periphe ral dm a contro ller, which enable s data transfers to t h e transmitte r and from th e receiver. th e pdc provid es chained buffer manage- ment without an y intervention of t he processor. 32058k avr32-01/12 300 at32uc3a 26.3 block diagram figur e 26-1. usar t block diagram peripheral dma controller channel channel intc power manager div receiver transmitter user interface pio controller rxd rts txd cts clk baudrate generator usart interrupt clk _usart clk_usart/div usart peripheral bus 32058k avr32-01/12 301 at32uc3a 26.4 a pplication bloc k diagram figur e 26-2. applic ation block diagram smart card slot usart rs232 drivers modem rs485 drivers differential bus irda transceivers modem driver field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp pstn spi driver spi transceiver 32058k avr32-01/12 302 at32uc3a 26.5 i/o lines description tabl e 26-1. i/o line description name description type active l evel clk serial clock i/o txd tran smit seri al data or master out sl av e in (mosi) in spi ma ster mode or mast er in slav e ou t (miso ) in spi slav e mode i/o rxd receiv e s er ial da ta or mast er in slav e ou t (miso ) in spi ma ster mode o r m aster out sl a v e in ( mos i) in sp i s la ve mo de input cts c lear to send or sl av e select (nss) in spi sl av e mode input low rts reque st to send or sl av e select (nss) i n sp i mas te r m ode output low 32058k avr32-01/12 303 at32uc3a 26.6 p roduct dependencies 26.6.1 i/ o li nes th e pins used for inte r facing th e usart ma y b e multiplexed with th e pio lines. th e program- mer mus t first program th e pi o controller to assign the desire d usart pi ns to thei r peripheral function. if i/o lines of th e usart are not used by the application, t hey can be used f or other purp oses by the pi o controller. to prevent the tx d line from falling when the usa r t is di sabled, the use of an internal pull up is m andato ry . if t he hardwar e ha ndsh akin g featur e or modem mode is us ed , t he internal pu ll up on tx d must also b e enabled. 26.6.2 power manager (pm) th e usart is not continuo usly clocked. the programmer must first enable t he usart clock in t he powe r manager (p m) before using the usart. howeve r, if th e applicatio n does not require usart op eration s, the usart clock can b e stopp ed when n ot ne eded and be restarte d later. in this case, the us ar t will resume its operations where it left off. configuring t he usart d oes no t require the usart cl oc k t o be enabled. 26.6 .3 interrupt th e usart interrupt lin e is connected on one o f the internal sources of th e advanced interrupt controller. using the usart interru pt requires t he intc to be programme d first. note that it i s not recommended to use the usart i nterrup t lin e in edg e sensit ive mode. 32058k avr32-01/12 304 at32uc3a 26.7 functional description th e usart is capable of managing several typ es o f seria l synchron ous or a synchro n o u s com munic ations . it su p port s the following co mmun icat io n modes: ?5- to 9-bit full-duplex asynchronou s serial communication ?msb - o r lsb-first ?1, 1. 5 or 2 sto p bits ?parity even, odd, marked, spac e or none ?by 8 o r by 16 over-samplin g receiver frequency ?optio na l hard war e ha ndsh aking ?optio na l b r eak ma nag eme nt ?optional multidr op serial communication ?high-spee d 5- to 9-bit full-duplex synchrono us seri al communication ?msb - o r lsb-first ? 1 or 2 s t op bits ?parity even, odd, marked, spac e or none ?by 8 o r by 16 over-sampling frequency ?optio na l hard war e ha ndsh aking ?optio na l b r eak ma nag eme nt ?optional multidr op serial communication ?rs4 85 wit h driver contro l signal ?iso7816, t0 or t1 protocols fo r interf acing wit h smart cards ?nack handling, erro r counte r wit h repetitio n a nd iteratio n limit ?infrare d irda mod ulatio n a nd de mod ulati on ? spi mode ? mast er or sl ave ? s erial c lo c k pro gramma bl e phase and pola ri ty ? spi serial clo ck (clk ) f r eque ncy u p t o i n t ern a l cloc k frequency clk_usart/4 ?test modes ?remot e loopback , local loopback, automa tic echo 32058k avr32-01/12 305 at32uc3a 26.7 .1 ba ud rate generator th e baud rate generator provid es th e bit period clock na med the baud rate clock t o both the receive r and the transmitter. th e baud rate gener at or cloc k source can be select ed by setting the uscl ks fiel d in t he mode register (mr ) between: ?the clk_usa rt ?a division o f t he clk_usart, th e divide r bein g product dependent, but generall y se t t o 8 ?the extern al clock, availabl e on th e clk pin th e baud rate generator is bas ed upon a 16-bit divider, which is programme d with the cd field o f the bau d rat e generator registe r (brgr). if cd is p rogrammed at 0, th e ba ud rate gener- ator doe s not generat e an y clock. if cd is programme d at 1 , the divide r is bypasse d and beco mes inactive. if th e e xternal cl k cl ock is se lec ted , the d u rat ion of the l o w a n d hig h lev els of the sig na l pro- vi de d o n the cl k p in m us t b e l onge r th a n a clk_usa r t pe r io d . t h e f r e quenc y o f the signal provided on clk m ust be at least 4.5 ti mes lower than clk_usart. figur e 26-3. baud rate generator 26.7.1 .1 baud rate i n asynch ronous mo de if the usart is programmed to operat e in asynchronou s mode, th e select e d clock is first divide d by cd, which is field programm ed in the ba ud ra te generator re gister (brg r). the resulting clock is p rovided to th e receiver as a sampling clock and then divided by 16 o r 8, dep e nding o n th e p rog ra mmin g of th e over bi t in mr . if over is s et to 1 , the receiver sampling is 8 times higher than the baud rate clock. if over i s cleared, the sampling is p erformed at 16 times th e bau d rate clock. th e following formul a performs the calculat ion of t he baud rate. 16-bit counter cd usclks cd clk_usart clk_usart/div re serv ed clk sync sync usclks = 3 fidi over sampling divider baudrate clock sampling clock 1 0 0 clk 0 1 2 3 >1 1 1 0 0 baudrate selectedclock 82 over ? ( )cd ( ) -------------------------------------------- = 32058k avr32-01/12 306 at32uc3a this gives a maximum baud ra t e of clk_usart divided by 8, assuming t hat clk_usar t is the hi ghest po ss ible cloc k a n d t ha t o v er is programme d at 1. 26.7.1 .2 baud rate calculatio n example table 26-2 on page 306 shows c alculat ions of cd to obta in a baud rat e at 38 400 bau ds f or dif- ferent source cl oc k frequen cies. th is ta ble also show s the act ual result ing bau d rat e and the error. th e bau d rate is calcul ated with the following formula: the bau d rate error is calcul at ed with th e following formula. it is not recommended to work with a n error higher tha n 5%. tabl e 26-2. baud ra te example (over = 0) sou r c e c lo ck expe cted baud rate calculation result cd actual baud r ate error mhz bit/s bit/s 3 686 4 00 38 400 6.00 6 38 40 0.00 0.00% 4 915 2 00 38 400 8.00 8 38 40 0.00 0.00% 5 000 0 00 38 400 8.14 8 39 06 2.50 1.70% 7 372 8 00 38 400 12.00 12 38 40 0.00 0.00% 8 000 0 00 38 400 13.02 13 38 46 1.54 0.16% 12 00 0 000 38 400 19.53 20 37 50 0.00 2.40% 12 28 8 000 38 400 20.00 20 38 40 0.00 0.00% 14 31 8 180 38 400 23.30 23 38 90 8.10 1.31% 14 74 5 600 38 400 24.00 24 38 40 0.00 0.00% 18 43 2 000 38 400 30.00 30 38 40 0.00 0.00% 24 00 0 000 38 400 39.06 39 38 46 1.54 0.16% 24 57 6 000 38 400 40.00 40 38 40 0.00 0.00% 25 00 0 000 38 400 40.69 40 38 10 9.76 0.76% 32 00 0 000 38 400 52.08 52 38 46 1.54 0.16% 32 76 8 000 38 400 53.33 53 38 64 1.51 0.63% 33 00 0 000 38 400 53.71 54 38 19 4.44 0.54% 40 00 0 000 38 400 65.10 65 38 46 1.54 0.16% 50 00 0 000 38 400 81.38 81 38 58 0.25 0.47% 60 00 0 000 38 400 97.66 98 38 26 5.31 0.35% 70 00 0 000 38 400 113.93 114 38 37 7.19 0.06% baudrate clkusart ( ) cd 16 ? = error 1 expectedb a udrat e actualbaudrate ----------------------------------- ----------------- ? ? ? ? ? = 32058k avr32-01/12 307 at32uc3a 26.7.1.3 fraction al baud rate in asynchrono us mode th e baud rate generato r prev iously defin ed is subject t o the fo llowin g l imitation : the output fre- quen cy changes by on ly integer multiples o f the reference frequency. an a pproach to this proble m is to integrat e a fractio nal n clo ck generator th at ha s a high resolution. t he generator architecture is mo dified to obta in baud rate change s by a fraction o f th e refer ence sour ce clock. this frac ti onal part is program med with the fp field in the baud ra te generator r egister (brgr). if fp is not 0 , the fractional part is activated. t he resolution is o ne eighth of th e clock divider. this featur e is only availabl e whe n using usart norma l mode. the fractional baud rate is calcu lat ed usin g th e following formula: th e mo di fie d archit ecture is p rese nte d bel ow: figur e 26-4. fractiona l ba ud rate generator 26.7.1 .4 baud rate i n synchr onous mod e or sp i mode if the usart is programmed t o opera te in synchronous mode , the selected clo ck is simply divid ed by the fi eld cd in brgr. in synchronous mode, if the externa l clock i s selected (usclks = 3), the c l ock is provided d irectly b y th e si gna l o n the u sa rt c lk p in. no divis ion is active. the value written in brgr baudrate selectedclock 82 over ? ( ) cd fp 8 ------- + ? ? ? ? ? ? ? ? ------------------------------------------------------- ----------- = usclks cd modulus control fp fp cd gli tch-free lo g ic 16-bit counter over fidi sync sampling divid er clk_usart clk_usart/div r eser ve d c lk clk baudra te clock sa mp ling clock sync usclks = 3 >1 1 2 3 0 0 1 0 1 1 0 0 baudrate selectedclock cd -------------------------------- ------- = 32058k avr32-01/12 308 at32uc3a has n o effect. t he extern al clock frequen cy must b e at least 4. 5 tim es lower than the system clock. when either t he external clock c lk or the intern al clock divided (clk_usart/di v) is selected, t he value programm ed in cd must b e even i f the us er has t o ensur e a 50:5 0 mark/space rati o on the clk pin. i f the in te rnal clock clk_usar t is selected, the baud rate generator ensures a 50:5 0 du ty cycle on th e clk pin, ev en i f the va lue programmed in cd is odd. 26.7.1.5 baud rate in is o 781 6 mode th e iso781 6 specificat ion defi nes th e bit rate wit h the followin g formula: where: ?b is th e bit rate ?di is t h e bit-rate adjustment factor ?fi is the cloc k fre quen cy divisio n fa ctor ?f is t h e iso781 6 clock frequen cy (hz) di is a bina ry value encoded on a 4-bit field, named di, as r epresented in tabl e 26-3 on page 308. fi is a bin ary value encoded on a 4-bit field, named fi , as represented i n table 26-4 on pag e 308. table 26- 5 on page 308 shows th e res u lti ng fi /di r a tio, which is the rati o betwe en t he is o7 816 clock and the baud rate clock. if th e usart is configured i n iso7816 mode, th e clock selected by the uscl ks field in the mode register (mr) is first divide d by the valu e progra mmed in the fi eld cd in the bau d rate b di fi ---- --- f u = tabl e 26-3. binary and de c imal values for di di fi eld 0001 00 10 00 11 0100 0 101 0110 10 00 1 001 di (decimal) 1 2 4 8 16 32 12 20 tabl e 26-4. binary and de c imal values for fi fi f ield 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (d ecimal 372 372 5 58 744 1 1 16 14 88 18 60 512 768 10 24 1 536 2 048 tabl e 26-5. possibl e va l ues fo r t he fi/ di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 2 3.25 3 4.87 46 .5 69.75 93 11 6.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4 32058k avr32-01/12 309 at32uc3a generator regist er (brgr). t h e resul ti n g clock can be provided to t he clk pin to feed the smart card clock i nput s. th is means that th e clko bit ca n be set in mr. th is clock is the n divide d by the value programme d in t he fi_di_ratio fi eld in th e fi_di_ratio register (fid i). th is is performe d by th e sampling divide r, whic h perfor ms a division by u p to 2047 in iso7816 mode. the non-intege r val ues o f the fi/d i ratio are not supporte d and the user mus t program th e f i_di_rati o fiel d to a valu e as cl o s e a s possib l e to th e expecte d value. the fi_d i _ratio field resets to t he value 0x1 74 ( 3 72 in decimal ) a nd is th e m ost c ommon divider between the iso7816 cloc k and th e bit rate ( fi = 372, di = 1). figure 26-5 on page 30 9 shows t he relation between the element ary time unit, corresponding to a bi t time, and the is o 78 16 clock. figur e 26-5. elementary ti me unit (etu) 26.7.2 receive r and transmitt e r contr ol aft er reset, the r eceiver is disabled . the use r must e nable the receive r by settin g the rxen bit in the co nt rol regist er (cr). however , t he rece iver regist ers can be programmed bef ore the receiver clock is e nabled. afte r reset , t he transmitte r is disabled. th e user mu st enable it by setting the t xen bit in the c ont rol r egi ste r ( cr) . how ever , th e tra nsmi tte r registe rs c a n b e pr ogramme d b ef ore b eing enabled. th e receive r and t he transmitter ca n b e enabled togethe r or independently. at any time , t he softwar e can perform a reset on the receiver or the transmitter of th e usart by sett ing the corresponding bit, rstrx and rst t x respectively, in the con t rol register (cr). th e softwar e rese ts clear th e stat us fla g an d rese t internal stat e ma ch ines bu t t he user interface configuration registers hold the va lue configur ed prior to software reset. regardless of what the receive r or the transmitte r is performing, th e communication is imm ediatel y stopped. th e user can als o indepe ndently disable th e receiv er or th e t r a nsmit ter by setti ng rx di s and txdis respec ti vely in cr. if the r eceiver is di sabled during a ch aracter receptio n, the usart waits u n til th e en d o f receptio n o f the curren t characte r, then the r eceptio n is stopped . if the transmitte r is disabl ed while it is operating, th e usart waits the en d o f transmission of both the cur rent character and character being stored in the tr ansmit holding register (thr). if a time- guar d is programm ed, it is handled norm ally. 1 etu fi_di_ratio iso7816 cloc k cycles iso 7816 clock on c lk is o7816 i/ o line on txd 32058k avr32-01/12 310 at32uc3a 26.7.3 synchronou s a nd asynchronous modes 26.7.3.1 transmitter operations the transmi tt er performs the same in both synchronous and asynchrono us operating modes (sync = 0 or sync = 1) . one start bit, up to 9 dat a bits , o ne o p tion al pa r ity bit a nd u p to two stop bits are succe ss ively shifted out on the txd pin at each falling edge of the programmed serial clock. th e number of dat a bi ts is selected by the chrl field and th e mode 9 bi t in the mode register (m r ). nin e bi ts ar e selecte d by settin g th e mode 9 b it regar d less of th e chrl f ield. t he pa rity bit is se t accordin g to the par field in mr. th e even , odd, space, mark ed o r none pari ty bit can be c onf igured. the msbf field in mr conf igures wh ich data bit is sent first. i f written at 1, th e most significant bit is s en t first. at 0 , the le ss significant bi t is sent first. th e number of sto p bits is selecte d by the n bsto p fiel d i n mr. the 1. 5 stop b i t is su pported i n a synchron ou s mod e o nl y. figur e 26-6. characte r transmit the characters are sen t by writin g in the tr ansmit holdin g register (thr ) . th e tr an sm itt er repor t s t wo st atus bi ts in th e chan nel s t at us r e gi st er ( csr) : t x r dy ( tr ansmi tte r r ead y), which indi ca tes that thr is empty and txempty, which indicate s that al l th e characte rs written in thr have bee n processed. when the curren t character processing is completed , th e last character writte n in thr is t ransferre d into th e shift registe r of the transmitte r and thr beco mes empty, th us txrdy rises. both tx rdy an d txempty bits ar e low when the transmitter is disabled. writing a characte r in thr wh il e txrdy is lo w has no effect an d th e writte n character is lost. figur e 26-7. transmitter status d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty 32058k avr32-01/12 311 at32uc3a 26.7.3.2 manchester encoder when the mancheste r encoder is in use, charac ters transmi t ted thr o ugh the usar t ar e encoded based on biphase ma nches ter i i for ma t. to e na ble th is mo de, set th e man fi el d in the mr regis ter t o 1. depending on polarity configura t ion, a logic level (zer o or one), is trans mitted as a co ded signa l one-to-zero or zero-to-one. thus, a t ransition always occurs a t the midpoint of each bit time . it consumes more bandwidth than t he origin al nrz signal (2x) bu t th e receiver has mor e error cont rol since t he expect ed input mu st show a change at the cent e r of a bit cell. an example of manchester encod ed sequence is: t h e byte 0xb1 o r 1011000 1 encodes t o 10 01 10 10 01 0 1 01 1 0, assuming th e defaul t polari ty of th e encoder. figure 26-8 on p ag e 311 illustrates th is coding scheme. figur e 26-8. nrz to manchester encoding the mancheste r encoded ch aract er can also be enca psulated by adding bot h a configurable preamble an d a start frame delimiter pattern. depend ing on t he configuration , th e preamble is a tr aining sequence, c ompose d of a pre-defined pattern wit h a pro gr a mmab l e leng t h fr om 1 to 15 bi t times. i f the preamb le lengt h is set to 0, th e preamble waveform is not generate d prior to any character. th e prea mble pattern is chosen amon g the following seque nces: all_one, all_zero, one_ze ro or zero_ one, writing the field tx_pp in the ma n register, the field tx_pl is used to configure t he preamble length. figur e 26-9 o n page 312 illust rates and defines the valid patterns. to improve fle xib ility, the encoding sc heme can be conf igured using the tx_mpol field in t he man register . if the tx_mpo l fiel d is set to zero (default), a lo gi c zero is encode d with a ze ro-to-one transition an d a lo gic on e is encoded with a one-to-zero transition. if t he tx _mpol fi eld is se t to o ne, a log i c on e is en code d wi t h a one-to -zer o tran sition a n d a logic zero is encode d wit h a zero-to-one transition. nrz encoded data manchester encoded data 1 0 1 1 0 0 0 1 txd 32058k avr32-01/12 312 at32uc3a figur e 26-9. preamble patterns, default polari ty assumed a st ar t frame delimiter is t o be configured using t he onebit fi eld in the mr register. it consists of a user-defined pattern that indicates the beginning of a v alid data. figur e 26-10 o n pag e 313 illustrates the s e pattern s. if the start frame delimiter, also kno w n as st art bit, is one bit, (one bit at 1), a logic z ero is ma nchest er encode d and indicate s that a new c haracte r is being sent seri- al ly on th e line . if the star t fram e delimiter is a sync hroniza tion pattern also ref erre d to as sync (onebi t at 0), a se quen ce of 3 bit tim es is sent seria lly on the line to indicate t he start of a new char acte r. th e sync wavefo rm is in it self an invalid mancheste r wave fo rm as t h e t r ansition occurs at the middle of the s econd bi t time. two distin ct sync patterns are used: the com mand sync and th e data sync. t he command sync has a lo gi c on e level fo r one and a half bit times, the n a transition to logic ze ro for th e secon d one a nd a ha lf bit time s. if the mods ync field in the m r re g iste r is s e t t o 1, th e next chara cte r is a comm and . if it is se t t o 0 , th e nex t c haract er is a data . when direct memo ry access is used, the modsync fi eld can b e imm ediately updated wit h a modified character locat ed in memory. t o enable t his mode, var_sync fiel d in mr reg- is te r mus t be se t t o 1 . in th is cas e , the modsync fi el d in m r is byp assed an d th e sy nc configu r atio n i s h el d in the txs ynh i n th e thr register. th e usa rt ch ar a cter f or mat i s mo di- fied and includes sy nc information. manchester encoded data txd sfd data 8 bit width "all_one" preamble manchester encoded data txd sfd data 8 bit width "all_zero" preamble manchester encoded data txd sfd data 8 bit width "zero_one" preamble manchester encoded data txd sfd data 8 bit width "one_zero" preamble 32058k avr32-01/12 313 at32uc3a figur e 26-10. star t frame delimiter 26.7.3.3 dr ift com pensa t ion drift compensation is ava i lable onl y in 16x oversampling mode. an ha rdware recovery system allows a larger clock drift. to enable the hardware system, the bit in t h e man register must be set . i f t he r xd edg e is o ne 16x c loc k c yc le fro m th e expe cte d edge , t hi s i s c onsider e d a s no r- mal jitt er a nd no correct ive actions is taken. if t he rxd even t i s bet ween 4 and 2 clo ck c yc les befo r e th e ex pe ct e d e dge , th en th e cu rre nt p erio d is s hortened by o n e cloc k cycle. if th e rxd event is between 2 and 3 clock cycles a fter the expected edge, then th e current period is le ngth- ene d by on e cloc k cycle. thes e inte rvals are consider ed t o be d rift an d so co rre ctive acti ons are automatically taken. figur e 26-11. bit resynchroni zation 26.7.3 .4 asynchronou s receiver if t he u sar t is p rogramme d in a sy n c hronous ope ratin g mod e ( sync = 0 ), th e receive r over- s am p le s t h e rx d input lin e . t h e o ver sam plin g is ei t he r 1 6 or 8 times th e baud r a te cl o ck, dependin g on the o ver bit in t he mo de register (mr). manchester encoded data txd sfd data one bit start frame delimiter preamble length is set to 0 manchester encoded data txd sfd data command sync start frame delimiter manchester encoded data txd sfd data data sync start frame delimiter rxd oversampling 16x clock sampling point expected edge tolerance synchro. jump sync jump synchro. error synchro. error 32058k avr32-01/12 314 at32uc3a the receiver samples th e rxd line. i f the line is sam pled during one half of a bi t time at 0, a start bit is detected an d data, parity a nd st op bits are su cc essively sampled on t he bit rate clock. if t he oversampling is 16, (over at 0), a star t is detected a t th e eighth samp le at 0. then , data bits, parity bit a nd stop bit ar e sampled on each 16 samp ling cloc k cycle. if th e oversampling is 8 (o ver at 1), a s tart bit is d etected at the fourt h sample at 0. then, data bits, parity bit a nd stop bit are sa mpled on each 8 sampling clock cycle. t he num ber of da t a bi ts , f i rst bi t s ent a n d pa rit y m o de a r e s ele cte d by th e same f ie ld s and bits as the transmitter, i.e. respectively chr l , mode9, msbf and par. fo r th e synchronization mechanism only, the number of stop bits h a s no effect on the receiver as it co nsider s only one sto p bi t, regardle ss of th e field nbstop, so that resynchronizatio n between the receiver an d the trans mitt er can o cc ur . mo r eove r , as s o on a s t he s top b it i s s am pled , t he r ece i ver st art s looking fo r a ne w st art bit so t hat resynchronizatio n can also be accomplished when t he transmitter is operating wit h one sto p bit. figure 26-12 on pag e 314 and figure 26-13 on page 314 illust rate start detection and characte r reception wh en usart operat es in asynchrono us mode. figur e 26-12. asynchronou s star t detection figur e 26-13. asynchronous character reception sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 0 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 32058k avr32-01/12 315 at32uc3a 26.7.3.5 manchester decoder when the man fiel d in mr r egister is se t t o 1 , t he manchester decode r is enabled. th e decoder perfor ms both pream ble and start fram e delimiter detection. one input line is dedicated t o man- cheste r encod ed input data. an op tional preambl e seque nce can be defined, it s lengt h is user-define d and to tally indepen- dent of the emi t ter side. use rx_pl in man regi ster to configure the length of the pr eamble sequence. if th e length is s e t t o 0, no preamble is detect ed and the function is disa bled. in addi- tio n, th e po larity of the i n put stre am is progr ammabl e wit h rx_mpol fi el d in ma n register. depending on the desired application t he preamble pattern matc hing is to be defined via the rx_pp f i eld in man . see figur e 26- 9 o n pag e 312 fo r availabl e preamb le patterns. unlike p reamble, t he star t fram e delimiter is sha re d between manchester encode r an d decoder. so, if onebit fiel d is set to 1, only a zero encoded manchest er ca n be detected as a vali d start fr am e del i mit er . i f o ne bit is se t to 0, only a sync pattern is detected as a valid star t f rame delimite r . d ecoder operate s b y de tecting transitio n on incoming stream. if rxd is sam p led dur- ing one quarte r of a bi t time at zero , a star t bit is detected. see figur e 26-1 4 o n page 315.. th e sample pul s e reject ion mechanism applies. figur e 26-14. asyn chron ou s star t bit d etection th e receiver is ac tivated a nd star ts preamb le an d frame delimiter detection , sampling th e data at on e quarte r an d then thre e quarters. if a val id preamble pattern or start fram e delimiter is detected, th e receiver continue s decodin g with th e sa me synchronization. if th e stream does not match a valid pattern or a valid start frame delimiter, the rec e iver re-synch ronizes on th e next vali d e dg e.t he mi ni mu m tim e thre shol d to esti m ate th e bit value is t hre e quarters of a b it ti me. if a valid preamble (i f us ed) followed with a valid start frame delimiter is detected , t he incomin g stre am is decoded into nrz dat a an d passed to usart fo r processing. figur e 26-1 5 o n page 316 ill ustr a tes manc hest e r patt er n mi smatch. wh en incoming dat a stream is pas s ed to the usar t, the receiver is also able to detect manchester code violation. a co de violatio n is a lack of tran s iti on in t he mi ddle of a b it cell. in thi s case, ma ne flag in csr register is ra ised. it is cleared by w riting t he contro l register (cr) wit h th e rststa bi t at 1. see figur e 26-1 6 on page 316 for a n exampl e of manchester erro r detectio n durin g dat a phase. manchester encoded data txd 1 2 3 4 sampling clock (16 x) start detection 32058k avr32-01/12 316 at32uc3a figur e 26-15. preamble pattern mismatch figur e 26-16. manchester erro r flag when th e star t fr am e deli mite r is a s ync pat t e rn ( o neb it f ield at 0) , bot h co mman d a nd data delimite r are supported. if a v a lid sync is de tected, th e received charact er is writt en as rxchr field in the rhr regis t er and t he rxsynh is updated. rxchr is se t t o 1 when the receive d character is a command, and it is set to 0 i f the received ch aracter is a data . this mechanis m alleviat es and simplifies th e direct memo ry access as t he cha racter cont ains its own sync field in the same regis t er. as the decode r is setup to b e used in unipolar mode , the first bi t o f the frame has t o be a zero-to- one transition. 26.7.3.6 radi o interface: manchester encoded usar t application th is sectio n describe s low data rate rf t ran smission syste ms and their integrat ion wit h a man- chester encoded usart. these system s ar e base d on transmitter and receiver ics that support ask and fsk modulation schemes. th e go al is to perform full dupl ex ra dio transmission of characters using tw o differen t frequency carriers. see the co nfiguration in figur e 26- 17 on pag e 317. manchester encoded data txd sfd data preamble length is set to 8 preamble mismatch invalid pattern preamble mismatch manchester coding error manchester encoded data txd sfd preamble length is set to 4 elementary character bit time manchester coding error detected sampling points preamble subpacket and start frame delimiter were successfully decoded entering usart character area 32058k avr32-01/12 317 at32uc3a figur e 26-17. manchester encode d charact ers rf transmission th e usart m odule is con fig ure d as a m ancheste r encod e r/deco der. l ookin g at th e down- strea m communication channel, mancheste r enco ded ch aracters are serially se nt to t he rf emitter. this ma y also includ e a use r define d preambl e and a st art fra me delimiter. mostly, pre- ambl e is used in the rf receiver to distinguish b etwee n a valid data from a transmitter a nd signal s du e to noise. th e manchester stream is the n modulated . see figur e 26-18 on page 317 for an e x ample o f ask mo dula tion sc hem e. when a l ogic one is sent to the ask modulator, th e powe r a m plifier, re fe rr ed to as pa, is e n able d and tr an smi t s an rf signa l at downst rea m f r e- quency. whe n a logic z e ro is tra n smit te d, th e rf sig n al is tur ned off. i f th e fsk mod u lato r i s acti va ted , tw o dif fere nt fre que ncies ar e used t o tr ansmit data . when a logic 1 is sen t, t he modu- lator outpu ts an rf si g nal at frequen cy f0 and swit ches to f1 if th e dat a sent is a 0 . see figure 26-1 9 o n pag e 318. from t he rece iver side, another carrie r frequency is use d. th e rf receiver performs a b i t check operat ion examinin g demodulat ed data stream . if a valid p atter n is detect ed, the receiver switches to receiving mode. th e demodulated stream is sent to th e manchester decoder. becaus e of bi t checking inside rf ic , the data transferred to t he microcontrolle r is reduc ed b y a user-defined numbe r of bits. th e manchester preamble length is to b e defined in acco rdance with th e rf ic configuration. figur e 26-18. ask modulator output lna vco rf filter demod control bi-dir line pa rf filter mod vco control manchester decoder manchester encoder usart receiver usart emitter ask/fsk upstream receiver ask/fsk downstream transmitter upstream emitter downstream receiver serial configuration interface fup frequency carrier fdown frequency carrier manchester encoded data default polarity unipolar output txd ask modulator output uptstream frequency f0 nrz stream 1 0 0 1 32058k avr32-01/12 318 at32uc3a figur e 26-19. fsk mo dulato r output 26.7.4 syn chro nou s re ce iver i n synchronou s mode (s ync = 1), the receive r samples t he rxd signal o n each rising edg e of t he ba ud rate clock. if a lo w leve l is detected, it is considered as a st art. all data bits, th e parity bit and the stop bi ts ar e sample d and the receiver waits for the ne xt start bit. synchronous mode operations provid e a high speed transfer capability. configuration fields an d bits are the same as in asy nchronous mode. figur e 26-2 0 o n pa ge 31 8 illustrates a chara c ter rece ption in synch ronous mode. figur e 26-20. synchrono us mode characte r reception 26.7.4.1 receiver operations wh en a characte r rece ption is complet ed, it is transferr ed to the receive holding registe r (rhr) and the rxrdy bit in the s t atus register (csr) rises. if a character is completed while the rxrdy is s e t, the ov re (ove rrun error) bi t is set. th e last char acter is transferr ed into rhr a n d ov e rwrite s t he previou s one . t he o vr e bit is cleared by wri t ing the control register (cr) wit h th e rststa (reset status ) bit at 1. manchester encoded data default polarity unipolar output txd fsk modulator output uptstream frequencies [f0, f0+offset] nrz stream 1 0 0 1 d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock 32058k avr32-01/12 319 at32uc3a figur e 26-21. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre start d0 d1 d2 d3 d4 d5 d6 d7 bit parity bit stop bit rststa = 1 read us_rhr 32058k avr32-01/12 320 at32uc3a 26.7.4.2 parity th e usart supports five parity mode s selected by programmin g the par fiel d i n the mode register (mr). t he par field also enable s th e multid rop mo de, see ?multidr op mo de? on page 321. eve n an d od d pari ty bit generati on an d erro r detectio n are supported. if even parity is sel ected , the parity generator o f t he trans mitte r dr ives th e pari ty bit at 0 i f a n um- ber of 1s in the character data bi t is even, and at 1 if the numb e r of 1s is od d. accordingly, the receive r pari ty checke r counts the number of received 1s and report s a parity error i f the sam- pled parity bit does not correspond . if odd pari ty is selected, th e parity generator o f the transmitte r drives th e parity bit a t 1 if a nu mber o f 1s in t h e character data bit is even , an d at 0 if t he number of 1s is odd. accordingly, the receiver parity ch ecker counts t he number of received 1s an d report s a parity error if the sampled pari ty bi t does no t correspond . i f the mark pa rity is used , th e pa rity generato r o f th e transmitte r drives the parity bit at 1 fo r a l l characte rs. the receiver pa rity checke r reports an error if t h e pa rity bit is sampled at 0. if t h e space pa rity is used , th e pa rity generato r o f th e transmitte r drives the parity bit at 0 fo r a l l characte rs. the receiver pari t y ch ecker reports an error if the parit y bit is sampled at 1. if parity is disa bled, the transmitte r does not generat e an y parity bit and the receive r does not report any parity error. table 26-6 on page 320 shows a n example o f the parity bi t for the character 0x41 (character ascii ?a? ) depe n din g on t h e confi gu rati on of th e usart. b ecau se th er e are tw o bit s at 1, 1 bi t is adde d when a p ari ty is odd, or 0 is ad ded whe n a parity is eve n . w he n th e receive r detects a pa rity error, it sets th e pa re ( pa rity e rror ) b it in th e cha nnel s tat us register (csr). the pare bi t ca n be cleare d by writing the contro l register (cr) with the rst- sta bit at 1. figur e 26-2 2 o n pa ge 32 1 illustrates the par i ty bit status sett ing a n d c lea ring. tabl e 26-6. parity bit examples chara cter hexa bina ry p arity bit p arity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none 32058k avr32-01/12 321 at32uc3a figur e 26-22. parity error 26.7.4.3 multidro p mode if th e par fiel d in the mo de registe r (m r) is programm ed to the value 0x 6 or 0x07 , th e usart runs in multidro p mo de. this mo de differentia tes the dat a char acters and th e address charac- ters. data is transmitte d with the parity bit at 0 and addr esses are transmitt ed with the parity bit at 1. if the usart is configu r ed in mult idrop mode, the r eceiver sets the pare parity erro r b it when t he parity bi t is hi gh an d th e transmitter is a b le to sen d a characte r with th e parity bit hi gh when the control regis t er is w ritt en wit h t he s e nd a b i t a t 1. t o ha ndle pa rit y e rr or, th e pa r e bit i s c le a red wh en th e con tro l r egi ste r i s w ritten with the bit rststa at 1. th e transmitter send s an addre ss byt e (par ity bit set) when senda is writte n to cr . in thi s case, the next byte written to thr is transmitte d as an address. any c haracte r written in thr wi thout hav i n g writte n th e com ma nd se nda is tran smitte d normall y wi th th e parit y a t 0. 26.7.4.4 t ransmitte r timegu ard th e timeguar d featur e enables the usar t interface wit h slow remote devices. the timeguard function enables the transmitter to insert an id le state on the txd l ine between two characters. th is idle stat e actu ally ac ts as a long st op bit. th e duration of th e id le stat e is programmed in the tg field of th e transmitter timeguard regis- ter ( t tgr). when this field is progr a mmed at zero no ti m eguard is g enerated. otherwise, th e transmitter holds a high level on txd a f ter each transmitte d byte durin g the num ber of bit peri- ods programme d in tg in addition to th e numbe r of st op bits. as illu st rated in figur e 26-23 on p ag e 322, th e behavior of tx rdy and txem pty stat us bits is modified by th e programmin g o f a timeguard. tx rdy rises on ly when the star t bit of th e next character is se nt, and thus remains at 0 during the timeguard tr ansmission if a character has bee n writt en in thr. txempty re mains low un til th e timeguard transmission is c omplete d as the timeguar d is par t of th e current characte r being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1 32058k avr32-01/12 322 at32uc3a figur e 26-23. tim eguar d op erations ta ble 26- 7 on page 322 indicate s the maximum length of a timeguard period that the transmitter can h andl e i n re latio n to the func tio n o f t h e ba ud rat e. 26.7.4 .5 receiver time-out the rece ive r ti m e-ou t provide s sup p ort i n ha ndlin g variable-lengt h frames. th is f eatur e de tects an idle condition on th e rxd lin e. when a ti me-out is detected , the bit timeout in t h e channel statu s r eg iste r ( csr ) ri ses an d can generat e an interr upt , th us in dica tin g to th e dri ve r a n en d of fra me . the ti me -out delay period (dur ing which the receiver waits for a new ch aracter ) is programmed in t he to fi eld of th e receive r time-out registe r (rtor) . if th e to fiel d is programme d at 0 , the receiver time-out is disabled and no time-out is d etected . the timeou t bit in csr remains at 0. otherwise, th e receiver load s a 16-b it counte r with th e va lue programmed in to. th is counter i s de c rem ente d a t each bi t pe r iod a nd r eloa d ed ea c h t im e a n e w c h a ract er is r eceived . i f the counter reache s 0, th e timeou t bit in th e stat us registe r rise s. then, th e user ca n either: ? stop t he counter cloc k un til a ne w character is received . th is is performed by writing the contro l registe r (cr) with t he sttto (start time-out ) bi t at 1. in th is case, t he idle stat e on rxd befo re a new char acter is receiv ed will not prov ide a time-out. this prev ents ha ving to d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 tabl e 26-7. maxim um timeguar d lengt h dependin g on ba ud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 1152 00 8.7 2.21 32058k avr32-01/12 323 at32uc3a hand le an interrupt before a c haracte r is received an d allows waiting for t he next idle stat e on rxd after a f r ame is received. ? o btain an interrupt wh ile no char acter is receiv ed. this is performed by writing cr wi th the rett o (reloa d a nd start time- ou t) bit at 1. if retto is per for med , the coun ter starts counti ng do wn immediately from the value to . th is enab les generatio n of a peri odic interrupt so t ha t a use r time- out can be h and led, fo r exam ple when no ke y is p ress e d o n a keyb oard. if sttt o is performed , t he counter clock is st opped unt il a first characte r is received. the idle state on rxd before the start o f the frame doe s not provid e a time-out. this p revents having to obtai n a pe r iodic inte rrupt a n d enables a wait o f th e en d of fram e when th e idle sta t e on rx d is detected. if rett o is performed , t he counter starts counti ng down immediately from the value to. this en ables generatio n of a p eriod ic interrup t so that a user time-o ut can be h andled, for example wh en no key is p r essed on a ke yboa rd. figur e 26-2 4 o n pa ge 323 shows th e block diagram o f the receiver time-ou t feature. figur e 26-24. rece iver ti m e-out b l oc k diagram ta ble 26- 8 o n pa ge 323 g ives th e maximu m time-out perio d fo r s o me standard ba ud rat es . 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto d q 1 clear tabl e 26-8. maximu m time-out perio d baud rate bi t time time-out bit/sec s ms 600 1 667 109 2 25 1 200 833 5 4 613 2 400 417 2 7 306 4 800 208 1 3 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 32058k avr32-01/12 324 at32uc3a 26.7.4.6 fra m ing err or the receiver is ca pable of detecting fram ing errors. a framing erro r happen s when the stop bi t of a received characte r is detected at level 0. th is can occu r if th e receiver and the transmitte r are fully desynchronized. a fra m ing error is reported on the frame bit of the ch a nnel status register (csr). the fr ame bit is asserted in th e middl e o f th e stop bi t as so on as th e framin g erro r is detected . it is cleare d by writin g th e contro l register (cr) with t he rststa bit at 1. figur e 26-25. framin g error status 26.7.4.7 transmit break th e user ca n request the transmitter to generate a b r eak condit ion on th e txd line. a br ea k con- ditio n drives t he txd line low du ring at least one c omplete character. it appears t he same as a 0x0 0 chara c ter s ent w i th t h e pari ty a n d t h e s to p bit s at 0. h o wever, th e tran smitt e r hold s the txd lin e a t least durin g one characte r until the user request s th e brea k condition t o be removed. a b rea k is transmitte d by writing t he cont rol register (cr) with th e sttbrk bit at 1. th is ca n be performed at any time, either wh ile th e transmitter is em pt y (n o characte r in either th e shift reg- ister or in thr) or when a ch aracter is b eing transmitted . if a b reak is requeste d while a character is b e ing shift ed out, t he character is fi rs t complete d be fore the txd line is held low. once sttbrk com m and is requested further st tbrk commands are ignore d until the end of the brea k is completed. the break condi ti on is re moved by writing cr with the st pbrk bit at 1. i f the stpbrk is request ed before the end of the minim um break duration ( one character, including s tar t, data, pa rity and st op bits) , the tran smitt e r e nsur es that t he br ea k cond it ion com plete s. t he transmitte r consider s the brea k as though it is a c haracter , i. e. th e sttb rk and stpbrk comman ds are take n in to a ccoun t on ly i f the txrdy bit in csr is at 1 and t h e start of the break condit ion clears th e txrdy an d txempty bits as if a character is p rocessed. writ ing cr with t he bot h sttb rk and stp b r k bits at 1 ca n lead to an unpredictable result. all stpbrk comm and s requested without a p revious sttbrk com mand ar e ignored. a byt e writ- ten into the transmit holding r egister while a b rea k is pe ndin g, b u t n o t sta rted , is ig nore d. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1 32058k avr32-01/12 325 at32uc3a after th e brea k condition , the transmitte r return s the tx d line to 1 f or a m ini mum o f 12 bit ti mes. thus, the transmitter ensures that the remot e receiver detect s correctl y th e en d of break and the start o f the n ext character. i f the timeguard is p rogrammed wit h a value higher than 12, th e txd line is hel d high for the timeguard period. afte r ho lding th e txd lin e for this per io d, the tr ansmitte r r esum e s norm al op eration s. figur e 26-2 6 on pa ge 325 illustrate s the effect of both the start break (sttbr k ) and stop break (stpbrk) commands on t he txd line. figur e 26-26. break transmission 26.7.4 .8 receiv e break t he rece iver de tects a brea k cond ition when all da ta, parity and stop bits ar e low. th is corre- spon ds t o detect ing a framin g error with data at 0x00, but frame rema ins low. when th e low stop bit is detecte d, the re ceiver asserts the rxbrk bit in csr. this bit may be cleare d by writin g th e contro l register (cr) with t he bit rststa at 1. an en d o f r eceive break is detected by a high lev el f or at le ast 2/1 6 of a bit period in asynchro- nous opera t ing mode or one sample at high level in synchr onous operating mode. the end of brea k detectio n also assert s th e rxbrk bit. 26.7.4.9 hardware handshaking t he usar t feature s a hardwar e h and shakin g o ut-of- b an d flo w contro l. th e rts a n d ct s pins ar e used to connect with th e remote device, as shown in figur e 26- 27 o n pag e 325. figur e 26-27. connecti on wit h a remote device f o r hardware handshaking d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break usart txd cts remote device rxd txd rxd rts rts cts 32058k avr32-01/12 326 at32uc3a setting the usart to operat e with hardware handshakin g is performed by w riti ng the mode field in the mode register (mr) to th e value 0x2. th e usart behavio r whe n hardware handshakin g is enable d is th e same as the behavior in standard synchrono us or asynchrono us mode, ex cept tha t the re ceiver drives the rts pin as descri bed b elow and th e level on the cts pin modifies th e beh avior of the transmit t er as described below. using this mode requires using the pdc cha nnel fo r reception. the transmitter c an handl e h ardware handshaking i n a n y case. figur e 26-2 8 on page 326 shows how the receiver operat es if hardware handshakin g is enabled. the rts pin i s driven high if the receiver is disabled and if t h e status rxbuff (r eceive buffer fu ll) coming from the pdc c hann el is high. normally , th e remote de vice do es not start transmit- ting while its cts pin (driven b y rts) is high. a s soo n as t h e receiver is ena bled , the rt s falls, indicatin g to the remot e device that it can start trans mi tting. definin g a new buffer to the pd c clears th e stat us bit rxbuff and, as a r esult, asserts th e pi n rts low. figur e 26-28. receiver behavior when operatin g with hardware handshaking figure 26 - 29 on page 326 shows how t he transmitt er operate s if hardware ha ndshaking is enabled. th e cts pin disabl es the transmitter . if a character is being processing , t he transmitter is dis abled only after the completion of t he curren t cha r acte r an d transmissio n o f th e next cha r- acte r happen s as soo n as th e pi n cts falls. figur e 26-29. transmitter behavio r when operating with hardware handshaking 26.7 .5 iso7816 mode the usart features a n iso7816-compat ible operating mode. this mode permits interfacing with smar t card s an d security access modu les (sam) communicating through an iso781 6 link. both t = 0 a nd t = 1 p rot ocols defined by t h e iso781 6 specificat ion ar e supported. setti ng th e usart in iso78 16 mode is performed by writing t he mode field in t he mode regis- te r (mr) to the valu e 0x4 fo r protocol t = 0 a n d to th e valu e 0x5 fo r protoc ol t = 1. 26.7.5.1 iso7816 mode overview the iso781 6 is a hal f duplex communic ati on on only one bidirection al line. the b aud rate is determined by a division o f t he clo ck provided to th e remot e device (see ?ba ud rate generator? o n pag e 305). th e usart connects to a smart card as sh ow n in figur e 26-30 on page 327 . th e txd l ine b e comes bidir e ct iona l a n d t h e b au d ra t e gene r a to r feed s t he iso 78 1 6 clo ck o n th e cl k pi n. rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd 32058k avr32-01/12 327 at32uc3a as the tx d pi n becomes bidirectiona l, it s output remain s dr iven by t he output o f the transmitter bu t on ly whe n t he t ra nsmitt er is acti ve w h ile its in put is directe d t o t he inpu t o f th e receiver . the usart is c onsidered as th e master of t he communi catio n a s it generate s th e clock. figur e 26-30. con necti on of a sma rt card t o th e usart when oper at ing in iso7816 , e ither in t = 0 or t = 1 m o des , t he chara cte r format is fixed. th e configurat ion is 8 da ta bits , ev en parity and 1 o r 2 stop bits, regardle ss of th e values pro- grammed in t he chrl, mode9, par and chmode fields. msbf ca n b e used to transmit lsb or msb fi rs t. pa rity bit (par) can be used to tr ansmit in n ormal o r inverse mode. refer t o ?u sart mode register ? o n p ag e 343 and ?par : pa rity type ? o n p a ge 3 45. t h e us a rt c ann o t o perate con curre n tly in both receive r a nd tran smitt e r m o de s as the commu- nica tion is unidirecti onal at a time. it has t o be configured according t o the required m ode by enabling or disablin g either the receiver or t he transmitter as desired. enabling both the receiver and the transmitte r at th e same time in iso7816 mod e may lead t o unpredictabl e results. the iso7816 specificatio n defines an inverse transmission format . data bits of the character mu st be tran smitt ed o n th e i/ o lin e a t thei r ne ga tive value. t he usart d oes no t suppor t th is f or- mat a nd the user has to perform an exclusive or on the data before writ ing it in the tra nsmit hold ing registe r ( thr) or afte r read ing it in th e rece ive holdin g register (rhr). 26.7.5 .2 protocol t = 0 in t = 0 prot oc ol, a character is made up of one sta rt bit, eight dat a bits , one parity bit and one guard time , which last s two bit times. the transmitter shifts ou t the bi ts and does not drive the i/o li ne durin g th e guar d time. if no pari t y err or is detected, the i /o line remains at 1 during t he guar d time and t he transmitter can co ntinue with the transmission of th e ne xt character, as show n in figur e 26-3 1 on pag e 328. if a parity error is detecte d by the rece iver, it drives the i/o line at 0 d u ring the guard ti me, as sh own in figure 26 - 32 on page 328. this err o r bit is also named nack, fo r non acknowledg e. in this c a se, the char acter lasts 1 bi t time mo re, as the gu ard time leng th is the same and is added to the error bi t t im e whic h lasts 1 bi t tim e . when the usart is t he receiver an d it detect s an error, it do es no t load the erroneo us character in the receive holding register (rhr). it appropriat ely sets t he pare bi t in the stat us register (s r) so that the softwar e ca n handle th e error. clk txd usart clk i/o smart card 32058k avr32-01/12 328 at32uc3a figur e 26-31. t = 0 prot ocol withou t parity error figur e 26-32. t = 0 prot ocol wit h parity error 26.7.5 .3 receiv e error counter th e usart receiver also records the total number of errors. this c a n be rea d in t he number of erro r (ner) register. the nb_errors fi eld ca n recor d up t o 255 err ors. read ing ner auto- matically clears the nb_errors field. 26.7.5 .4 receiv e nack inhibit th e usart can also be co nfigured to inhibit an error. th is can be achieved by setting the inack bit in t he mode register (mr) . if in ack is at 1, no e rro r signal is d riven on t he i/o line even i f a pa rit y bit is detecte d, but the in ack bit is set in th e stat us registe r (s r). the inack bit can be cleare d by writing the contro l register (cr) wi th th e rstnack bit at 1. moreover , i f in ack is set , t he erroneous receiv ed characte r is stored in t he receive holding register, as if no erro r occurred. however , th e rxrdy bi t do es not raise. 26.7.5.5 transmit character repetition when the usart is tr ansmittin g a charac ter an d gets a nack, it can automa tically repea t the charac ter bef ore m ov ing on t o t he ne x t one . r epetit ion i s e n abled by writi n g t he max_ i teratio n fi el d i n th e mo de regi ster (mr) at a valu e hi gher tha n 0. eac h char acte r can be transmitte d up to eight time s; the first transmission plus seven repetitions. if max_iteration do e s no t eq ual zero, th e u sa rt r epe a ts th e ch a ract e r a s man y t ime s as t he valu e loa de d i n m ax_i terat ion . when th e usart repetition number reac hes max_iteration, the iteration bi t is se t in the channe l stat us register (c sr). if th e repe tition of th e character is ack nowledged by the receiver, the repetitions are stoppe d and the iteration counter is cle ared. the it eratio n bit in csr can be clea red by w r iting the contro l regist er with t he rsi t bit at 1. 26.7.5.6 disab le successive receiv e nack the receive r can limi t t he nu mb er of successive na cks se nt b ack t o t h e remot e tr ansmitt e r. th is is programmed by se tti ng th e bit dsnack in t h e mod e register (mr). t he maximum num- ber o f nack transmitt ed is progr ammed in t he max_iteration field. as soon as d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition 32058k avr32-01/12 329 at32uc3a max_iteratio n is reached , t he characte r is considered as co rrect, an acknowledge is s ent on t he lin e and th e iteratio n bit in th e chan nel stat us register is s et. 26.7.5 .7 protocol t = 1 whe n operating in iso78 1 6 protoc ol t = 1, th e transmi ssion is similar to an asynchronou s for- ma t wit h onl y one sto p bit. t he pa r ity is generate d when transmitt ing an d ch ecked when receiving. parity erro r detection sets th e par e bit in t he channe l stat us registe r (csr). 26.7.6 irda mode t he usart features an irda m o de supplying half-duplex point-to-point wire less communica- tion. it em beds th e modulator a nd demodulat or whic h allo ws a glueless connect ion to the infrared transceivers , as show n in figure 26-33 on page 329. the modulator an d demodulator ar e compliant with the ir da specificatio n vers ion 1. 1 an d suppor t data transfer spee ds ranging fro m 2.4 kb/s t o 115 .2 kb/s. the usart i rda mode is ena bled by sett ing th e mo de field in t he mode register (mr) to th e value 0x 8. th e ir da filter register (ifr ) allo ws configuring t he demodulator filter. t he usart transmitter and receiver operate in a norm al asynchron ous mode and a ll parameters are acces- sible. no te that th e mo dulato r an d th e de modulato r ar e activa te d. figur e 26-33. con nection to irda transceivers t h e rece iv e r and th e tra ns m i tte r m ust be ena ble d or disabled acc ording to th e dire ction of the transmission to be m ana ged . 26 .7 .6.1 ir da m odu lation fo r baud rate s up to a nd including 115.2 kbits/sec , t he rzi modulati on schem e is used. ?0 ? is represent e d by a light puls e o f 3/16t h o f a b it time. so me examples of signal p ulse duratio n are shown in tabl e 26- 9 o n pag e 329. irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter tabl e 26-9. irda pul se duration baud r ate puls e dura tion (3/16) 2.4 kb/s 78.1 3 s 9.6 kb/s 19.5 3 s 19 .2 kb/s 9.77 s 32058k avr32-01/12 330 at32uc3a figur e 26-3 4 o n pa ge 33 0 shows an exam ple of char acte r tran smission. figur e 26-34. irda modulation 26 .7 .6.2 ir da ba ud rate table 26-1 0 o n page 330 gi ves some exampl es of cd values , bau d ra te erro r an d pulse dura- tion. not e tha t th e requirem ent on th e ma ximum acceptabl e erro r of 1 .8 7% mu st b e m e t. 38 .4 kb/s 4.88 s 57 .6 kb/s 3.26 s 115.2 kb/s 1.63 s tabl e 26-9. irda pul se duration baud r ate puls e dura tion (3/16) bit period 3 bit period 16 start bit data bits stop bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd tabl e 26-10. ir da baud rate error peripheral clock bau d rate cd baud r ate error pulse time 3 68 6 4 00 1 15 200 2 0 . 00% 1. 63 20 00 0 000 1 15 200 11 1.38% 1.63 32 76 8 000 1 15 200 18 1.25% 1.63 40 00 0 000 1 15 200 22 1.38% 1.63 3 6 8 6 4 00 5 7 6 00 4 0 . 00% 3. 26 20 00 0 000 5 7 600 22 1.38% 3.26 32 76 8 000 5 7 600 36 1.25% 3.26 40 00 0 000 5 7 600 43 0.93% 3.26 3 6 8 6 4 00 3 8 4 00 6 0. 00% 4. 88 20 00 0 000 3 8 400 33 1.38% 4.88 32 76 8 000 3 8 400 53 0.63% 4.88 40 00 0 000 3 8 400 65 0.16% 4.88 3 68 6 4 00 1 9 200 12 0.00% 9.77 20 00 0 000 1 9 200 65 0.16% 9.77 32 76 8 000 1 9 200 107 0.31% 9.77 40 00 0 000 1 9 200 130 0.16% 9.77 32058k avr32-01/12 331 at32uc3a 26.7.6.3 ir da d emod ulator the demodulator is ba sed on the irda receive filter c omprised of an 8-bit do wn counter which is loa ded with th e va lue programme d in i fr. when a f allin g ed ge is detecte d on t he rxd pin , the filter c ou nter st arts counting dow n at th e clk_usar t s peed. if a risin g ed g e i s de tec ted on th e rxd pin, t he count er stop s and is reloa d ed with ifr. if no rising e dge is detecte d whe n the counter reaches 0, the input of th e receiver is driven low duri ng on e bit time. figur e 26-3 5 o n pa ge 33 1 illustrates the operation s o f t he ird a dem o dula tor. figur e 26-35. irda dem od ulato r o pe r ations as the ir da mode uses the same logic as t he iso7816, note that the fi_di_ratio field in fidi must be set t o a va lue higher tha n 0 i n order to assure ir da communicat ions operate correctly. 3 68 6 4 00 9 600 24 0.00% 19.53 20 00 0 000 9 600 130 0.16% 19.53 32 76 8 000 9 600 213 0.16% 19.53 40 00 0 000 9 600 260 0.16% 19.53 3 68 6 4 00 2 400 96 0.00% 78.13 20 00 0 000 2 400 521 0.03% 78.13 32 76 8 000 2 400 853 0.04% 78.13 tabl e 26-10. irda baud rate error (continued) peripheral clock bau d rate cd baud r ate error pulse time clk_us art rxd counter value receiver input 6 5 4 6 3 puls e rejected 2 6 4 5 3 2 1 0 pulse accepted driven low durin g 16 baud ra te clock cycles 32058k avr32-01/12 332 at32uc3a 26.7.7 rs4 85 mo de the usart featur es the rs485 mode to enable li ne driver control. while oper ating in rs485 mode, th e usart beh aves as though i n asynchronou s or synchron ous mod e and configuration of all t he parameter s is possible. the differenc e is tha t t he rts pin is driven high when the transmitte r is operating. t he behavior of th e rts pi n is controlle d by th e txempty bit. a typical connecti on of t he usart to a rs48 5 b u s is shown in figur e 26-3 6 on pag e 332. figur e 26-36. typical co nnection to a rs48 5 bus the usart is se t in rs485 mode by programming t h e mode fiel d in the mode registe r (mr) to the valu e 0x1. the rts pi n is a t a level inverse to t he txempty bit. significantly, t he rts pin re mains high when a timeguar d is programmed so tha t th e line ca n remain driven after the last ch aracter com- pletion. figure 26-37 on page 33 2 gives an exa mple of th e rts waveform du ring a character tra nsmi ssi o n w he n the time guard is e na bl ed. figur e 26-37. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts 32058k avr32-01/12 333 at32uc3a 26.7.8 spi mode th e se ri al pe riphe ral i nter fac e (spi ) mo de is a synch r onou s serial da t a link th at pr ovide s com- munica tion with extern al device s in maste r or slave mode . it also enable s communication betwe en processors if an external processor is con nected to th e system. t he serial periph eral interface is esse n tially a shift regi ster tha t se rially transm its da ta bits to othe r spi s. during a data transfer, one spi system acts as the ?master? which c ontrols the data flow, while th e othe r de vices act as ?sla ves'' whic h hav e dat a shifte d int o an d ou t by t he master. different cpus ca n ta ke turn s being mast ers and on e mast er may simultane ously shift data into mu ltiple slaves. (multiple ma ster protoc ol is th e opp osite of single ma ster protoc ol, wh ere one cp u is a lw a ys th e m a ster while all o f t he others are alwa y s sla ves .) howev er, onl y one slave ma y dr ive its outpu t to writ e data ba ck to the master at an y give n time. a slav e device is s elected when its nss sig n al is asse rted by the ma ster. the usart in sp i master mod e ca n addr ess only o ne spi slave because it ca n generat e only o ne nss signal. th e spi syst em consists of tw o data lines an d two contro l lines: ? master out slav e in (mosi): this data line supplie s th e outpu t data from th e master shifted into th e input of the slave. ? master i n s la v e o u t (miso) : this data line suppli es t he o utput data fr o m a sl a v e t o th e inp ut of t he master. ? ser ial clock (c lk): this control line is driven by t he maste r and regulates th e flow of the data bits. th e maste r may transm it dat a at a variet y of baud rates. t he clk line cycle s once for each bi t that is transmitted. ? slave se lect (nss ): this control line allows t he maste r to se lect or deselect t he slave. 26.7.8.1 mo des of operation th e usart can o per at e in m aste r mo de or i n slav e mod e. operat ion in spi mast er m o d e is p rogra mme d b y writin g at 0x e th e mo de fie l d i n th e mod e regist er . in th is cas e th e spi lines must be connect ed as describe d below: ? t h e mos i line is driven b y th e ou tpu t pi n txd ? t he mi so line driv es th e input pi n rxd ? t he clk line is d riven by th e output pi n clk ? t he nss lin e is driven by th e output pin rts ope ratio n in spi slave mo de is p r og ramm ed by writ ing at 0xf th e mo de fi eld in t he mod e re g- ister. in th is case t he spi lines mu st be connected as described below: ? t he mo si line driv es th e input pi n rxd ? t h e mi so li ne is drive n b y t h e ou tpu t pi n txd ? t he clk lin e drives the inpu t pin clk ? t he nss lin e drives t he input pin cts in orde r to av oid unpr edic t ed beh avio r, an y c han ge o f the spi mo de mus t b e fo llowe d by a sof t- ware reset o f the transmitter and of the receive r (exc ept th e in itia l configu ratio n a fte r a hardwa re reset). 32058k avr32-01/12 334 at32uc3a 26.7.8 .2 baud rate i n spi mode , the baudrat e generator operat es in t he sam e way as in usart synch ronous mode: see sectio n ?26.7.1.4 ? on pag e 307. howeve r, ther e ar e som e restrictions: in sp i master mode: ? the exter nal cloc k clk must no t be selected (usclks 0x3) , an d th e bit clko must b e set to ?1 ? in the mode registe r (mr), in o rder to generat e correctly the seri al cloc k on the clk pin. ? t o o b tain corre ct behavior o f t h e receive r an d th e tra nsmitter , th e valu e prog ramm ed i n c d of must be superio r or equal to 4. ? i f t he intern al clock divide d (clk_usart/div) is selected, the va lue progra mmed in cd must be even t o ensur e a 50:5 0 mark/space rati o on th e clk pin , this valu e ca n b e o dd i f the intern al cloc k is select ed (clk_usart). in spi slave m ode: ? the exter nal cloc k (clk) selectio n is forc ed regard less of the valu e o f th e usclks fiel d in the mod e r egi ste r ( mr ) . likewise , t he v alu e writte n i n b rgr ha s n o effe ct, becaus e th e c loc k is provide d directly by th e signal o n th e usar t clk pin. ? t o obta in correct behavio r o f th e receive r an d the transmitter , the extern al clock (clk) frequency must be at least 4 times lower than t he syst em clock. 26.7.8.3 data transfer up to 9 da t a bits are successively shifted out on th e txd pi n a t each risin g o r falling edg e (de pen din g of cpol an d cpha ) o f the prog ra mme d seri al clock. there is n o sta rt bit, no pa rity bit an d no st op bit. th e number of dat a bi ts is selected by the chrl field and th e mode 9 bi t in the mode register (mr ) . the 9 bi ts are s e lected by setting the mode 9 bit regardless of the chrl f i eld. the msb data bi t is alwa ys se nt fir st in spi mode (master or slave). four combinations o f po larity and phas e ar e availa ble fo r da ta transfers. the clock p o larity is progr ammed wit h the cpol bit in t he mode register . the clo ck phase is pr ogrammed with the cpha bi t. these two p aramete rs determine t he e d ges o f t h e c l oc k si g nal u p on w hich dat a is dr iven and sampled. each o f the two parameters ha s two possible states, resultin g in four possi- ble combinations that ar e incompatib le with on e another. thus, a master/slave pair must use the same parameter pair valu es to communicate. if multiple slaves are used and fixed in differen t configurations , t he mast er must reconfigure itself each ti me it n eeds to communicat e with a d if- ferent slave. tabl e 26-11. spi bu s prot ocol mode spi bus p r otocol mode cpol cpha 0 0 1 1 0 0 2 1 1 3 1 0 32058k avr32-01/12 335 at32uc3a figur e 26-38. spi transfer format (cpha=1, 8 bi ts per transfer) figur e 26-39. spi transfer format (cpha=0, 8 bi ts per transfer) 26.7.8.4 receive r and transmitter control see sectio n ?26.7.2? o n pag e 309. clk cycle (for reference) clk (c p ol = 1) mosi spi maste r ->txd spi slave ->rxd miso spi master ->rxd spi slave ->txd nss spi m a s t e r -> rts spi slave ->cts msb msb 1 clk (c pol= 0) 3 5 6 7 8 l sb 1 2 3 4 6 6 5 5 4 3 2 1 l sb 2 4 clk cycle ( for r eferenc e) clk (cpo l= 0) clk (c pol= 1) mosi spi master -> txd spi slav e - > rxd miso spi master -> rxd sp i s lav e -> txd nss spi master -> rts spi slave -> cts msb 6 5 msb 6 5 4 4 3 3 2 2 1 1 lsb lsb 8 7 6 5 4 3 2 1 32058k avr32-01/12 336 at32uc3a 26.7.8.5 character transmission the characters are sen t by writin g in the tr ansmit holdin g register (thr ) . th e tr an sm itt er repor t s t wo st atus bi ts in th e chan nel s t at us r e gi st er ( csr) : t x r dy ( tr ansmi tte r r ead y), which indi ca tes that thr is empty and txempty, which indicate s that al l th e characte rs written in thr have bee n processed. when the curren t character processing is completed , th e last character writte n in thr is t ransferre d into th e shift registe r of the transmitte r and thr beco mes empty, th us txrdy rises. both tx rdy an d txempty bits ar e low when the transmitter is disabled. writing a characte r in thr wh il e txrdy is lo w has no effect an d th e writte n character is lost. if the usar t is in spi sl av e mode a nd if a char acter mu st be sent wh ile the tra nsmit holding registe r ( thr) is empty, t he unre (underru n error) bit is se t. th e txd tran smission line stays at high leve l duri ng al l this ti me. the unre bi t is cl eared by writin g the control regi ster (cr) with th e rststa (reset status) bi t at 1. in spi master mode , th e slave select line (nss) is assert ed at lo w level 1 tb it befor e th e trans- mission of the msb bi t and released at high level 1 tbit after the transmission of th e lsb bit. so, t he slave select line (nss) is always rele ased betwe en each character transmissio n and a mini- mu m delay of 3 t bit s al ways in serte d. however, in o rder t o addre ss sla v e d e vice s s upp ort ing th e csaat m ode (ch ip select a ctive after transfer), t he slave select line (n ss) can be force d at low level by wr iting the control register (cr) with the rt sen bit at 1. th e slave select line (nss) can be released at hi gh level only by wr iting th e contro l re gister (cr) with the rtsdis bit at 1 (fo r example, when all d ata have b een transferred to the slav e device). in spi slave mo de , t he transmitte r does not require a f a lling edge of th e slave select line (nss) to initiate a characte r transmission but onl y a low level. however, this l o w leve l must be present on the slave select line (nss) at le as t 1 tbit before the first serial clock cycle corres p onding to t he msb bit. 26.7.8.6 character reception wh en a characte r rece ption is complet ed, it is transferr ed to the receive holding registe r (rhr) and the rxrdy bit in the s t atus register (csr) rises. if a character is completed while rxrdy is set , the ovre (ov e rrun error) bit is se t. the las t character is transferr ed into rhr an d overwrites th e previous one. t he ovre bit is cleare d by writing th e contro l register (cr) with th e rststa (reset status) bi t at 1. to ensur e corr ect behavior o f the re ceiver in spi slav e mode , the maste r de vice sending the frame mu st ensur e a minimum delay of 1 t b it between each character transmission . the receiver does not require a falling edge o f t he slave select line (nss) to initiate a ch aracter receptio n but on ly a low leve l. however , this lo w le vel must be presen t on th e slave sele ct line (nss ) at leas t 1 tb it before the first seri al cloc k cycle corresponding to t he msb bit. 26.7.8 .7 receiver timeout because th e receive r b aud rat e cloc k is activ e on ly d urin g da t a t ra nsfer s i n sp i m o de , a receive r tim eout is impossible in this m ode, what ever the tim e-out value is (field to) in the time-out regist er (rtor). 32058k avr32-01/12 337 at32uc3a 26.7.9 test mod es th e usart ca n be programmed to operat e in thre e differen t test mod es. the inter nal loopback capabi lity allo w s on-boa r d diagnostics. in the l o opback m ode t he usa rt in terfac e p ins ar e di s- connect ed o r not an d r econf igur e d fo r lo opb a ck in tern a lly o r exter n ally. 26.7.9.1 normal mode norm al mod e connect s th e rxd pi n o n th e re ceive r inpu t an d the transmitt e r outp u t o n t he tx d pin. figur e 26-40. norm al mo de configuration 26.7.9.2 automatic ec ho mode automati c echo mod e a llows bit-by-bit retransmission . whe n a bi t is received on the rxd pi n, it is s en t t o th e txd pin , a s s how n i n figure 26-4 1 on pag e 337. programm ing th e transmitte r has no effect on the t x d pin. the rx d pin is still conn ected to the receiver input, thus the receive r remains a c tive. figur e 26-41. automati c echo mo de configuration 26.7.9.3 lo cal loopback mode local loopb a ck mode c onnects th e outpu t of the tran smitter directly to th e input of t he receiver, as s h own in figure 26-4 2 on pa ge 337. t he txd a nd rxd pins ar e not used. the rxd pi n h as n o effect on th e receiver and th e txd pi n is continuou sly driven high, as in id le state. figur e 26-42. loca l lo opb a ck m o de con figur ation receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1 32058k avr32-01/12 338 at32uc3a 26.7.9.4 remote loopback mode remote loopback mod e direct ly connects the rxd pi n to t he txd pin, as shown in figu re 26 -4 3 on page 338 . the transmitter and th e receiver are disabled and h ave no effect. this mod e allows bit-by-bit retransmis sion. figur e 26-43. remote loopback mode configuration receiver transmitter rxd txd 1 32058k avr32-01/12 339 at32uc3a 26.8 univer sal synchr onous/asynchr onous receiver/transmitter (usart ) user interface 26.8.1 register mapping 3. values in the versi on register vary with th e ve rsion of th e ip bloc k implementation. tabl e 26-12. re giste r mapping offset register name access reset 0x0000 control register cr write-only ? 0x0004 mode register mr read-write ? 0 x0 008 interrup t enab l e re gis t er ier w r it e - only ? 0x0 0 0c interrup t disab l e r eg ister idr w r i t e- only ? 0 x0 010 interrupt mas k r e g i st er imr r ead-only 0 x0 0x0014 channe l status register csr read-only ? 0x0018 receiv er holding register rhr read-only 0x0 0x001c tr ansmitter holdi ng register thr write-only ? 0x0020 baud rate generator register brgr read-write 0x0 0 x0 024 rece iv e r t i m e- out re g is ter rtor re a d-wr ite 0x0 0x0028 tr ansmitter timeg uard register ttgr read-write 0x0 0x2c - 0x3c res er v ed ? ? ? 0 x0 040 f i d i r at i o r egister f i di re a d-wr ite 0x1 74 0x0044 number of errors r egister ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter reg ister ifr read-write 0x0 0x0050 manchester enco der decoder register man read-write 0x30011004 0x5c - 0xf8 reserved ? ? ? 0xfc version register version read-only 0x? (3) 0x5c - 0xfc reserved ? ? ? 32058k avr32-01/12 340 at32uc3a 26.8.2 usar t contro l register name: cr acces s type: write-only offset: 0x0 reset value: - ? rtsdi s/rcs: reques t t o send disable/relea se spi chi p select ? i f usart d oes no t operate in spi maste r mod e (mode 0xe): 0: no effect. 1: drives th e pin rts t o 1. ? i f usart operat es in spi maste r mod e (mod e = 0xe): rcs = 0: no effect. rcs = 1 : rele ases th e slave select line nss (rts pi n). ? rtsen/fcs: request to se nd enable/force spi chip select ? i f usart d oes no t operate in spi maste r mod e (mode 0xe): 0: no effect. 1: drives th e pin rts t o 0. ? i f usart operat es in spi maste r mod e (mod e = 0xe): fcs = 0 : no effect. fcs = 1 : forc es th e slave select line nss (rts pin) to 0, even if usart is n o tran smitting , in order to addres s spi slave devices supporting the csaat mode (chip selec t active after transfer). ? retto : rearm time-out 0: no e ffect 1: restart time-out ? rstnack: re set non acknowledge 0: no e ffect 1: resets nack in csr. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? rtsdis/rcs rtsen/fcs ? ? 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 7 6 5 4 3 2 1 0 txdis txen rxdis rxen rsttx rstrx ? ? 32058k avr32-01/12 341 at32uc3a ? r stit : re se t iterat io ns 0: no effect. 1: reset s iteration in csr. no effect if the iso7816 is n o t enabled. ? senda : send address 0: no effect. 1: in multidro p mod e only , th e next character writte n to th e thr is sent wit h th e addr ess bit set. ? sttt o: star t time-out 0: no effect. 1: star ts waiting fo r a characte r before clocking the time-out counter. resets th e status bi t timeou t in csr. ? stpbrk: st op break 0: no effect. 1: stops transmissio n o f the brea k aft er a minim um of on e character length an d transmits a high level during 12-b it periods. no e ffe ct if no br ea k is bei n g tr ansm itte d. ? sttbrk : s ta r t br eak 0: no effect. 1: star ts transmission of a brea k after t he characters present in thr an d the transmit shift register have been transmit- ted. n o effect if a b rea k is alread y being transmitted. ? r stst a: reset status bits 0: no e ffect. 1: resets th e status bits pare, frame, ov re, mane rr and rxbr k in csr. ? txdis: transmitte r disable 0: no e ffect. 1: dis ables the transmitter. ? txen: t ransmitter enable 0: no e ffect. 1: enables the transmitter if txdis is 0. ? rxd is: receiv er disable 0: no e ffect. 1: dis ables the receiver. ? rxen: receive r enable 0: no e ffect. 1: en able s the r e ce iver, i f rxd is is 0. ? rsttx : reset transmitter 0: no e ffect. 32058k avr32-01/12 342 at32uc3a 1: resets th e transmitter. ? r strx: rese t receiver 0: no e ffect. 1: resets th e receiver. 32058k avr32-01/12 343 at32uc3a 26.8 .3 usar t mode register name: mr acces s type: read-write offset: 0x4 reset value: - ? onebit: start frame delimit er selector 0: s t art f ram e delimite r is comma nd or data sync. 1: start frame delimiter is o n e bit. ? mo dsy nc : manc hes ter synchr onization mo de 0:th e manchester start bi t is a 0 t o 1 transition 1: the manchester start bit is a 1 t o 0 transition. ? man : m anches te r e nco de r/dec o der enable 0: manchester encoder/decoder ar e disabled. 1: manchester encoder/decoder ar e enabled. ? fil ter: infrared receive line filter 0: the usart do es no t filter the receive line. 1: the usart filter s the receiv e lin e usin g a three-sample filter (1/16-bit clock) (2 ove r 3 majority). ? m ax_itera tion defines the ma ximum number of iterat ions in mode iso7816, prot ocol t= 0. ? v ar_ sync : variab l e synchr on iz atio n o f com mand /dat a syn c star t fram e deli mit er 0: user defined configuratio n of comman d or data sync fi el d depending on sync valu e. 1: th e sync fiel d is updat ed whe n a characte r is written into thr register. ? dsnack: disable successive nack 0: nack is se nt on th e iso lin e as soon as a p arity erro r occur s i n t h e receive d c haracte r (unle ss ina ck is set ). 31 30 29 28 27 26 25 24 onebit modsync man filter ? max_iteration 23 22 21 20 19 18 17 16 ? var_sync dsnack inack over clko mode9 msbf/cpol 15 14 13 12 11 10 9 8 chmode nbstop par sync/cpha 7 6 5 4 3 2 1 0 chrl usclks mode 32058k avr32-01/12 344 at32uc3a 1: succes sive parity erro rs ar e counte d up to the valu e specifi e d i n th e ma x_ iteration field. t h es e p ari ty err ors gen e r- at e a nack on th e iso line . as so on as th is valu e is reached , no additiona l nack is sent on the is o line. the flag ite ratio n is a sse rted. ? inack: inhibit no n acknowledge 0: th e nack is generate d. 1: the nack is no t generated. ? over: oversa mpling mode 0: 16 x o versamp lin g. 1: 8x ove rsampling. ? clk o: clo c k ou tput se lect 0: the us art do es no t drive the clk p i n. 1: th e usart drives th e cl k pi n if usclk s does no t s ele ct th e exte rnal clock cl k. ? mode9 : 9-bi t char act er length 0: chrl d ef i nes characte r le ngt h. 1: 9-bit characte r length. ? m sbf/cpol: bit o rde r o r spi cloc k po larity ? i f usart d oes no t operate in spi mode (mode 0x e an d 0xf): msbf = 0: least significant bit is sent/received first. m sbf = 1: most significant bit is s ent/received first. ? i f usart operat es in spi mode (slave o r master , mo de = 0xe or 0xf): cpol = 0: t he inactive state va lue of spc k is logic level zero. cpol = 1 : t he inac tive state va lue of spck is lo gic level one. cpol is u sed to determin e the inactive state valu e of the seri al cloc k (spck) . it is use d wit h cpha to prod uce th e required clock/data relationsh ip betwee n maste r and slave devices. ? chmode: channel mode ? nbsto p: number of st op bits chmode m ode description 0 0 norm al mode 0 1 automati c echo . receiv er input is con necte d to the txd pin. 1 0 loca l loopback. transmitte r outp ut is connecte d to the receiv er input.. 1 1 remo te loopbac k. rxd pin is interna lly connecte d to the tx d pin. nbstop asynchr onous (sync = 0) synchronous (sync = 1) 0 0 1 st op bit 1 stop bit 32058k avr32-01/12 345 at32uc3a ? par: parity ty p e ? sync/cpha: synchronous mode sele ct or spi clo c k phase ? i f usart d oes no t operate in spi mode (m ode is 0x e an d 0xf): sync = 0: usar t operat es in asynchronou s mode. sync = 1: usart operat es in synchronous mode. ? i f usart operat es in spi mode (m ode = 0xe or 0xf): cpha = 0: dat a is c hanged on the leadin g edg e of spck a nd capt ur e d o n th e followi ng e d g e o f spc k. cpha = 1: data is c aptur ed on th e leadin g edg e of spck a nd change d on the follo wing edg e of spck. cpha determines which edge of sp ck causes data to chang e and which edge causes data to be captured . cp ha is used wit h cpol t o produce th e requir ed clock/data relationsh ip betwee n maste r and slave devices. ? chrl: charact er length. ? usclk s: cloc k selection 0 1 1.5 st op bits reserved 1 0 2 st op bits 2 stop bits 1 1 r e s erv ed re ser v ed par parity type 0 0 0 ev en parity 0 0 1 od d parity 0 1 0 parity forced to 0 (s pace) 0 1 1 parity forced to 1 (m ark) 1 0 x n o parity 1 1 x mu l t i d r op m o de chrl charac ter length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits usclks sele cted clock 0 0 clk_usart 0 1 clk_usart /div (div = xx) 1 0 reserved 1 1 clk 32058k avr32-01/12 346 at32uc3a ? mode mode mode of the usa rt 0 0 0 0 normal 0 0 0 1 rs485 0 0 1 0 hardware handshaking 0 1 0 0 is07816 protocol : t = 0 0 1 1 0 is07816 protocol : t = 1 1 0 0 0 irda 1 1 1 0 spi master 1 1 1 1 spi sl ave others reserved 32058k avr32-01/12 347 at32uc3a 26.8 .4 usar t inte rrupt enabl e register name: ier acces s type: write-only offset: 0x8 reset value: - ? mane a: mancheste r err or inte rrup t enable ? m ane: manchester error interru pt enable ? ctsic: clear to se nd input change interrupt enable ? na ck: non acknowledg e interrupt enable ? rxbuff: buf f er full interrupt enable ? txbufe: buffer empt y interrupt enable ? iter/unre: iterat ion or spi un derru n erro r interru pt enable ? txempty: txempty interrupt ena ble ? timeout : time-ou t interrupt enable ? pare: pa ri ty erro r interrupt en able ? f rame: fr aming error interrupt enable ? o vre: overrun erro r interrupt enable ? endtx : end of tran smit interrupt enable ? endrx: en d o f receive transfer interrup t enable ? r xbrk: receiver break interru pt enable ? t xrdy : txrdy inter rupt enab le ? rxrdy : rxrd y interr up t enab le 31 30 29 28 27 26 25 24 ? ? ? ? ? manea 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 nack rx bu ff txbufe iter/unr e txempty t imeout 7 6 5 4 3 2 1 0 pare frame ovre endtx endrx rxbrk txrdy rxrdy 32058k avr32-01/12 348 at32uc3a 26.8 .5 usar t inte rrupt disable register name: idr 32058k avr32-01/12 349 at32uc3a acces s type: write-only offset: 0xc reset value: - ? mane a: mancheste r err or inte rrup t di sable ? m ane: mancheste r error interru pt disable ? ctsic: clear to se nd input change interrupt disable ? na ck: non acknowledg e interrupt disable ? r xbuff: buff er full interrupt disable ? t xbufe : bu ffer em pty in te rrup t dis a ble ? iter/unre: iterat ion or spi un derru n erro r interru pt enable ? txempty: txempty interrupt disable ? tim eout : ti me- ou t i nt err upt disab le ? pa re: pa r it y e rror i nter r up t d isa ble ? f rame: fr aming error interrupt disable ? o vre: overrun erro r interrupt disable ? endtx : end of tran smit interrupt disable ? endrx: en d o f receive transfer interrup t disable ? rxbrk: receive r break interru pt disable ? txrdy : txrd y interrupt disable ? rxrdy : rxrd y interrupt disable 31 30 29 28 27 26 25 24 ? ? manea 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 nack rx bu ff txbuf e iter/unr e txempt y t imeout 7 6 5 4 3 2 1 0 pare frame ovre endtx endrx rxbrk txrdy rxrdy 32058k avr32-01/12 350 at32uc3a 26.8.6 usar t interrup t mask regist er name: imr acces s type: read-only offset: 0x10 reset value: 0x00000000 ? m anea: man ches te r err or int erru pt mask ? m ane: manchester error interru pt mask ? ctsic: clear to se nd input change interrup t mask ? na ck: non acknowledg e interrupt mask ? r xbuff: buff er full interrup t mask ? txbufe: buffer empt y interrup t mask ? iter/unre: iterat ion or spi un derru n erro r interru pt enable ? txempty: txempty interrupt mask ? tim eout : ti me- ou t i nt err upt mask ? pa re: pa r it y e rror i nter r up t m ask ? f rame: fr aming error interrupt mask ? o vre: overrun erro r interrupt mask ? endtx : end of tran smit interrupt mask ? endrx: en d o f receive transfer interrup t mask ? r xbrk: receiver break interru pt mask ? txrdy : txrd y interrup t mask ? rxrdy : rxrdy interrupt mask 31 30 29 28 27 26 25 24 ? ? manea 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 nack rx bu ff txbuf e iter/unr e txempt y t imeout 7 6 5 4 3 2 1 0 pare frame ovre endtx endrx rxbrk txrdy rxrdy 32058k avr32-01/12 351 at32uc3a 26.8.7 usart channe l status register name: csr 32058k avr32-01/12 352 at32uc3a acces s type: read-only offset: 0x14 reset value: - ? manerr : manchester error 0: no ma nchest er error has been detected since the last rststa. 1: at least on e mancheste r erro r ha s bee n detecte d sinc e th e last rststa. ? c ts: im a g e of cts in put 0: cts is a t 0. 1: cts is a t 1. ? ctsic: clear to se nd input change flag 0: n o i np ut change h as be e n de tected on th e cts pi n sinc e th e last rea d of csr. 1: at l e ast on e input change has b e en detected on the cts pi n since the last read of csr. ? na ck: non acknowledge 0: no n o n acknowledg e ha s not bee n detect ed since t he last rstnack. 1: at l e ast on e non acknowled ge has bee n detect ed since t he last rstnack. ? rxbuff: recep tion buff er full 0: the sig nal buffer fu ll from the receiv e pdc channel is inactive. 1: the sig nal buffer fu ll from th e receiv e pdc channel is active. ? txbufe: transmission buff er empty 0: the sig nal buffer empty from th e transmit pdc c hann el is inactive. 1: the sig nal buffer empty from th e transmit pdc c hann el is active. ? iter/unre: max numb er of repetition s reache d or spi underrun error ? i f usart d oes no t operate in spi slave mod e (mode 0xf): i ter = 0: maximu m numbe r of repetitions ha s not bee n reache d sinc e th e last rststa. i ter = 1: maximu m numbe r of repetitions ha s bee n reached since th e last rststa. 31 30 29 28 27 26 25 24 ? ? manerr 23 22 21 20 19 18 17 16 cts ? ? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 nack rx bu ff txbuf e iter/unr e txempt y t imeout 7 6 5 4 3 2 1 0 pare frame ovre endtx endrx rxbrk txrdy rxrdy 32058k avr32-01/12 353 at32uc3a ? i f usart operat es in spi slav e mod e (mod e = 0xf): unre = 0: no spi u nderr un erro r has occurred since t h e last rststa. unre = 1: at least o ne spi underrun erro r has occurr ed since t he last rststa. ? txempty: transmitter empty 0: ther e are characters i n either thr or th e transmit s hif t reg ister , o r th e transmitte r i s disable d. txempty == 1: me ans that th e transmit shift register is em pt y an d that ther e is n o data in thr. ? timeout : receiv er time-out 0: ther e ha s not bee n a time-out since t he last start time-out command (sttto in cr ) o r the tim e- o ut registe r is 0. 1: th er e ha s bee n a time- out since th e l a st star t time- out command (s ttto in cr). ? pare: pari ty error 0: no pa rit y erro r has bee n detect ed since t he last rststa. 1: at l e ast on e parity erro r has been detected since the last rststa. ? f rame: fr aming error 0: no s top bit has been detected lo w since t he last rststa. 1: at l e ast on e stop bit ha s bee n detected low sinc e the last rststa. ? ovr e: overrun error 0: no ove rru n error has occu rred since the last rststa. 1: at l e ast on e overru n erro r ha s occurred sinc e th e last rststa. ? endtx : end of transmitter transfer 0: the en d of transf er sign al from the transmit pdc ch anne l is inactive. 1: the en d of transf er sign al from the transmit pdc ch anne l is active. ? endrx: en d o f receiver transfer 0: the en d of transf er sign al from the receive pdc ch anne l is inactive. 1: the en d of transf er sign al from the receive pdc ch anne l is active. ? r xbrk: brea k recei ved /e nd o f bre ak 0: no b reak rec ei ve d or en d of b rea k dete cte d sinc e th e last rs tst a. 1: brea k r ece ive d o r en d o f brea k det ect e d sinc e th e last rs tst a. ? txrdy: transmitte r ready 0: a cha ract er is in t he thr waiting t o be transferr ed to t he transmit shift register , or an sttbrk comm a nd has been requested, or the transmitter is disa bled. as soon as the transmitte r is enabled, txrdy becom es 1. 1: ther e is no character in the thr. ? rxrdy : receiv er ready 0: no c omplete character has been received since the last read of rhr or the receiver is disabled . if characters were being received when t he receiver was disa bled, rxrdy changes t o 1 when the receiver is e nabled. 32058k avr32-01/12 354 at32uc3a 1: at least one complete charact er has been r e ceived and rhr has not ye t been read. 32058k avr32-01/12 355 at32uc3a 26.8 .8 usar t receiv e holding register name: rhr acces s type: read-only offset: 0x18 reset value: 0x00000000 ? rxsy nh: received sync 0: last character received is a d ata. 1: last character received is a c ommand. ? rx c hr: received character la st characte r received if rxrdy is se t. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rxsynh ? ? ? ? ? ? rxchr 7 6 5 4 3 2 1 0 rxchr 32058k avr32-01/12 356 at32uc3a 26.8 .9 usart transmit holding register name: thr acces s type: write-only offset: 0x1c reset value: - ? t xsynh : sync field to be transm itted 0: the next characte r sent is encode d as a data. start fram e delimiter is data sync. 1: th e next characte r s ent is encode d as a command. start fram e delimi te r is comm and sync. ? txchr: characte r to be transmitted next character t o be transmitte d after the current characte r if txrdy i s not set. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 txsyn h ? ? ? ? ? ? txchr 7 6 5 4 3 2 1 0 txchr 32058k avr32-01/12 357 at32uc3a 26.8.10 usart baud rate genera tor register name: brgr acces s type: read-write offset: 0x20 reset value: 0x00000000 ? fp: fractional part 0: fraction al divide r is disabled. 1 - 7 : baudrat e resolution, defined by fp x 1 /8. ? cd: cloc k divider 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? fp? 15 14 13 12 11 10 9 8 cd 7 6 5 4 3 2 1 0 cd cd mode iso 78 16 mode = iso78 16 sync = 0 sync = 1 or mode = spi (m aster or slave) ov er = 0 ove r = 1 0 bau d rate cl oc k disabl ed 1 to 6 5535 baud ra t e = selected clock/16/cd baud rate = select ed clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio 32058k avr32-01/12 358 at32uc3a 26.8.1 1 usart receiv er t ime-out register name: rtor acces s type: read-write offset: 0x24 reset value: 0x00000000 ? to: time-out value 0: the receive r time-out is disabled. 1 - 6 5535: the receiver time-out is e nabled an d th e time-out de lay is to x bit period. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 to 7 6 5 4 3 2 1 0 to 32058k avr32-01/12 359 at32uc3a 26.8.12 usart transmitte r timeguar d register name: ttgr acces s type: read-write offset: 0x28 reset value: 0x00000000 ? t g: timeguard value 0: th e t r an smit te r tim eguard is d isabled. 1 - 255: th e transmitte r timeg uar d is e nab led an d th e timeguar d d elay is t g x b it p erio d. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 tg 32058k avr32-01/12 360 at32uc3a 26.8.13 usart fi di ratio register name: fidi acces s type: read-write offset: 0x40 reset value: 0x00000174 ? fi_di_ratio: fi over di ratio value 0: if iso78 16 mo de is selected, th e baud rate generat or generate s no signal. 1 - 2047 : if iso 7 81 6 mod e is sele cted, th e ba ud rate i s th e clock provi de d o n clk divi de d b y f i_di_r ati o. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? fi_di_ratio 7 6 5 4 3 2 1 0 fi_di_ratio 32058k avr32-01/12 361 at32uc3a 26.8.14 usart number o f errors register name: ner acces s type: read-only offset: 0x44 reset value: - ? nb_erro rs: number of errors t otal numbe r of e rro rs that occurre d duri ng a n is o7 81 6 transf e r. th is r egiste r auto matica lly cle ars whe n read. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 nb_errors 32058k avr32-01/12 362 at32uc3a 26.8.1 5 usar t ird a filt e r register name: ifr acces s type: read-write offset: 0x4c reset value: 0x00000000 ? irda_filt er: irda filter se ts the filter o f the irda demodulator. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 irda_f il ter 32058k avr32-01/12 363 at32uc3a 26.8.16 usart manchest er configurat ion register name: man acces s type: read-write offset: 0x50 reset value: 0x30011004 ? drift: drif t compensation 0: th e usart ca n no t re cove r fr om an im por tan t cl oc k d rift 1: the usart c a n recover from cloc k drift. th e 16 x cloc k mode must be enabled. ? rx_mpo l: receiver manchester polarity 0: lo gic zer o is c ode d a s a z ero-to-on e trans ition, l ogic on e is cod ed as a one-to-zero transition. 1: lo gic zer o is c ode d a s a o n e-to-zero trans ition, l ogic on e is cod ed as a zero-to-one transition. ? rx_p p: re ce ive r prea mble p atter n d et ected ? rx_pl: receive r preambl e length 0: the receive r preamb le patter n detection is dis abled 1 - 1 5: th e detected preamble lengt h is rx_pl x bi t period ? t x_mpol : tr a nsm itt er m ancheste r polari ty 0: lo gic zer o is c ode d a s a z ero-to-one trans ition, l ogic on e is cod ed as a one-to-zero transition. 1: lo gic zer o is c ode d a s a o n e-to-zero trans ition, l ogic on e is cod ed as a zero-to-one transition. 31 30 29 28 27 26 25 24 ? drift 1 rx_mpol ? ? rx_pp 23 22 21 20 19 18 17 16 ? ? ? ? rx_pl 15 14 13 12 11 10 9 8 ? ? ? tx_mpol ? ? tx_pp 7 6 5 4 3 2 1 0 ? ? ? ? tx_pl rx_pp preamble patter n defa ult polarity assumed (rx_mpol fiel d not set) 0 0 a l l _ one 0 1 all_zero 1 0 zero_one 1 1 one_zero 32058k avr32-01/12 364 at32uc3a ? t x_pp : transmi tter pream b l e patte rn ? tx_pl: transmitte r preambl e length 0: the transmitte r preamb le patter n generatio n is disabled 1 - 1 5: the pream ble length is tx_p l x bit pe riod tx_pp preamble pattern default polarit y a ssumed ( tx _mpo l f iel d no t s et) 0 0 all_o ne 0 1 all_zero 1 0 zero_one 1 1 one_zero 32058k avr32-01/12 365 at32uc3a 26.8.17 usart versi on register name: version acces s type: read-only offset: 0xfc reset value: 0x00000000 ? variant reserved. no functionalit y associated. ? ver sion vers ion of t he module. no functionalit y associated. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? variant 15 14 13 12 11 10 9 8 ? ? ? ? version 7 6 5 4 3 2 1 0 vers ion 32058k avr32-01/12 366 at32uc3a 27. static memory controller (smc) re v. 1.0.0.0 27.1 features ? 4 chip s elects available ? 64-mby te address space per chip s elect ? 8-, 16- or 32-bit data bus ? word, halfword, byte transfers ? byte write or b y te select lines ? programmabl e setup, pulse and hold tim e f o r re a d sig n a l s pe r ch i p se lect ? programmabl e setup, pulse a n d hold time for wr ite signal s per chip select ? programmabl e data float ti me per ch ip select ? com p lian t w i th lcd m odu le ? extern al wa it req u est ? a u t o mati c switc h t o s low clock m ode ? asynchrono us read in page mode supported: page size ranges fr om 4 to 32 bytes 27.2 overvi ew the st atic memory controller (smc) generates t he signals th at control t he acce ss to t he exter- nal memory devices or p eripheral devices. i t has 4 chi p selects a n d a 2 6-bit add ress bus. the 32-bit data bu s can be co nfigured to interface with 8-, or16-, or 32-bit extern al devices. separate read an d write contro l signals allow fo r direct memory and peripheral interfacing. read an d write sign al waveform s are f ully parametrizable. th e sm c ca n manag e wait req uests from external device s to exten d th e curren t acce ss. the smc i s p rovide d wi t h a n au toma tic slo w c lock mo d e . i n slow cl oc k m ode, it sw i tc he s fr om use r- programmed waveform s to slow-r ate specific waveforms on read an d write signals. t he smc suppor ts asynchrono us bur st read i n page mode access fo r page size u p t o 32 bytes. 32058k avr32-01/12 367 at32uc3a 27.3 block diagram figur e 27-1. block diagram 27.4 i /o lines description tabl e 27-1. i/o line description name description type active l evel ncs[3:0] static memory controller chip sele ct lines output low nrd r ead signal output low nwr0/nwe wr ite 0/wr ite enab le signal output low a0/nbs0 address bit 0/byte 0 se le ct signal output low nwr1 /nbs1 wr ite 1/byte 1 sele ct signal output low a1/nwr 2/ nb s2 ad dress bi t 1/w ri t e 2/ byte 2 se lect si gnal output low nwr3 /nbs3 wr ite 3/byte 3 sele ct signal output low a[25:2] add ress bus output d[31:0] data bus i/o nwait external wa it signal input low smc chip select bus matrix pm clk_smc smc gpio controller ncs[5:0] nr d nwr0/nwe a0/nbs0 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 a[25:2 ] d[31:0] nwait user inter face peri pheral bus ncs[5:0] nr d nwr0/nwe a0/nbs0 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 a[25:2] d[31:0] nwait 32058k avr32-01/12 368 at32uc3a 27.5 p roduct dependencies 27.5 .1 ebi i/ o lines th e stat ic memory controller signa ls pass througth the ebi mo du le where they are multiplexed. th e pro gr a mm e r mu st fi rst con figure th e gpi o con tr olle r t o assig n th e e b i pin s corr espon ding to smc si gnals to thei r peripheral function. if i/ o lines of t he ebi corresponding to smc signals ar e not used by th e application , they ca n be used fo r othe r purposes by th e gpio controller. 27.6 functionnal description 27.6.1 applic atio n example 27.6.1.1 hardware interface figur e 27-2. smc c onnections to st atic memory devices 27.6 .2 external memor y mapping the smc pr ovides up to 2 6 addr ess lines, a[25:0]. thi s allows ea ch chip select lin e to address u p to 6 4 mb ytes of me mory. 128k x 8 sram d0-d7 cs oe we a0-a16 128 k x 8 sram d0- d7 cs oe we a0-a16 128 k x 8 sram d0- d7 cs oe we a0-a16 128k x 8 sram d0-d7 cs oe we a0-a16 d0- d 31 nwr1/nbs1 a0/nbs0 nw r0/n we a1/nwr2/nbs2 nwr3/nbs3 ncs0 ncs1 ncs2 ncs3 ncs5 ncs4 nrd nrd nrd nrd a2-a25 sta ti c memory controller a1/n wr2 /nbs2 nwr0/nwe nwr1/nbs1 nwr3/nbs3 d8-d15 d0-d7 d16-d23 d24-d31 a2-a18 a2-a18 a2-a18 a2-a18 32058k avr32-01/12 369 at32uc3a if t he ph ysical memo ry device connecte d on on e ch ip se lect is smaller tha n 64 mbyt es, it wraps around and ap pears to be re peate d within this space. t h e smc correctly handles any vali d access to the memory dev i ce within th e pag e (see figure 27-3). a[25:0] is o n ly significan t for 8-bit memory , a[25:1 ] is used f or 16-bit memory, a[25:2] is used for 32-b it memory. figur e 27-3. memory connecti ons fo r 6 extern al devices 27.6.3 connectio n to extern al devices 27.6.3 .1 d ata bus width a d ata bu s width of 8 , 16 or 32 bits can be selected for each ch ip select. th is option is c ontrolled by t he fi eld dbw in mode (mod e register) for the corresponding ch ip select. figure 27-4 sh o ws ho w t o co n ne ct a 5 12k x 8- bi t memo ry o n n cs2 . figur e 27-5 show s how to c onne ct a 512k x 16-b it mem ory on ncs2. fig ure 27-6 shows tw o 16-bit memories connected as a singl e 3 2-bit memory. 27.6.3 .2 byte writ e or byte select access each c h ip select with a 16-bi t or 32-bit dat a bus ca n operat e with one of tw o different types o f writ e acce ss: byte writ e o r byte select access. this is controlled by th e bat fiel d of the mode register for th e correspond ing chip select. nc s[0] - ncs[5] nrd nwe a[25:0] d[31:0] smc ncs5 ncs4 ncs3 ncs2 ncs1 ncs0 8 or 1 6 or 32 memory enable memor y ena b le mem or y enab le memory enable memory enable memory enable output enable write enable a[25:0] d[31:0] or d[15:0] or d[7:0] 32058k avr32-01/12 370 at32uc3a figur e 27-4. memory connection fo r a n 8-bi t da ta bus figur e 27-5. memory connection fo r a 16-b it da ta bus figur e 27-6. memory connection for a 32 -bit data bus smc a0 nwe nrd ncs[2] a0 write enable output enable memory enable d[7:0] d[7:0] a[18:2] a[18:2] a1 a1 smc nbs0 nwe nrd ncs[2] low byte enable write enable output enable memory enable nbs1 high byte enable d[15:0] d[15:0] a[19:2] a[18:1] a[0] a1 d[31:16] smc nbs0 nwe nrd ncs[2] nbs1 d[15:0] a[20:2] d[31:16] nbs2 nbs3 byte 0 enable write enable output enable memory enable byte 1 enable d[15:0] a[18:0] byte 2 enable byte 3 enable 32058k avr32-01/12 371 at32uc3a ? byte write access byte write access suppor ts one by t e write signal per byte of the data bus and a single read signal. note that th e smc does no t allow boot in byte write access m ode. ? f or 16-bi t devices : th e s mc provi des nwr 0 and nw r1 wr ite signals fo r respectively byte0 (lower byte) and byte1 (upper byte) of a 1 6-bit bus. on e single read signal (nrd) is p rovided. byte write access is used to connect 2 x 8-bit devices a s a 16-bit memory . ? for 32-bit devices: nwr0, nwr1, nwr2 a n d nwr3, are th e write signals of byte 0 (lower byte), byte1, byte 2 and byt e 3 (upper byte ) respectively. o ne single read signal (nrd) is provided. byte write access is used to connect 4 x 8-bit devices a s a 32-bit memory. byte write optio n is illustrated on figure 27-7. ? b yt e sele ct acce s s in th is mode, read/writ e operations can b e enabled/disabled at a b yte level . one byte-select line pe r byte of th e dat a bu s is provided . one nrd a n d on e nwe signa l control read and write. ? for 16-bit devices: t he smc provid es nbs0 an d nbs1 selectio n signals for respectively byte0 (lower byte) and byte1 (upper byte) o f a 16-bit bus. byte se lect acce ss is used to conn ect on e 16-bit device. ? for 32-bit devices: nbs0, nbs1 , nbs2 and nbs3, ar e th e selection sign als of byte 0 (lower byte), byte1, byte2 and byt e 3 (upper byte) resp ectively. by te sel e ct acc e ss is used t o connect two 16-b it devices. figure 27-8 shows how to connec t tw o 16-bit de vices on a 32-b it data bus in by te select access mode, on ncs3 (bat = byte select access). 32058k avr32-01/12 372 at32uc3a figur e 27-7. connectio n of 2 x 8-bit device s o n a 16-bit bus: byte write option ? s ignal multiplexing depending on th e bat, on ly th e writ e signals or th e byte sele ct signals ar e used. to save io s at the extern al bu s interface, control signals at the smc interfac e ar e multiplexed. for 32- bit d evices, bits a0 and a1 are unused. for 16-bit devices , bit a0 of add r ess is unused. when byte select option is selec ted, nwr1 to nwr3 are unused . when byte write opti on is selected , nbs0 to n bs3 are unused. smc a1 nwr0 nrd ncs[3] write enable read enable memory enable nwr1 write enable read enable memory enable d[7:0] d[7:0] d[15:8] d[15:8] a[24:2] a[23:1] a[23:1] a[0] a[0] 32058k avr32-01/12 373 at32uc3a figur e 27-8. connecti on of 2x16-b it data bus on a 32-b it data bus (byt e selec t option) 27.6.4 standard read and writ e protocols in the fo llowing sect ions , the byt e acce ss ty pe is n o t considered . byte select lines (nbs0 to nbs3 ) always h av e t he sa me timi ng as th e a a ddr ess bus. nwe r epresent s eith er th e nwe sig- na l in by te sele ct acc ess ty pe o r on e o f th e byt e writ e line s (n wr0 to nwr3 ) i n b yt e write access ty pe. nwr0 to nwr3 ha ve the s ame ti mings an d protoc ol as nwe. in t he same way, ncs represen ts on e o f the ncs[0..3 ] chip select lines. smc nwe nrd ncs[3] write enable read enable memory enable nbs0 d[15:0] d[15:0] d[31:16] a[25:2] a[23:0] write enable read enable memory enable d[31:16] a[23:0] low byte enable high byte enable low byte enable high byte enable nbs1 nbs2 nbs3 tabl e 27-2. smc multiple xe d signal translation signal name 32-bit bus 1 6-bit bus 8 -bit bus device type 1x32-bit 2x16-bit 4 x 8 -bit 1x1 6-bit 2 x 8-bit 1 x 8-bit byte access ty pe (bat) byte select byte select byte w rite byte select byte w rite nbs0_a0 nbs0 nbs0 nbs0 a0 nwe_nwr0 nwe nwe nwr0 nwe nwr0 nwe nbs1_nwr1 nbs1 nbs1 nwr1 nbs1 nwr1 nbs2_nwr2_a1 nbs2 nbs2 nwr2 a1 a1 a1 nbs3_nwr3 nbs3 nbs3 nwr3 32058k avr32-01/12 374 at32uc3a 27.6.4.1 read waveforms th e re ad cycle is s h own on figur e 27-9. th e re ad cycle star ts with th e addr ess settin g on t he memory address bu s, i.e.: {a[25:2], a1 , a0 } fo r 8-bit devices {a[25:2] , a1} for 16-bit devices a[25:2] fo r 32-b it devices. figur e 27-9. standar d read cycle ? nrd waveform th e nrd sig nal is characterize d by a setup timing, a pulse width a nd a hold timing. 1. nrd_setup: th e nrd setu p ti me is defined as the setu p o f a dd res s be fo re t he nrd fa lling edge; 2. nrd_puls e: the nr d puls e length is th e time betw een nrd f alling edge and nrd ris- in g edge; 3. nrd_ ho ld: th e nrd h o ld time is d efi ned as th e ho ld tim e of ad dr ess af ter t he nrd ris- in g edge. a[25:2] clk_smc nbs0, nbs1, a0, a1 nrd ncs d[15:0] ncs_rd_setup nrd_setup nrd_pulse ncs_rd_pulse nrd_cycle nrd_hold ncs_rd_hold 32058k avr32-01/12 375 at32uc3a ? ncs waveform similarly , the ncs si g nal can be divided into a s etup time, pulse lengt h a nd hold time: 1. ncs_rd_setup : t he ncs setup time is de fined as the setup time of address before the ncs fa lling edge . 2. ncs_rd_pulse : the ncs p u lse length is the time betwee n ncs fa lling edg e an d ncs risin g edge; 3. nc s_rd _hold: th e ncs ho ld tim e is de fi ne d as t h e h o ld tim e of addre ss afte r t h e ncs risin g edge. ?read cycle th e nrd_cycle time is define d as th e tota l duration o f th e re ad cycle , i.e ., from the time where addr ess is set o n th e addr ess bus to the point wher e addr ess ma y change . the tot al re ad cycle time is equal t o: nrd_c ycle = nrd_setup + nrd_pulse + nrd_hold = ncs_rd_setup + ncs_rd_pulse + ncs_rd_hold all nrd and ncs timin g s are define d separately f or ea ch chip select as a n intege r numbe r of master clock cycles. to en su re that th e nrd and ncs ti mings are coherent , user mus t define the tota l re ad cycle instea d of th e hold timing. nrd_c ycle implicitly defines t he nrd hold time an d ncs ho ld time as: nrd_hold = nr d_cycle - nr d setup - nrd pulse ncs_rd_hold = nr d_cycle - ncs_rd_setup - nc s_rd_pulse ? nul l dela y setu p an d hold if null se tup and hold parame ters are programmed for n rd and/or ncs , nrd and ncs remain acti ve continu ously in cas e of consecutiv e read cycles in th e same memory (see figu re 27 -1 0). 32058k avr32-01/12 376 at32uc3a figur e 27-10. no setup, no ho ld on nrd and nc s read signals ? null pulse programming n ull pulse is n ot permitted. pulse mus t b e at least se t t o 1 . a null value leads t o unpredictab le behavior. 27.6.4.2 rea d mode as ncs and nrd w avefo rms are defined in dependently of one other, th e smc n eeds to know when the rea d data is availabl e on t he dat a b us. th e sm c does not compar e ncs an d nrd tim- ings t o know which signal rises first. the read_mode pa rameter in t he mode regist er of the corres ponding chip select indicate s which sign al of nrd and ncs co ntrols the rea d operation. ? re a d i s c o ntrol l ed b y n r d ( r ead_ mo d e = 1): figur e 27-11 show s the waveforms of a read operatio n of a ty pi cal asynchro nous ram . the read dat a is availabl e t pacc after the falling edge of nr d , and turn s to ?z? after the risi ng edge of nrd. in t his case , th e read_mode mus t be set to 1 (r e ad is cont rolled by nrd), t o indicate that data is avail a ble with t he rising edge of nrd. the smc sam ples the read data intern ally on the ri sing edge of master clock t hat gener ates the rising edge of nrd, whatever t he pro- grammed waveform of ncs may be. clk_smc a[25:2] nbs0, nbs1, a0, a1 nrd ncs d[15:0] nrd_setup nrd_pulse ncs_rd_pu lse nrd_cycle nrd_cycle nc s_r d_ pu lse n cs _rd_pulse nrd _pul se nrd_cycle 32058k avr32-01/12 377 at32uc3a figur e 27-11. read_m ode = 1: data is sam pled by smc before the risin g ed ge of nrd ? read is controlled by nc s (read_mode = 0) figure 27-1 2 shows t h e typica l read cycle of an lcd m o dule. th e rea d data is valid t pacc after the falling edge of the nc s si gnal a n d rem ain s v a lid until the risi ng edge of ncs. data must be sample d whe n ncs is ra ised . i n that case, th e read_mode mus t b e se t t o 0 ( rea d i s c on trolled by ncs ): the smc in terna lly samp les th e dat a on the rising edg e of master clo ck that generates the rising ed ge of ncs, wha teve r th e pr ogr amm ed wave for m of nrd may be. clk_smc a[25:2] nbs0, nbs1, a0, a1 nrd ncs d[15:0] t pacc data sampling 32058k avr32-01/12 378 at32uc3a figur e 27-12. read_m ode = 0: data is sam pled by smc before the risin g ed ge of ncs 27.6.4 .3 write waveforms t he write p r otoc o l is si mila r to the r e ad protoc ol. it is de pict e d in figu re 27-13 . the write cycle st arts w ith th e add re ss setting o n th e memory a ddress b us. ?nwe waveforms th e nwe signal is c haracterize d by a setu p timi ng, a p ulse widt h a nd a h o ld ti ming. 1. nwe_setup: th e nwe setup ti me is define d as th e set up of addres s an d dat a before the nwe fa lling edge; 2. nwe_pul se: th e nwe pulse lengt h is th e time between nwe fal ling edg e a nd nwe risin g edge; 3. nwe_hold: t he nwe hold ti me is define d as th e hold tim e of address an d dat a after t he nwe risin g edge. th e nwe waveforms a pply t o a ll byte-write lin es in byte writ e access mode : nwr0 to nwr3. 27.6.4 .4 nc s wave for ms th e ncs signal waveform s in writ e operation are no t the same tha t those applied in read opera- tions, but ar e separate ly defined: 1. ncs_wr_setup: th e ncs setup ti me is define d as th e setup ti me of addre ss before the nc s fa lling edge. 2. ncs_wr_pulse : the nc s puls e length is the time bet w een ncs fa lling edge and ncs risin g edge; 3. ncs_wr_hold : the ncs hold time is de fin ed as th e ho ld time of addre ss after the ncs risin g edge. clk_smc a[25:2] nbs0, nbs1, a0, a1 nrd ncs d[15:0] t pacc data sampling 32058k avr32-01/12 379 at32uc3a figur e 27-13. write c ycle ?write cycle the write_cycle ti me is defined as the tot al duratio n of the wr ite cycle, th at is, fro m th e time wher e addre ss is set on t he address bus to the point where addr ess ma y change. the tota l write cy cle time is equ al to: nwe_c ycle = nwe_ se tu p + n w e_p u ls e + nw e_ h old = ncs_wr_setup + ncs_wr_pulse + ncs_wr_hold all nwe a n d ncs (write) timings ar e define d separately for each chi p select as an integer num- be r of master clock cycl e s. to ensure tha t the nwe and ncs timings are coheren t, t he user must define the tota l write cycle inst e ad of the hold timing. this implicitly defines the n w e hold ti me an d ncs (write ) hold ti mes as: nwe_h o ld = nwe_cycl e - nw e_se tu p - nw e_pu lse ncs_wr_hold = nwe_cy cle - ncs_wr_setup - ncs_wr_pulse ? nul l dela y setu p an d hold if null se t up pa rameter s ar e p r ogr amme d fo r nwe a nd/or ncs, nwe a nd/or ncs r e main ac ti ve contin uously in case of consecutive w r ite cycles in the same m e mory (see figur e 27-14). ho w- ever, fo r devices that perfor m write operation s on th e rising edge of nwe o r nc s, such as sram, eithe r a setup or a h old must be programmed. clk_smc a[25:2] nbs0, nbs1, a0, a1 nwe ncs nwe_setup nwe_pulse ncs_wr_setup ncs_wr_pulse nwe_cycle nwe_hold ncs_wr_hold 32058k avr32-01/12 380 at32uc3a figur e 27-14. null setup and hold values of ncs and nwe in write cycle ? null pulse programming n ull pulse is n ot permitted. pulse mus t b e at least se t t o 1 . a null value leads t o unpredictab le behavior. 27 .6 .4. 5 wr it e m o de the write_mode par a meter in the mode registe r of the corresponding c h ip sele ct indicates which sign a l controls t he write operation. ? wri te is controlled by nw e (write_mode = 1): figur e 27 -15 shows the waveforms o f a writ e operation with write_mode se t t o 1. th e data is put on the bu s during th e pulse and ho ld step s of th e nwe signal. the intern al data buffers are t u rned o u t after th e nwe_ set up t i me, a n d u nti l t h e e n d o f t he wri t e cy cl e , re g ardles s o f t he programme d wa vef or m o n ncs. clk_smc a[25:2] nbs0, nbs1, a0, a1 nwe, nw e0, n we1 ncs n we_ s etup nwe_pul se n c s_ wr _pu l se ncs_wr_setup nwe_cycle d[15:0] nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle 32058k avr32-01/12 381 at32uc3a figur e 27-15. write_mode = 1. the write o p eration is controlled by nwe ? wri te is controlled by ncs (writ e_mode = 0) figur e 27 -16 shows the waveforms o f a writ e operation with write_mode se t t o 0. th e data is put on the b u s during t he puls e a nd hold st eps of the ncs signal . th e intern al da ta buffers are turned out af ter the ncs_wr_setup time , and until the end of the wri t e cycle, reg ardless of the prog ramme d w avef orm o n nw e. figur e 27-16. write_mode = 0. the write o p eration i s controlled by ncs 27.6.4.6 codi ng timing parameters all ti ming pa rame te r s are define d for o ne chip se lect and are grou ped to ge the r in on e regis- ter acc ording to their type. clk_smc a[25:2] nbs0, nbs1, a0, a1 nwe, nwr0, nwr1 ncs d[15:0] clk_smc a[25:2] nbs0, nbs1, a0, a1 nwe, nwr0, nwr1 ncs d[15:0] 32058k avr32-01/12 382 at32uc3a th e setup regist e r gro ups t h e d efini tion of all s et up parameters: ? nrd_setup , ncs_rd_setup , nwe_setup , ncs_wr_setup t h e pu lse register group s the definition of a ll puls e p ara me ters: ? n rd _pu lse, n cs_rd_ puls e, n we_puls e, n cs_wr _ pulse th e cycle registe r gro ups th e definition of all cycle parameters: ? nrd_cycle, nwe_cyclee ta ble 27-3 sh ows ho w th e t imin g para mete rs ar e cod ed an d t h ei r permitte d r a nge . 27 .6 .4.7 usag e re striction the smc do e s not chec k the validity of the us er -programmed paramete rs. if the sum of setup and pulse para met ers is larger than the corresponding cycle paramet er, this lead s to unpredicta ble beha vior o f the smc. fo r rea d operations: null bu t posit ive setup and ho ld of add ress and nrd and/or ncs ca n not be guaranteed a t the memory inte rface b ecau s e of th e pr op aga tio n delay of th eses signals throu gh exter nal logi c and pad s. if positive setup and ho ld values must be ve rified, then it is strictly reco mmen ded to pro- gra m non-nu ll valu es s o as to cove r po ssible skew s betwe en address, ncs an d nrd signals. fo r writ e operations: if a n ull hold va lue is programm ed on nwe , the sm c ca n guarante e a positi ve ho ld of address, byte select lines, and ncs sig nal after the rising edge of nwe. th is is tru e for wr i te_mod e = 1 o n ly. see ?ear ly rea d wa it state ? o n pa ge 385. fo r r ead an d write o p erations: a null valu e fo r puls e pa ram eters is forb idd en an d m ay le ad t o unpredictab le behavior. in read and write cycles, the setup and hold tim e parameters are define d in reference to th e address bus. for extern al devices that require setu p and hold tim e between ncs a n d nrd sig- na ls (read ), or between ncs an d nwe sig n als (write), these se tup and hold times must be converted into setu p an d hold time s in reference to t he address bus. 27 .6 .5 automa tic wai t s t ates un de r ce rt ain circu mst an ce s, th e smc a utoma tica lly inse rts idle cy cles betw een access es to avoi d bus contentio n or operatio n conflict. tabl e 27-3. co di ng an d ran g e o f timing para mete rs coded value number of bits effective value permi t ted ran ge coded value effective value setu p [5:0] 6 12 8 x setup[ 5] + setup[4:0] 0 31 128 128+31 pulse [6:0] 7 2 56 x pulse [6] + pulse[5:0] 0 63 256 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 127 256 256+127 512 512+127 768 768+127 32058k avr32-01/12 383 at32uc3a 27.6.5.1 chi p select wai t states the smc always inserts an idle cyc le between 2 transfers on separate chip sele cts. this idle cycle e nsure s that ther e is no bu s contentio n between the de-activation of one device and the activati on of t he next one. during ch ip sele ct wait state, a l l control li nes are turned in active: nbs0 to nbs3, nwr0 t o nw r3, nc s[0..5], nrd lines are all set to 1. figur e 27-17 il lustrates a ch ip select wait state betwee n a ccess on chip select 0 a n d chip select 2. 32058k avr32-01/12 384 at32uc3a figur e 27-17. chip s elect wa it stat e between a re ad access on ncs0 an d a write acce ss on ncs2 clk_smc a[25:2] s0, nbs1, a0, a1 nrd nwe ncs0 ncs2 d[15:0] nrd_cycle read to write wait st ate chip select wait state nwe_cycle 32058k avr32-01/12 385 at32uc3a 27.6.5 .2 early read wait state in some cases, the smc inse rts a wait st ate cycle bet ween a writ e access and a read a ccess to allow time for t he writ e cycle to en d before t he subsequent re ad cycle begins. th is wait stat e is not gener ated in addition to a chip select wait state . the ea r ly read cycle t hus only occurs be twee n a wr ite an d r ea d a cce ss t o th e sam e memory device (sam e chip select ). ? a n early read wait stat e is automatica lly inserted if a t least one o f the followin g condition s is valid: ? i f the write controlling si gnal has no hold time and the read controlling signal ha s no se tup time (figure 27-18). ? i n n c s write con tr olled mod e (write _m od e = 0) , i f th er e is n o hold timing on t he n cs si g nal and th e nc s_ rd _se tu p paramete r is se t t o 0, regardless o f th e rea d mod e ( figur e 27-19). th e writ e operation must end wit h a ncs rising edge. without an earl y read wait state , the write operation co uld no t complete properly. ? i n nwe controlled mode (write_m ode = 1) and if ther e is no hold timing (nwe_hold = 0 ), the feedback of t he writ e contro l sig nal is used to control address, data , chip select and byte select lines. if the exter nal writ e contro l sig nal is not inactivate d as expected due to load capacitances, an earl y read wait state is inse rte d a nd a ddress, da ta a nd c ontro l si g nals are maintained on e more cycle. see figur e 27-20. figur e 27-18. early read wa it state: write w ith no hold followed by read with no setup. clk_smc a[25:2] nbs0, nbs1, a0, a1 nwe nrd d[15:0] no hold no setup read cycle early read wait state write cycle 32058k avr32-01/12 386 at32uc3a figur e 27-19. early read wa it state: ncs controlled write with no ho ld followed by a read with no setup. clk_smc a[25:2] nbs0, nbs1, a0, a1 nwe nrd d[15:0] no hold no setup read cycle early read (read_mode= 0 or read_mode=1) wait state write cycle (write_mode=0) 32058k avr32-01/12 387 at32uc3a figur e 27-20. earl y re a d wait sta te: nwe-contro lled writ e wit h no ho ld follo we d by a re ad wit h on e set-up cycle. 27.6.5.3 reload u s er conf igur ation wa it state th e use r ma y change any of th e configuratio n parameters by wri ting the sm c user interface. whe n d e tectin g th at a ne w u se r conf igura t ion h a s been wri t t en in t h e user inter face , t he s m c in ser ts a wa it stat e be fore starti ng the n ext ac cess. the so cal le d ?rel oad u s er conf igura ti on wait state? is u se d by the sm c to load t he new set o f parameters to apply t o next accesses. th e reload configuration wa it state is not a p plied in addition to t he chip select wait sta te. if accesses bef ore a nd after re-program ming the user interface are m ade to diffe rent devices (chi p selects) , then on e single chi p se lect wait state is applied. on the other hand, if accesses b efore and after writing the user interf ace are made to the same device, a reload configura t ion wait state is ins erted, even if the change does no t concern th e current chip select. ? use r procedure to insert a r eload configuratio n wa it state, th e smc detects a writ e access to any mo de reg- i ste r o f t he use r i n t erf a ce. if t he us er onl y m odifies timing registers ( setup, pulse, cycle registers) in the user interface, he must validate t he modification by wri ting the mode, even i f no change was ma de on th e mode parameters. ? s lo w cloc k mode transition a rel oad configuration wait stat e is al so inserted wh en th e slow cloc k mode is entered or exited , after th e en d of t he curren t transfe r (see ?slow clo ck mode? on page 39 8). clk_ s mc a[25:2] nbs0, nbs1, a0 , a1 internal writ e controllin g signal extern al write controlling si gnal(nw e) nrd d[15:0] no hold read setup=1 write cycle (write_m ode = 1) earl y read wait state read cy cle (read_mode=0 or read_mode=1) 32058k avr32-01/12 388 at32uc3a 27.6.5 .4 read to write wait state due t o an internal mechan ism, a wait cycle is always i nserted betwe en cons ecutive re ad and write smc ac cesses. this wait c ycle is referred to as a rea d to write wait sta t e in thi s document. th is wait cycle is ap p lied in addit ion to ch ip select and reload user configuration wait states when they ar e to be inserted . see figur e 27-17 o n pag e 384. 27.6 .6 data float wa it states some memory device s are sl ow to release the external bus. fo r such devices, it is necessar y to add w ait state s ( da ta fl oat wa it st ates) after a rea d a cce ss: ? be fore starti n g a rea d a cce ss t o a d iff e rent externa l mem o ry ? before startin g a writ e access to t he sam e de vice or to a different extern al one. the d a ta float outp ut time (t df ) f or each external memory de vice is programmed in the tdf_cycl es field of th e m ode register for th e correspond ing chip select. t he valu e of tdf_cycl es indicate s the number of data float wait cycles (between 0 a n d 15 ) before the e xterna l de vice rele ase s t he bus, and represen t s the tim e a llow ed f or the da t a out pu t t o go to high impeda nce after th e memo ry is disabled. dat a fl oa t wai t st at es do no t dela y in t ern al me mory ac ce sses . he nce , a singl e acc e ss to an external mem ory wit h lon g t df will not slo w down the exe c utio n of a program from internal memory. the data floa t wait states management depends on the read_ m ode and the tdf_mode fields of th e mode register for the corresponding ch ip select. 27.6.6 .1 read_mode setting the read_m ode to 1 in dicates to the smc t hat th e nrd sign al is responsible for turn- ing off th e tr i-st at e buf fer s o f t he exter nal memo ry d evice . th e data float peri od th en begin s after the rising edge of the nrd sig n al and lasts tdf_cycles mck cycles. whe n th e rea d operat ion is c ontr olled by th e ncs si gnal (read_m od e = 0) , t h e td f fiel d gives t he number of mck cycles duri ng which the data bu s remains bu sy after the rising edge of ncs. figure 27 -21 illustrates t he dat a floa t pe riod in nrd-co ntrolled mode (read_mode =1), assuming a d ata floa t period of 2 cycles (tdf_cycl es = 2). figur e 27-22 shows the r ea d ope r- ation wh en controlle d by ncs (read_m ode = 0) and the tdf_cycles paramete r eq uals 3. 32058k avr32-01/12 389 at32uc3a figur e 27-21. tdf period in nr d controlled re ad access (tdf = 2) figur e 27-22. tdf period in ncs controlled read operatio n (tdf = 3) clk_smc a[25:2] nbs0, nbs1, a0, a1 nrd ncs d[15:0] t pacc nrd controll ed read operation tdf = 2 clock cycles clk_smc a[25:2] nbs0, nbs1, a0, a1 nrd ncs d[15:0] t pacc ncs controlled read operation tdf = 3 clock cycles 32058k avr32-01/12 390 at32uc3a 27.6.6.2 tdf o ptimi zation ena bled (t df _mod e = 1) when the tdf_mode of the mode register is s et to 1 (tdf optimizatio n is enabled), the smc takes advantage of th e setu p period of the ne xt access to optimize the number of wait states cy cle to insert. figur e 27-23 shows a r ead access cont rolled by nrd, followe d by a write ac cess cont rolled by nw e, on chip select 0. chip sele ct 0 ha s bee n programme d with: nrd_h old = 4; read_m ode = 1 ( nrd c ont rolle d) nwe_setup = 3; write_mo de = 1 (n we controlled) tdf_ cycles = 6; tdf_mo de = 1 (optimization enabled). figur e 27-23. tdf o ptimization: no tdf wait states ar e insert ed if th e tdf period is ove r when t he ne xt access begins 27.6.6 .3 tdf optimization disable d (tdf_mod e = 0) w he n o ptimi zatio n i s disabled, td f wa it s tate s ar e inse rted a t th e en d o f th e re a d tr ansfer, s o tha t the data fl oat perio d is e nded when the second access begins. if the hold period o f the read1 controlling s ignal ov erlaps the data float period, no additional tdf wait states w ill be inserted. figur e 27-24, fig ur e 27-25 and figure 27-26 illustrate the cases: ? rea d access followed by a r e ad access on another ch ip select, ? r ead access followed by a wr ite ac cess on another ch ip select, clk_smc a[25:2] nrd nwe ncs0 d[15:0] read access on ncs 0 (nrd controlled) read t o write wait state w r it e acce ss o n ncs0 ( nw e c o ntro lle d) tdf_cycles = 6 nwe_setup = 3 nrd_hold = 4 32058k avr32-01/12 391 at32uc3a ? r ead a ccess fo llo wed by a wr ite a c cess on the same chip se lect, w it h no tdf optim i zation . figur e 27-24. tdf optimization disable d (tdf mode = 0 ). tdf wait states between 2 r ea d accesses o n differen t chip sele cts. figur e 27-25. tdf m o de = 0: tdf wai t stat es betwee n a rea d a nd a write access on different ch ip selects. clk_smc a[25: 2] nbs 0, n b s1, a0, a1 read 1 controlling s ignal (nrd) read 2 controlling s ig nal (nrd) d[1 5: 0] read 1 hol d = 1 read 1 cycle tdf_cycles = 6 chi p s e l ec t wai t sta te 5 tdf wait states tdf_cycles = 6 read2 set up = 1 re ad 2 cycle tdf_mode=0 (optimizati on disabled) clk_smc a[25:2] nbs0, nbs1, a0, a1 read 1 controlling signal(nrd) w ri te 2 cont ro lli ng signal(nwe) d[15 :0] re ad1 cycle tdf_cycles = 4 chi p se l e ct wait state read 1 hold = 1 tdf_cycles = 4 read to write wait state 2 t df wait states writ e2 setup = 1 writ e 2 cycle tdf_ mo d e=0 (optimization disabled) 32058k avr32-01/12 392 at32uc3a figur e 27-26. tdf m o de = 0: tdf wai t stat es betwee n read a nd writ e accesses on t he same chip select. 27.6 .7 ext e rn a l wa it any acc e ss can b e ext ended by an exter nal device usin g the nwai t inp ut sig nal of t he smc. th e exnw_mod e fiel d of the mo de regi ster on the correspondin g chip select must be set t o either to ?10? (froze n mode) or ?11? (r eady mode). when t he exnw_mo de is set to ?00 ? (dis- abled), th e nwait sig nal is simp ly ignored on th e correspond ing ch ip select. the nwai t signal delays the read or wr ite operation in regard s to the read or w r ite controlling signal, depending o n the read and writ e modes of t he corresponding chip select. 27.6.7.1 rest riction whe n one of t he exnw_mo de is enabled, it is mand atory t o progr am at leas t one hold cyc le fo r the re ad/write controllin g signal. fo r tha t reaso n, the nwait signal cannot be used in page mo de (?asynchronous page mode? on page 40 0 ), or in slow clock mode ( ?slow clock mo de? on page 398). th e n wa i t signa l is assume d to be a res pons e o f th e e x t erna l de vi c e t o t he read/ w rite request o f the smc. th en nwait is examined by the smc only in the pu lse state of the re ad or write controlling sig n al. th e a ssertion of the nwai t signal ou tside the expecte d pe riod has n o impact on smc be havior. clk_smc a[25:2] nbs0, nbs1, a0, a1 read1 controlling signal(nrd) write2 controlling signal(nwe) d[1 5:0] read1 hold = 1 tdf_cycle s = 5 read1 cycle tdf_cycles = 5 read to write wait state 4 t df wait sta tes writ e2 setu p = 1 write 2 cycle tdf_mode=0 (optimization disabled) 32058k avr32-01/12 393 at32uc3a 27.6.7.2 froze n mode when th e external de vice asserts t he nwait signal (active low), and afte r intern al synchroniza- ti on o f t his signal , th e sm c state is frozen, i.e., smc in ter nal counters are frozen, a nd all control signals rema in unchanged . when th e resynchronize d nwait signa l is deassert ed, th e smc completes the a ccess, resuming the acce ss from t he point where it was s topped . see figure 27- 27 . t hi s mode must b e selecte d whe n th e exte r na l d evic e uses th e nwai t sig n al t o del a y the access and to freeze th e smc. the a s sertion of the n wait sign al outs ide the ex pected period is ig nored as illust rate d i n fig ure 27-28. figur e 27-27. writ e acce ss with nwait assertio n in fr ozen mod e (exnw_mo de = 10). clk_s mc a [ 25: 2] nbs0, nbs1, a0, a1 nwe ncs d[15:0] 6 5 4 4 3 3 2 2 1 1 2 1 2 2 1 0 0 froze n st ate nwait internally synchronized nwait signal wr it e cycle exnw_mode = 1 0 (frozen) write_mode = 1 (nwe_controlled) n we_puls e = 5 ncs_wr_puls e = 7 32058k avr32-01/12 394 at32uc3a figur e 27-28. read a ccess with nw ait as sertion i n froze n mod e (exnw_mo de = 10). clk_ smc a[25:2] nbs0, nbs1, a0, a1 ncs nrd nwait internall y synchroni zed nwai t s ignal exnw_mo de = 10 (frozen) read_mode = 0 (n cs_con tro ll ed) nrd_pul se = 2, nrd_hold = 6 ncs_rd_pulse = 5, ncs_rd_hold = 3 read cy cle asse rtion is ig no r ed 4 3 2 1 0 2 2 1 0 5 5 5 4 3 2 2 1 1 0 0 froz en st ate 32058k avr32-01/12 395 at32uc3a 27.6.7.3 read y mode in ready mod e ( e xnw_mode = 11), the s m c behaves diffe rently. nor mally, the smc begins the acce ss by down counting t he setup and pulse counters o f th e read/write controll ing signal. in t he last cycle of th e puls e phase, the resynchronized nwait sign al is examined. if asserted, the smc s uspen ds th e access as shown in figure 27-29 and figure 27-30 . after deassertion , th e acce ss is completed: th e ho ld st ep of th e access is performed. this mo de must be selected when th e extern al de vice uses deassertio n of t he nwai t sign al to indicate its ability to complet e the read or write operation. if th e nwait signa l is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/writ e signal, it ha s no impa ct on the acces s length a s shown in fig- ur e 27-30. figur e 27-29. nwai t asse rtion in write access: ready mod e (exnw_ mode = 11). clk_smc a [25 : 2] nbs0, nbs1, a 0 , a1 n w e ncs d[15:0] 6 5 4 4 3 3 2 2 1 0 1 0 1 1 0 f roze n st a te nw ait in te rna ll y synch r o ni ze d nw a i t s i gn al w rite cycle ex n w _ m o de = 1 1 (re a dy m o de) w rite_ m o d e = 1 (nw e_controlled) nw e_ pul se = 5 ncs_w r_pul se = 7 0 32058k avr32-01/12 396 at32uc3a figur e 27-30. nwai t asse rtion in read access: re ady mode (exnw_mod e = 11). clk_ smc a[25:2] nbs0, nbs1, a0 , a1 n cs n rd 6 6 5 5 4 4 3 2 3 1 2 1 0 nwait internally synchronized nwai t signal read cycle exnw_mod e = 11 ( ready mode) read_mod e = 0 (ncs_controlled) nrd_pul se = 7 ncs_rd_pul se = 7 1 0 0 assertion is ignored assertion is ignored wait state 32058k avr32-01/12 397 at32uc3a 27.6.7.4 nwai t latenc y and read/writ e timings there ma y be a latency between the as se rtion of the read/w rite controlling signal and the asser- tio n of th e nwai t signal by the device. t he programme d p ulse lengt h of t he read/write controlling signal must be at least equal to this latency plu s the 2 cy c les of resynchronization + 1 cycle. ot herwise , th e smc ma y e nt er th e ho l d stat e of the access without detectin g the nwait signal a s sertion. this is true in froz en mode as we ll as in ready mode. this is illustrated on fig- ur e 27-31. when exnw _ mode is enabled (ready or frozen), the use r must progra m a pulse length of the read and write controlli n g signal of at least: minimal pul s e length = nw ait latenc y + 2 resynchronization cycles + 1 c ycle figur e 27-31. nwai t latency wait sta te 0 1 2 3 4 clk_smc a[2 5: 2] nbs0, nbs1, a0, a1 nrd nwait nternally synchronized nw ai t si gnal minimal pulse length 0 0 nwait latency 2 cycle resynchronization read cycle exnw_mode = 10 or 11 read_mode = 1 (nrd_controlled) nrd_pulse = 5 32058k avr32-01/12 398 at32uc3a 27.6 .8 slow cloc k mode th e sm c is ab le to automatically a pply a set of ?s low cloc k mo de? read/w rite waveform s when an inter nal sign al driven by th e powe r managemen t contro ller is asserted becaus e clk_smc has been turned to a very slow clo ck rat e (typically 32k hz clo ck rate ). in this mode , th e user-pro- grammed waveform s are ignored a nd th e slow clock mode waveforms ar e applied. this mode is provid ed so as to avoid reprogramming t he user interface wit h appropriate waveform s at very sl ow clock rate . whe n activated , the slow mode is active on all ch ip selects. 27.6.8 .1 slow clock mo de wave for ms figure 27-32 illustrates th e read and write operations in slow clock mode. they a re valid on all chip sele cts. indicates the va lue of read and wr ite parameters in slow clo ck mode. figur e 27-32. read/write cycles in slow clock mode clk_smc a[25:2] nbs0, nbs1, a0, a1 ncs nwe nwe_ cy cl es = 3 slow clock mode wri te 1 1 1 clk_smc a[25:2] nbs0, nbs1, a0, a1 ncs nrd sl ow cl ock mode read nrd_cyc le s = 2 1 1 tabl e 27-4. rea d a nd writ e timi ng paramete rs in slow cloc k mode read pa ram et er s duration ( cy c les) write parameter s dura tion (cy c les) nr d_ setup 1 n we_ setup 1 nrd_pulse 1 nwe_pulse 1 ncs_rd_setup 0 ncs_wr_setup 0 ncs_rd_pulse 2 ncs_wr_pulse 3 nr d_ cycle 2 nwe _ cyc le 3 32058k avr32-01/12 399 at32uc3a 27.6.8. 2 swit ching fro m (to) slo w cloc k mode t o ( from ) nor m al m ode when switching from slow clock m ode to th e norma l mode , th e curren t slow clock mode transfer is c omplete d at high cloc k rate , with th e set of slow cl oc k mode parameters.see figure 27-3 3 on pag e 399. th e external device may n o t be fast enoug h to support such timings. fi gur e 27- 34 il lust r ate s th e rec omm ended procedu re t o properl y s wit ch f rom one mod e to the other. figur e 27-33. clock ra te transition occu rs while t he smc is performi ng a write operation clk_smc a[25:2] nbs0, nbs1, a0, a1 ncs nwe slo w clock mo de internal signal from pm this write cycle finishes with the slow clock mode set of parameters after the clock rate transition nwe_cycle = 3 slow c lock mod e write slow cl ock mode write 1 1 1 1 1 1 2 3 2 nw e_cycle = 7 normal mo de write slow clock mode transition is detected: reload configuration wait state 32058k avr32-01/12 400 at32uc3a figur e 27-34. recom mended proce dur e t o switc h fr om slow cl oc k mode to normal mod e or from normal mode to slow clock mode 27.6.9 asynchronous page mode the sm c suppor ts asynchronous burs t reads in pag e mode , providin g tha t th e page mode is enabled in th e mode regist er (pmen field). t he page size mus t be con f igured in the mode registe r (ps field) to 4, 8, 16 o r 32 bytes. th e page defines a set of consecut ive byte s int o memory . a 4-byte page (resp. 8-, 16-, 32-byte page ) is always aligned to 4-byte boundar ies (resp. 8-, 16-, 32-byte boundar ies) of memory. the msb o f dat a address define s th e addre ss o f the page in m emory, the l sb of addre ss define the address of t he dat a in th e pa ge as deta iled in tabl e 27-5. with pag e mod e memory devices , the firs t access to on e page (t pa ) take s longer than th e subse- quent accesses to t he page (t sa ) as show n in f ig ur e 27- 35 . whe n in page m ode , t he s mc ena bles th e use r to de fine differe nt re ad timings fo r t he firs t a c cess withi n o ne pag e, and n e x t accesses with i n th e page. notes : 1. a de n otes th e a ddress bu s of th e mem ory de vi ce 2. fo r 16-bit devices, th e bit 0 of ad dress is ignored. fo r 32-bit devices, bits [1:0] are ignored. 27.6.9.1 prot ocol and timing s in page mode fig ur e 27-35 shows t he nrd an d ncs timing s in page mod e access. clk_smc slow cl ock mode inter nal s i gnal fr om pm a[25:2] nbs0, nbs1, a0, a1 nwe ncs 1 1 slo w cloc k mo de write 2 3 2 i dle state reload configuration wait state no rmal mode write 1 tabl e 27-5. page add re ss an d dat a address withi n a p age page size page address (1) data address in the page (2) 4 byt es a [25:2] a [ 1:0] 8 byt es a[2 5:3] a [ 2 : 0] 16 bytes a[25:4] a[3:0] 32 bytes a[25:5] a[4:0] 32058k avr32-01/12 401 at32uc3a figur e 27-35. page mode read protocol (address ms b an d lsb ar e defined in ta ble 27-5 ) th e nrd and ncs si gnals are he ld low duri ng all read transfers, whatever th e programmed val- ues of the setup and ho ld timings in the u s er inte rface may be. moreover, the nrd and nc s timings are iden t ical. the pulse length of the firs t access to the page is defined wi th the ncs_rd_pulse field of the pulse register . the pulse lengt h of subsequent accesses wi thin the page are defined usi n g the nrd_pulse parameter. i n pa ge mode, th e programmin g of the rea d timi ngs is describe d in tabl e 27-6: t he smc doe s not ch eck th e coherency of timings. it wi ll always a pply th e ncs_rd_pulse tim ing s as pag e a cc es s timin g ( t pa ) and t he nrd_pulse fo r ac cesses to t he pag e (t sa ), ev en if the programmed value for t pa is sh orter than the programmed value for t sa . 27.6.9 .2 byte access type in page mode th e byte acce ss type configuration rema ins active in page mode. for 16-bit or 32-bit page mode de vices that require byte selectio n signals, configure t he bat field of th e register to 0 (byt e select access type). clk_smc a[msb] a[lsb] ncs nrd d[15:0] t pa ncs_ rd _ pulse t sa nrd_pulse nrd_pulse t sa tabl e 27-6. programm ing of read timing s in pag e mode parameter value definition read_mode ?x? no impact ncs_rd_setup ?x? no impact ncs_rd_pulse t pa access time of fi r st access to the page nr d_se tup ?x? n o i m p a ct nrd_pulse t sa access time of subse q uent accesses in the page nrd_cycle ?x? no impact 32058k avr32-01/12 402 at32uc3a 27.6.9.3 pag e mode restriction the page mod e is not compatib le with the use of the nwa it signal. using th e pag e mo de and t he nwait sign al may lead t o unpredicta ble behavior. 27.6.9.4 sequenti al and non-sequent ial accesses if the ch ip select and the msb of addr esses as defin ed in tabl e 27-5 ar e identical , then the cur- rent acce ss lies in t he sam e page as the prev ious one, a nd no pag e br eak occurs. using th is information, all d ata within th e sa me page , sequential or not sequential, ar e accessed wit h a minimu m acce ss time (t sa ). fig ur e 27-36 illustrates access to an 8-bit memory device in page m ode, with 8-byte pages. access t o d1 c auses a page access wit h a long access time (t pa ) . accesses to d 3 and d7 , though they are not sequential accesses, only require a s hort access time ( t sa ). if the m sb of ad dre sses ar e d ifferent, th e smc per form s th e acc e ss o f a n ew page. i n t he sam e way, if the chip se lect i s diff erent from the previo us access, a pag e bre ak occurs. i f two sequen- ti al accesses ar e made to t he pa ge mod e memory, bu t separate d by a n oth e r inter nal o r ext ernal peripheral access , a page break occu rs on the second access because the chip selec t of the device was d easserte d betwee n both accesses. figur e 27-36. access to non-sequential data within the same page clk_smc a[25:3] a[2], a1, a0 ncs nrd d[7:0] a1 page address a3 a7 d1 d3 d7 ncs_rd_pulse nrd_pulse nrd_pulse 32058k avr32-01/12 403 at32uc3a 27.7 u ser interface t he smc is programm ed us in g th e regi st er s liste d i n table 27 -7 . for each chip selec t , a set of 4 registe r s is used t o pro- gra m th e parameters of t he exter nal de vice connect ed on i t. in tabl e 27-7, ?cs_number ? denote s th e ch ip select number. 16 byte s (0x10 ) ar e re quir e d per chip se lect. th e use r mu st complete writing th e configuratio n by writin g an y on e of th e mode registers. tabl e 27-7. smc r egist er mapping offset register name access reset state 0x10 x cs_ number + 0x00 smc s etup register setup read/write ? 0x10 x cs_ number + 0x04 smc p u lse register pulse read/write ? 0x10 x cs_ number + 0x08 smc cycl e register cycle read/write ? 0x 10 x cs_num ber + 0x0c smc mo de register mode read/write ? 32058k avr32-01/12 404 at32uc3a 27.7.1 set up regist er register name: se tu p[0 ..3] acces s type: read/write offset: 0x10 x cs_number + 0x 00 reset value: ? ? ncs_rd_setu p: ncs se tup length in re ad access in rea d access , the ncs sig n al set up lengt h is defined as: ncs setup length = (128* ncs_r d_setup[5 ] + ncs_rd_setup[4:0]) clock cycles ? nrd _set up : nrd setup length the nrd s ignal setup length is de f ined in clock cycles as: nrd setu p length = (128 * nrd_setup[5] + nrd_setup[4:0 ]) clock cycles ? ncs_wr_setup: ncs se tup length in w rite access in writ e access, t he ncs sign al setu p length is define d as: ncs setup length = (128* ncs_w r_setup [5] + ncs_wr_setup[4:0]) clock cycles ? nwe_setup: n we setup length th e nwe signa l setu p length is d efine d as: nwe setu p le ng th = ( 128* nwe_se tup[5] + nwe _setup[4:0]) clock cycles 31 30 29 28 27 26 25 24 ? ? ncs_rd_setup 23 22 21 20 19 18 17 16 ? ? nrd_setup 15 14 13 12 11 10 9 8 ? ? n c s _w r _ set up 7 6 5 4 3 2 1 0 ? ? nwe_setup 32058k avr32-01/12 405 at32uc3a 27.7.2 puls e register register name: pulse[0..3 ] acces s type: read/write offset: 0x10 x cs_number + 0x 04 reset value: ? ? ncs _ r d_pulse : n c s pu lse leng th i n read ac cess in standar d read access, th e ncs signal pu lse length is define d as: ncs pulse length = (256* ncs_rd_pul se[6] + nc s_rd_pulse[5:0]) clock cycles th e ncs pulse lengt h mu st b e at le ast 1 clock cycle. in pa ge mo de rea d acce ss , th e ncs_rd_pulse par ame te r defi nes t he d ura tion of th e firs t access t o on e pa ge. ? nrd _pu l se: nrd pulse length in sta nd ar d re a d access, the nr d signal pulse lengt h i s defi ne d i n clock cyc les as: nrd puls e length = (256* nrd_pulse[ 6] + n rd_pulse[5:0]) clock cycles th e nrd pulse lengt h must b e at leas t 1 clock cycle. i n pa ge mode rea d access , th e nrd_pulse parameter defines t he duratio n of th e subsequent ac cesses in th e page. ? ncs_wr_pulse: ncs pu lse length in wr ite access in writ e access, t he ncs sign al pulse lengt h is defined as: ncs pulse length = (256* ncs_wr_pul se[6] + ncs_w r_pulse[5:0]) clock cycles th e ncs pulse lengt h mu st b e at le ast 1 clock cycle. ? n we _puls e : n we pulse length th e nwe signal pu lse length is define d as: nwe pu lse len gt h = (256 * n we_pu ls e [6] + nwe _pulse [5:0]) cloc k cycles the nw e puls e length must be at leas t 1 clock cycle. 31 30 29 28 27 26 25 24 ? ncs_rd_pulse 23 22 21 20 19 18 17 16 ? nrd_pulse 15 14 13 12 11 10 9 8 ? ncs_wr_pulse 7 6 5 4 3 2 1 0 ? nwe_pulse 32058k avr32-01/12 406 at32uc3a 27.7.3 cycl e register register name: cy c le [0..3] acces s type: read/write offset: 0x10 x cs_number + 0x 08 reset value: ? ? nrd_ c ycle: to tal read cycl e length the to ta l re ad cyc le l eng t h i s t he to t al dura ti on in c lo c k cycles of the re ad cycle. it is equal to the sum of th e setup, pulse an d ho ld steps of the nrd a n d ncs signals. it is define d as: read c ycle length = (nrd_cycle[8:7]*256 + nrd_cycle[6:0 ]) clock cycles ? nwe_cycle: tot al writ e cycl e length t h e to ta l writ e cycl e len g th is the t ot a l durati o n i n cl ock cycles of th e writ e cycle. it is equ al t o th e sum o f t h e setup, pu lse an d ho ld steps of the nwe a nd ncs signals. it is de fined as: write cy c le length = (nwe_cy cle[8:7 ]* 256 + nwe_cy cle[6:0]) clock cycles 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? nrd_cycle 23 22 21 20 19 18 17 16 nrd_cycle 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? nwe_cycle 7 6 5 4 3 2 1 0 nwe_cycle 32058k avr32-01/12 407 at32uc3a 27.7.4 mo de register register name: mode[0 ..3] acces s type: read/write offset: 0x10 x cs_number + 0x 0c reset value: ? ? ps: page size if pag e mode is e nabled, this field indicate s th e siz e of the page i n bytes. ? p men: pag e mod e enabled 1: asy nchr ono u s bu rst rea d in p a ge mo de is ap plie d on th e corr espo nd ing chip sel ect. 0: st anda rd rea d is a ppli ed. ? tdf_m ode: tdf optimization 1: tdf op timizatio n is enabled. ? the numbe r of tdf wa it states is op timiz ed usin g th e set up perio d of the next read/write access. 0: tdf optimizatio n is disabled. ? the numbe r of tdf wa it states is inse rted before th e next acce ss begins. ? tdf_cycles: data float time this fi eld gives t he intege r numb er of cloc k cycles required by th e extern al device t o release t he dat a after th e risin g edge o f the re ad control ling signal. th e smc always provide one fu ll cycle of bus turnaround after the tdf_cycles p eriod. the 31 30 29 28 27 26 25 24 ? ? ps ? ? ? pmen 23 22 21 20 19 18 17 16 ? ? ? t df_mode td f _cycles 15 14 13 12 11 10 9 8 ? ? dbw ? ? ? bat 7 6 5 4 3 2 1 0 ? ? exnw_mode ? ? writ e_mod e read_mode tabl e 27-8. page s ize settings. ps pag e si ze 0 0 4-byt e page 0 1 8-byt e page 1 0 16-b yte page 1 1 32-b yte page 32058k avr32-01/12 408 at32uc3a ex ter nal b u s canno t be used by anoth e r chip selec t du ring tdf_cycl es + 1 cycle s. from 0 up to 1 5 tdf_cycl es can be set. ? bat: byte access type this field is use d o n ly if dbw define s a 16- or 32-bit data bus. 1: b y te write access type: ? write operation is con trolle d us ing ncs, nwr0 , nwr1 , nw r2, nwr3. ? r e a d opera tion i s c ontrolled usi ng nc s a nd nrd. 0: b y te sele ct access type: ? wr ite opera tion is controlled using n cs, nwe, nb s0, nbs1, nbs2 and nbs3 ? rea d operation is con trolle d us ing ncs, nrd, nbs0, nbs1, nbs 2 and nbs3 ? exnw_ mode: nwai t mode th e nwai t sign al is used to extend t he curren t read or write signal . it is only taken int o account duri ng th e pulse ph ase of the read and wri t e controlling si gnal. when the use of nwait is enable d, at least one cycle hol d duration m u st be pro- grammed for the read and write controlling si gnal. ? disab led mode: the nwai t input sign al is ignored on t he corresponding chip select. ? froze n mode: if asserted, the nwai t signal freezes the current read or writ e cycle. afte r deassertion, the read/write cycle is r esumed from t he point wher e it wa s stopped. ? r eady mode: the nwai t si gnal indicates the availability of the extern al devi ce at t he end of t he puls e of th e co ntro lling read or writ e sig nal , to complete the access . i f hig h , th e access nor mall y comp letes . if low , t he acces s is ex tend e d until nw ait return s high. ? write_mode 1: the write operation is controlle d by the nwe signal. ? i f tdf optimiza tion is enab led (tdf_mode =1 ), tdf wait state s w i l l be inser t ed a ft er t he set up o f n we. 0: the write operation is controlle d by the ncs signal. ? i f tdf optimiza tion is enab led (tdf_mode =1 ), tdf wait st ates will be insert ed after the se tup of ncs. ? read_mode: 1: the read operat ion is contro lled by t he nrd signal. ? dat a bus widt h (dbw) dbw d ata bus width 0 0 8-bit bus 0 1 16-bit bus 1 0 32-bit bus 1 1 reserved tabl e 27-9. exnw_mode exnw_mode nw ait mode 0 0 disabled 0 1 reserved 1 0 frozen mode 1 1 rea dy m ode 32058k avr32-01/12 409 at32uc3a ? i f tdf cycles ar e programmed , the external bu s is marked bu sy after the rising edg e of nrd. ? i f tdf op timizati on is enab le d (tdf_m ode = 1), tdf wait stat es a r e inse rte d a f ter t h e se t up of nrd. 0: the read operat ion is contro lled by t he ncs signal. ? i f tdf cycles ar e programmed , the external bu s is marked bu sy after the rising edg e of ncs. ? i f tdf op timizati on is enab le d (tdf_m ode = 1), tdf wait stat es a r e inse rte d a f ter t h e se t up of ncs. 32058k avr32-01/12 410 at32uc3a 28. sdram controller (sdramc) re v: 2.0.1.1 28.1 features ? numerou s configurations supported ? 2 k, 4k, 8k ro w addres s memory parts ? s dram with tw o or four internal banks ? s dram with 1 6 - or 32-bit data path ? programming facilities ? word, half-word, byte access ? automatic page brea k when memory boundary has b e en reached ? m ulti bank ping-pong access ? timing parameters specified by software ? automati c refres h operation, refre sh rate i s programmable ? aut omatic update of ds, tcr and pa sr param e t e r s ( m ob ile sdra m devices) ? energy-saving capabilities ? s elf- refresh , p o w e r-down a n d deep power modes supported ? s upport s mobile sdra m devices ? erro r detection ? r efr esh error int errupt ? sdram power- up initialization by software ? cas l atency of 1, 2, 3 supported ? au to precharge command n ot used 28.2 description the sdram controller (sd ramc) extends the memor y capabilities of a ch ip by providing the interface to a n exte rnal 16-bi t or 32-bi t sdram device. t he page size sup ports range s from 2048 t o 8 1 9 2 a n d th e num ber of colu mn s f rom 256 t o 2 048 . it s uppo rt s by te (8-bi t), hal f-w ord (16-bit) a nd word (32-bit) accesses. th e sdram controller supports a re ad or write burst length of one location. it keeps trac k o f the acti ve row in each bank, thus maximi zing sd ram per formance, e.g. , t he applicat ion may be plac ed in on e ba nk an d data in the other banks. so as to opti mize performance, it is advisable to avoi d accessin g different ro ws in th e same bank. the sdra m co ntroller su pp o rts a c as latency of 1, 2 o r 3 a n d op timizes t he r ea d a ccess depending on the frequency. the different modes available - self-refresh, power-dow n a nd deep power-down modes - m ini- miz e power consumptio n on the sdra m device. 32058k avr32-01/12 411 at32uc3a 28.3 block diagram figur e 28-1. sdra m controller block diagram 28.4 i /o lines description memory controller peripheral bus sdramc interrupt sdck sdcs sdramc_a[12:0] sdramc pio controller ba[1:0] sdcke ras cas sdwe nbs[3:0] user interface pmc mck d[31:0] sdramc chip select tabl e 28-1. i/ o lin e descript ion name description type active l evel sdck sdram clo ck output sdcke s dram clock enable output high sdcs sdram control l er chip select output low ba[1:0] bank sele ct signals output ras row signal output low cas co lumn signal output low s d we s dra m w r i t e en ab le o u t p ut l ow nbs[3:0] da ta mask enable signals output low sdramc_a[12:0] addre ss bus output d[31:0] da ta bus i/o 32058k avr32-01/12 412 at32uc3a 28.5 a pplication example 28.5 .1 hardwa re interface figure 28 -2 shows an example o f sdram device conne cti on to the sdram controller using a 32-b it dat a bus width. figur e 28-3 shows an example o f sdram device connectio n usin g a 16- bit dat a bu s width . it is imp ortan t t o not e tha t these exam p les ar e give n for a direct con nec tio n of t he devices to th e sdram co ntroller , withou t externa l bu s inter face or pio cont roller multiplexing. figur e 28-2. sdr am controller connections to sdra m device s: 3 2- b it data b us wi d th figur e 28-3. sdr am controller connections to sdra m device s: 1 6- b it data b us wi d th sdram controller d0-d31 sdramc_a[0-12] ras cas sdck sdcke sdwe nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nbs1 nbs2 nbs3 sdcs d0-d7 d8-d15 ba0 ba1 a10 sdramc_a[0-9], sdramc_a11 sdramc_a10 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sdramc_a[0-9], sdramc_a11 sdramc_a10 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 sdramc_a[0-9], sdramc_ a11 sdramc_a10 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sdramc_a[0-9], sdramc_a11 sdramc_a10 ba0 ba1 nbs0 nbs1 nbs3 nbs2 sdwe sdwe sdwe sdwe sdram controller d0-d31 sdramc_a[0-12] ras cas sdck sdcke sdwe nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nbs1 sdcs d0-d7 d8-d15 ba0 ba1 a10 sdramc_a[0-9], sdramc_a11 sdramc_a10 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sdramc_a[0-9], sdramc_a11 sdramc_a10 ba0 ba1 nbs0 nbs1 sdwe sdwe 32058k avr32-01/12 413 at32uc3a 28.5 .2 softwa re interface th e sdram addres s space is organized into banks, rows, and column s. th e sdram controller allows m apping differe nt memory type s according to t he values se t in th e sdramc configura- tion register. th e sdram controller?s function is t o make th e sdram device ac cess protocol transparent to t he user. ta ble 28-2 to tabl e 28-7 illustrate the s d ram devic e memor y m a pping s e en by th e user in correlation with the device structure. variou s configurations are illustrated. 28.5.2.1 32-bit memor y data bu s width notes: 1. m[1:0] is the byte addr es s i n side a 32-bit w ord. 2. bk[1] = ba1, bk[0] = ba0. tabl e 28-2. sdram configuration mapping: 2k rows, 256/512/1024/204 8 columns cp u a ddr ess line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m[1:0] bk[1:0] row[10:0] column[8:0] m[1:0] bk[1:0] row[10:0] column[9:0] m[1:0] bk[1:0] row[10:0] column[10:0] m[1:0] tabl e 28-3. sdram configuration mapping: 4k rows, 256/512/1024/204 8 columns cp u a ddr ess line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m[1:0] bk[1:0] row[11:0] column[8:0] m[1:0] bk[1:0] row[11:0] column[9:0] m[1:0] bk[1:0] row[11:0] column[10:0] m[1:0] tabl e 28-4. sdram configuration mapping: 8k rows, 256/512/1024/204 8 columns cp u a ddr ess line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m[1:0] bk[1:0] row[12:0] column[8:0] m[1:0] bk[1:0] row[12:0] column[9:0] m[1:0] bk[1:0] row[12:0] column[10:0] m[1:0] 32058k avr32-01/12 414 at32uc3a 28.5.2.2 16-bit memor y data bu s width notes: 1. m0 is t he byt e a ddress insi de a 16-bi t half-word. 2. bk[1] = ba1, bk[0] = ba0. tabl e 28-5. sdram configuration mapping: 2k rows, 256/512/1024/204 8 columns cp u a ddr ess line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 bk[1:0] ro w[ 10 :0] col umn [7 : 0] m 0 bk[1:0] row[10:0] column[8:0] m 0 bk[1:0] row[10:0] column[9:0] m 0 bk[1:0] row[10:0] column[10:0] m 0 tabl e 28-6. sdram configuration mapping: 4k rows, 256/512/1024/204 8 columns cp u a ddr ess line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m 0 bk[1:0] row[11:0] column[8:0] m 0 bk[1:0] row[11:0] column[9:0] m 0 bk[1:0] row[11:0] column[10:0] m 0 tabl e 28-7. sdram configuration mapping: 8k rows, 256/512/1024/204 8 columns cp u a ddr ess line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m 0 bk[1:0] row[12:0] column[8:0] m 0 bk[1:0] row[12:0] column[9:0] m 0 bk[1:0] row[12:0] column[10:0] m 0 32058k avr32-01/12 415 at32uc3a 28.6 p roduct dependencies 28.6 .1 sdram device initialization the initializati on sequ ence is generated by so ftware. the sdram de vices ar e initialized by the following sequence: 1. sdram features mu st be se t in the configuratio n register : asynchronous timings (trc, tras , ...), numbe r o f column, rows , c as late n cy, an d t h e da t a bu s widt h. 2. fo r mob ile sdram, temperature-compensate d self refresh (tcsr), driv e strengt h (ds) an d partial arra y self refr esh (pasr) must be set in th e low power register. 3. the sdra m m emory typ e mus t b e set in the memory de vic e r e giste r. 4. an no o peratio n (nop)command must be issued to t he sdra m devices to start the sdram clock. t h e applicat ion must set mode to 1 in th e an d perfor m a write access to an y sdram address. 5. a minimum paus e of 200 s is provided to prece de any sign al toggle. 6. an all b a nks precharg e command must be issued to t he sdram devices. th e applica- ti on must set mode to 2 in t he mode register an d perform a write access to an y sdram address. 7. eigh t auto-refre sh (cbr) cycles ar e provided. th e application must set th e mode to 4 in t he mode register and perform s a write acce ss to an y sdram locati on eight times. 8. a mo de regist er set (mrs) cycle must be issued t o program th e parameters of the sdra m devices, in p articula r cas l atency and burs t length. t h e applic atio n mu st set mo de to 3 in t he mode registe r an d perf orm a writ e access t o t he sdram . th e wr ite address must be chose n so that ba[1:0] are set t o 0. for example, with a 1 6-bit 1 28 mb sdram (12 rows, 9 columns, 4 banks ) bank address , the sdram w rit e ac cess should b e don e a t the addre ss 0x20000000. 9. fo r mob ile sdram initialization, an extend ed mo de register set (emrs) cycle must be issued t o progra m th e sdram parameters (tcsr, pasr , ds). the application must set mo de to 5 in t he mode registe r an d pe rfor m a writ e access t o t he sdram . th e wr ite addr ess mu st be chos en so that ba[1 ] or ba[0] are set t o 1. fo r example, wit h a 16-bit 12 8 mb sdram, (12 rows, 9 columns, 4 b anks) ba nk address the sdram w rite access shou ld b e don e a t the addre ss 0x2080000 0 or 0x20400000. 10. the ap p lication mus t go into norm al m ode , se tti ng mo de t o 0 in the mod e re giste r and performin g a writ e access at an y location in th e sdram. 11. write th e refresh rate into th e count fi eld in the sdramc re fres h timer register. (refresh rate = d elay between refresh cycles). t he sdra m device requir es a refresh ever y 15.62 5 us o r 7.8 1 us. wit h a 1 00 mhz frequency, the refr esh time r counte r reg- ist er mu st be se t with th e va lue 156 2 (15. 625 s x 1 0 0 mhz) o r 7 81 (7 .8 1 s x 10 0 mhz). aft er ini tiali zation, the s dra m devices a r e fully functional. 32058k avr32-01/12 416 at32uc3a figur e 28-4. sdra m device initialization sequence 28.6.2 i/ o li nes the pi ns used for interfacing t he sdram contro ller may be multiplexed with the pio lines. the programmer mus t f irs t program the pi o controller to assign the sdram controlle r pins to their peripheral function . if i/o lines o f the sdram controller ar e no t used by t h e applica tion, they can b e used fo r other purpose s by t he pi o controller. 28.6 .3 interrupt th e s dr a m c on tr olle r ha s an interru pt line con nected t o th e interru p t c ontroller . i n orde r t o ha n- dle i nterrupts, the inte r r up t c ont rol le r m u st be p rogr a mm ed be fo re c onf igurin g the sdra m controller. using t he sdram controlle r interrupt require s th e ic to be p rogramme d first.) sdck sdramc_a[9:0] a10 sdramc_a[12:11] sdcs ras cas sdwe nbs inputs stable for 200 sec precharge all banks 1st auto-refresh 8th auto-refresh mrs command valid command sdcke t rp t rc t mrd 32058k avr32-01/12 417 at32uc3a 28.7 functional description 28.7 .1 sdram controller writ e cycle the sdram co ntroller allows burst acce ss or sing le access. in both cases, the sd ra m control- ler keeps trac k o f the active ro w in each bank, th us maximizing performance. to initiate a burst acces s , t he s dr a m con t rol ler u s es the t r ans fer ty pe sig nal provided by the master requesting t he access . if the next access is a sequentia l writ e access, writing to the sdram device is c ar- ried out. i f the nex t acce ss is a write-sequentia l ac cess, bu t the current a ccess is to a boundary page , or i f the next acce ss is in anothe r ro w, then the sdram con trolle r generate s a precharge command , activate s the new row a nd initiates a write co mmand. to comply with sdra m timing parameters, addition al clock cycles ar e inserted between precharge/active (t rp ) co mman ds and active/write ( t rcd ) com m ands. f or definition of these ti ming parameters, refer to the ?sdramc configurat ion register ? on pag e 427 . this is described in figur e 28-5 below. figur e 28-5. w rit e b u rst, 32 - bit s dra m a cc e ss 28.7 .2 sdram controller read cycle th e sdram controller a llows burst access, incrementa l burst of unspecified length or single access. in al l case s, the sdram controller keep s track of the active row in each bank, thus maximizin g performanc e of the sdram. if row and bank addr esse s do not match the previous row/ban k add ress, then the sdram controller automatically generates a prech a rge command, acti vat es t h e ne w r ow an d starts th e rea d co m ma nd. t o comp ly wi th th e s dram timing pa r am- eters, additio n al clo c k cycl es o n sdck a r e in serte d b etw e e n pr ec h arg e a n d ac tive c omm ands (t rp ) a nd be t ween acti ve a nd read command (t rcd ). these two parameters ar e set in t he config- ur ation register o f th e sdram cont roller. after a read command, addition al wait st ates are generated to comp ly with th e cas late ncy (1 , 2 or 3 cloc k delays specifie d in the configuration register). sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rcd = 3 dna sdwe dnb dnc dnd dne dnf dng dnh dni dnj dnk dnl row n col a col b col c col d col e col f col g col h col i col j col k col l 32058k avr32-01/12 418 at32uc3a for a single access or an incr emen te d bur st of unsp ecif ied le ngth , t he sdram c ontroller an tici- pates the next access. while the las t value of t he column is returne d by t he sdram controller on th e bus, th e sdram controller an ticipates t he read to th e ne xt column and t hus anticipates t he cas late ncy. this reduces th e effect o f the cas la tenc y on the intern al bus. for burst access of s pecifie d lengt h (4 , 8, 16 words) , access is n o t anticipated. th is ca se leads t o th e best performance. if th e burst is b roken (border, b usy mode , etc.), t he next acce ss is han- dled as an inc rementin g burst of unspecified length. figur e 28-6. read bu rst, 32-bit sdra m access 28 .7.3 bor der manage m e nt whe n th e memo ry ro w boundary has been reached, a n automati c pa ge brea k is inserted. in this case, t he sdram con troller genera tes a precharge command, ac tivates th e new row a nd initi- ates a read or write command. to co mply wit h sdram timing parameters, an addition al clock cycle is i nserted between the precharge/active (t rp ) command and the active/read (t rcd ) com- mand. this is describe d in figur e 28-7 below. sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna sdwe dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2 32058k avr32-01/12 419 at32uc3a figur e 28-7. read bu rst with boundary ro w access 28.7.4 sdram con troll er refres h cycles an a uto-refresh comman d is used to refresh th e sdram device. refresh addresses ar e gener- at ed int ernally by t he sdram de vice and incre mented af ter each auto-refres h automatically. th e sdra m con trolle r generat e s th ese auto- refr esh comm a nds periodically. an in tern al ti mer is loaded wi t h the value in t he regist er tr that indicates t he number of clock cycles be tween refres h cycles. a r efr esh error in terr upt is g enerate d when th e pr evio us auto -refre sh co m ma n d did not perfo rm. it is a cknowl e dged by r ea ding the inter r upt stat us regist er (isr ). when the s dram co ntroller initiate s a refresh o f th e sdra m devi ce, inte rnal memory accesses a re not dela ye d . how e ver , i f t he cp u t ries to a cce s s the s d ram , t he s lav e ind ica t e s that t h e device is busy an d the mast er is hel d by a wait signa l. see figur e 28-8. sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rp = 3 sdwe row m col a col a col b col c col d col e dna dnb dnc dnd t rcd = 3 cas = 2 col b col c col d dma dmb dmc dmd row n dme 32058k avr32-01/12 420 at32uc3a figur e 28-8. re fres h cycle follo wed by a rea d access 28.7.5 power management thre e low-powe r mode s ar e available: ? self-refres h mode: th e sdram executes its own auto-refresh cycle without contro l of the sdr am controller. current d rained by the sdram is very low. ? pow er-do w n mode: au to- ref re sh cycles ar e con tro lled by th e sdram controller. between aut o-r efre sh cycle s , th e sdram is i n powe r-d own . curren t dra i ned in power-dow n mode is higher than in sel f-refres h mode. ? deep power-down mode : (only availabl e wit h mobile sdram) th e sdra m conten ts ar e lost, bu t th e sdram do es no t d rain a n y curr ent. the sdra m controller activate s on e low-power mod e as soon as the sdra m de vice is not selected . i t is possible to delay th e entr y in self-refresh an d power-down mode after the last access by programming a timeou t valu e in th e lo w power register. 28.7.5.1 self-refres h mode this mode is s elected by p rogramming th e lpcb fiel d to 1 in the sdramc lo w power register. i n self-ref resh mode , th e sdram device re tains dat a with out exte rnal clockin g and prov ides its own in ternal clocking, thus performing its ow n a uto-r e fre sh cycle s. a ll t h e i nputs to t he sd ram device beco me ?don?t care? except sdcke, whic h remain s low. as soo n as t h e sdram device is s elected , th e sdram controlle r provides a sequen ce of commands an d exit s self-refresh mode. som e low-powe r sdrams (e.g., mob ile sdram) can r efr esh onl y one quarte r or a hal f quarter o r a ll ba nks o f th e sdram arra y. this featur e reduces t he self-refresh current. to c onfigure this feature, tempera ture compen sated self refr esh (tcsr) , part ial array self refr esh (pasr) and drive streng t h (ds) parameters must be set in the low power regis t er and trans mi tted t o t he low-powe r sdram dur i ng i ni ti al izati on. sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d cas = 2 row m col a t rc = 8 t rcd = 3 dma row n 32058k avr32-01/12 421 at32uc3a aft er ini t ializati on , as soon as pasr/ds/tcs r fields are modif i ed and self-r efresh mode is acti- vated, the extended m o de register is accessed automatic ally and pas r/ds/tcsr bits ar e update d befo re entry int o self-refresh mode. th e sdram device must rema in in self- r efresh mo de for a minim um per io d of t ras an d may remai n in self-refres h m o d e for a n indefinit e period. t h is is de scribe d in figur e 28-9. figur e 28-9. self-re fres h mode behavior 28.7.5 .2 low-po we r mo de this mode is s elected by p rogramming th e lpcb fiel d to 2 in the sdramc lo w power register. powe r consumption is g reater than in self- refre sh mode . all the inpu t an d output buffe rs of the sdram device are d eactivated exce pt sdcke, which remains low. in c ontrast to self-refres h mode, th e sdram device cannot remain in low -power mod e longer than the refresh period (64 ms f o r a wh o l e de vice re fres h ope r a t io n ) . as n o auto-re f resh op erati ons a r e per fo rm ed b y t he sdram itsel f , th e sdram controller carr ies out t he refr esh operation. the exit procedure i s faster than in self-refres h mode. this is described in fig ur e 28-10. sdck sdcs ras cas sdramc_a[12:0] self refresh mode sdwe row t xsr = 3 sdcke write sdramc_srr srcb = 1 access request to the sdram controller 32058k avr32-01/12 422 at32uc3a figur e 28-10. l ow-powe r mod e behavi or 28.7.5.3 d e e p power- dow n mo de this mode is s elected by p rogramming th e lpcb fiel d to 3 in the sdramc lo w power register. when this mode is activated, all in ter nal voltage generato rs inside th e sdram are stoppe d and all data i s lost. when th is mode is enabled, th e application must not access to th e sdram until a ne w initializa- ti on sequence is d on e (see ?sdram device initializ ation? on page 415 ). thi s is described in figu re 28- 11. sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2 sdcke low power mode 32058k avr32-01/12 423 at32uc3a figur e 28-11. deep power-down mode behavior sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d row n cke 32058k avr32-01/12 424 at32uc3a 28.8 sdram contro ller user interface tabl e 28-8. sdra m controlle r memory map offset register name access res et state 0x00 sdramc mo de register mr read/write 0x00000000 0x04 sdramc re fr es h timer register tr read /write 0x000 000 00 0x08 sdramc configuration register cr read/write 0x852372c0 0x0c sdramc h igh spee d register hsr read/write 0x00 0x 10 sdram c l ow powe r r egister lpr re ad /wri te 0 x0 0x 14 sdram c i nterr up t en a b le register ier wri te-only ? 0x 18 sdram c interrup t di s abl e r e gist er i dr write-on ly ? 0x1c sdramc inter rup t mask register imr read-only 0x0 0x20 sdramc inter r up t status r egister isr re ad-on ly 0x0 0x24 sdramc memo ry device register mdr read/write 0x0 0x 28 - 0xfc reserved ? ? ? 32058k avr32-01/12 425 at32uc3a 28.8 .1 sdramc mode register register name: mr acces s type: read/write rese t va lue: 0x00000000 ? mode: sdramc co mm and mode this fiel d defines t he command issued by t h e sdram controller when the sdra m de vice is accessed. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? mode tabl e 28-9. mode description 0 0 0 no r mal mode . a n y access to the sdram is deco d ed no r mall y. 0 0 1 t he s dram co n tr olle r i ssu e s a no p c o m m a n d w h e n th e sdra m d evi c e i s a c c ess ed r eg ar dle s s o f t he cy cle. 0 1 0 th e sd ram contro ller issues an ?all bank s precha rge? comma nd when the sdra m de vice is accessed regardl ess of the cycle. 0 1 1 th e sd ram contro ller issues a ?loa d mo de register ? command w hen the sdram devi ce is accessed regard less of the cycle. the command wil l load the ca s l atency from the configuratio n re gister and ever y other valu e set to 0 into t h e mo de re gister. 1 0 0 th e s d ram contr olle r iss ue s a n ? a uto- re fres h ? co m mand wh en the sdram devi ce is acce ssed regard less of th e cycle. previously , an ?all banks precharge ? command must b e issued. 1 0 1 th e sdram controll er issues an extended lo ad mo de regi ster comma nd when the s d ram de vice is accessed regard less of th e cycle. the comma nd wi ll lo ad the p asr, ds an d tcr from the low powe r re gister and every other valu e set to 0 into th e exten ded mode register. 1 1 0 dee p power-do wn mode . ente rs de ep power-down mode. 32058k avr32-01/12 426 at32uc3a 28.8.2 sdramc refresh time r register register name: tr acces s type: read/write rese t va lue: 0x00000000 ? count : sdramc refr esh time r count this 12-bi t fi eld is loaded into a timer that generates the refresh pulse. each time th e refresh pulse is generated, a refresh burst is ini tiated. t he valu e t o be loaded depends on th e sdramc clock frequency (m ck: master clock) , th e refr esh rate of t he sdram devic e and th e refr esh bur st length wher e 15.6 s pe r ro w is a ty pical value for a bu r st of length one. to refresh the sdram device , th is 12-bit field must be writ ten. i f this co nd ition is not satisfi e d, n o ref r esh co mmand i s issue d an d no refr esh of th e sdram device is c arrie d out. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? count 7 6 5 4 3 2 1 0 count 32058k avr32-01/12 427 at32uc3a 28.8.3 sdram c configuration register register name: cr acces s type: read/write rese t va lue: 0x852372c0 ? nc: nu mber of co lumn bits reset va lue is 8 co lumn bits. ? nr: nu mber of ro w bits reset va lue is 11 row bits. ? nb: nu mber of banks reset va lue is two banks. 31 30 29 28 27 26 25 24 txsr tras 23 22 21 20 19 18 17 16 trcd trp 15 14 13 12 11 10 9 8 trc twr 7 6 5 4 3 2 1 0 dbw c as nb nr nc nc column bits 0 0 8 0 1 9 1 0 10 1 1 11 nr ro w bits 0 0 11 0 1 12 1 0 13 1 1 reserved nb number of banks 0 2 1 4 32058k avr32-01/12 428 at32uc3a ? cas: cas lat ency reset va lue is two cycles. in t he sdramc, only a cas lat enc y o f one , t w o a n d thre e cycles is ma nage d. ? dbw : data bus width reset va lue is 16 bits 0: da t a bu s width is 3 2 b its. 1: da t a bu s width is 1 6 b its. ? tw r: write recovery delay reset va lue is two cycles. this field define s the write recovery time in num b er of c ycles. number of cycles is be tw een 0 and 15. ? tr c: ro w cycle delay reset va lue is seve n cycles. this field de f ines th e delay be tween a ref resh and a n activate comma nd in numbe r o f cycles. num b er o f cycl e s is betwe en 0 a nd 15. ? trp: ro w precharg e delay reset va lue is three cycles. this fi eld defines the delay between a precharge co mmand and another command i n number of cycles. number o f cycles i s be tween 0 an d 1 5. ? trcd: ro w to column delay reset va lue is two cycles. thi s field defines the dela y between an activate comman d and a read/write command in number of cycles. number o f cycle s is betwee n 0 an d 15. ? tras: active to p rec harg e de lay reset va lue is five cycles. this fi eld defin es the delay between an activa te command a nd a precharge command in number o f cycles . number of cycle s is betwee n 0 an d 15. ? txsr: exit self ref re sh to active delay reset va lue is height cycles. this field defines the delay between sck e set hi gh and an a ctivate command in num b er of cycles. number of cycles i s betwe en 0 a nd 15. cas cas l a tenc y (cycle s) 0 0 reserved 0 1 1 1 0 2 1 1 3 32058k avr32-01/12 429 at32uc3a 28.8. 4 s dra mc h ig h sp ee d regi st er register name: hsr acces s type: read/write ? d a: decode cycl e enable a dec o de cycle ca n be adde d on t he addresses as soon as a n on-sequenti al access is p erforme d on th e hsb bus. th e additi on of t he decode cycle allows th e sdramc t o gain time to access the sdram memory. 0: decode cycle is disabled. 1: decode cycle is enabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? da 32058k avr32-01/12 430 at32uc3a 28.8.5 sdramc l ow powe r register register name: lpr acces s type: read/write rese t va lue: 0x0 ? lp cb: lo w- po wer con fi g uratio n bi ts ? pasr: part ial arra y self-ref resh (only for low-po wer sdram) pasr parameter is transmitted to the sd ra m during initialization to specify wh ether only one quar ter, one half or all banks of t h e sdra m arra y are enabled . disable d ban ks are not refresh ed in self-refres h mode . this paramete r mu st be set accordin g to the sdram device specification. afte r initialization , as soon as pasr fiel d is modified and self-refre sh mode is activated, the ex tended mode register i s accesse d au tomatica l ly an d pa s r b its ar e up d ate d befor e entr y i n self- r efres h mod e. ? tcsr: temperature compensa ted self-refre sh (only fo r low-powe r sdram) tcsr par ameter is t ransmitted t o th e sdram during initialization to set t he refr esh interv al dur ing self-refr esh mode dependin g on t he temperature of the low -power sdram. th is paramet er must be set according t o t he sdram device s peci ficat ion. afte r initialization , as soon as tcsr fi eld is modified and self-refre sh mode is activated, the extended mo de register is accessed automa tically an d tcsr bits ar e updat ed befor e entr y in self-refresh mode. ? ds: drive strength (on l y fo r l ow-po wer sdram) ds parameter i s transmitted to the sdram during initiali z ation to select t he sdram strengt h of dat a output . th is parame- te r mu st be se t according to the sdram device speci fication. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? timeout ds tcsr 7 6 5 4 3 2 1 0 ? pasr ? ? lpcb 00 low power f eature is inhibited: no power-do wn, self-refresh or dee p power-do wn comma nd is issu ed to the sdram device. 01 the sdram c ontrolle r issues a se lf-refresh command to the sdram device , th e sdclk cloc k is deact iva ted an d the sdck e sig n al is set l o w. t he sdram devic e leaves the self refresh mode w hen accessed and enters it after the acces s. 10 the sdram c ontrolle r issues a power-do wn command to the sdram device af ter eac h access , the sdcke sign a l is se t to low. the sdram d e vice leav es the power-do wn mode wh en accessed and ente rs it after the acces s. 11 t h e s dra m c on t rolle r issu e s a deep pow er - dow n com m an d to the sdra m d e vice. t h is m ode is unique to l ow-powe r sdram. 32058k avr32-01/12 431 at32uc3a after initialization, as so on as ds f i eld is modifi ed and self-refresh mode is ac tivated, t he extend ed mode regist er is accessed automa tically an d ds bits ar e updat ed before entry in sel f-refre sh mode. ? timeout: ti me t o define wh en low-po wer mode is ena bled 00 the sdram c o ntro ller activ a tes the sdram low-p owe r m o de immediately af ter th e end of t h e last transfer. 01 the sdram controller acti va tes the sdram low-power mo de 64 clo c k cycles aft er the end of the last transfer. 10 the sdram controller acti va tes the sdram low-power mo de 128 cloc k cycles after the end of the last transfer. 11 reserved. 32058k avr32-01/12 432 at32uc3a 28.8.6 sdramc inte rrupt enable register register name: ier acces s type: write-only ? res: refresh er ro r status 0: no effect. 1: en ab les th e re fr esh e rro r interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? res 32058k avr32-01/12 433 at32uc3a 28.8 .7 sdramc interrupt disabl e register register name: idr acces s type: write-only ? res: refresh er ro r status 0: no effect. 1: disables the refres h erro r interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? res 32058k avr32-01/12 434 at32uc3a 28.8 .8 sdramc interrupt mask register register name: imr acces s type: read-only ? res: refresh er ro r status 0: th e re fr esh er ro r inte rru pt is disab le d. 1: the refr esh erro r interrupt is enabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? res 32058k avr32-01/12 435 at32uc3a 28.8 .9 sdramc inte rrupt stat us register register name: isr acces s type: read-only ? res: refresh er ro r status 0: no refr esh erro r has bee n detect ed since the register was las t read. 1: a refr esh erro r ha s been detected since t h e regist er was last read. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? res 32058k avr32-01/12 436 at32uc3a 28.8.10 sdr amc memo ry device register register name: mdr acces s type: read/write ? md: memo ry device type 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? md 00 sdram 01 l ow- p ow e r sd ram 10 reserved 11 reserved. 32058k avr32-01/12 437 at32uc3a 29. e thernet ma c (macb) re v: 1.1.2.5 29.1 features ? compatible with ieee standard 802.3 ? 10 and 1 0 0 mbit/s oper ation ? full- and half-dupl e x operation ? statistics counter registe rs ? mii/rmii interfa c e to the phys ical layer ? interrupt gener a tion to signal re ceive and tr ansmit completion ? dma maste r on re ce ive and tr an sm it channels ? transmit an d re ceive fifos ? automatic pa d an d crc generatio n on transmitted frames ? automatic discar d of fram es re ceived with errors ? address chec king logic suppor ts up to four specific 48-bit addresses ? suppor ts promiscuous m ode wh ere all vali d recei v ed frames are copied to me mo ry ? hash mat c hing of unicast and multicas t destination addresses ? exter n al ad dres s matc hing of rece ived fra m es ? physical layer management throug h mdio interface ? half-duple x flow control by forcin g collisions on incomin g frames ? full-duplex flow contr ol with recognition of incoming paus e fram es an d hardware generation of transmitted paus e frames ? su p po r t f or 802.1 q v lan ta gg in g w ith re co gniti o n o f i nc o min g v l an and pri ori ty tagg ed fra m es ? multip le b uf fer s p er r ece ive an d t r an smit frame ? wa ke-on -la n s up p o rt ? j umbo frame s u p t o 1 0240 b yte s suppor ted 29.2 description t h e m a cb modu le i mple m en t s a 1 0/ 100 etherne t m a c c omp at ible w i th t he ie e e 802 .3 st an- dard using an address che c ker, statistics and c ont rol registers, rece ive and transmit blocks, and a dma interfa ce. the addr ess checker recognizes four specif ic 48-bit addr esses an d contai ns a 64-bit hash regis- ter for matching mul t icast an d unicast add r esses. i t can reco gnize the broadcast ad dress of al l ones, copy all frames, an d act on an extern al addr ess ma tch signal. the s t atistics regist er block cont ains register s for counting va ri ous types of event s associated with transmit and rece ive operat ions. th ese register s, alo n g wit h th e sta tu s wo rd s s tored in the receive buffer list, en a ble software to gen e rate network managemen t statisti cs com patible with ie ee 802.3. 32058k avr32-01/12 438 at32uc3a 29.3 block diagram figur e 29-1. macb bl oc k diagram 29.4 p roduct dependencies 29.4.1 i/ o li nes th e pi ns used fo r int erfacin g th e comp lia nt external devices ma y be multip lexed wit h pio lines. the programme r mus t first program the pi o controllers to assign t he ma cb pins to thei r periph- eral functions. 29.4.2 power management th e macb clock is g e nerate d by the powe r ma nag er . before usin g th e macb , th e pr ogram mer must ensure that t he macb cloc k is enabled in the powe r manager. in the macb description , mast er clock (mck) is t he clock of the perip heral bus to which the macb is con nected. th e synchronizatio n modu le in th e macb requires that the bus clock (hclk) ru ns on at least the speed of the macb_tx/rx_clk, which is 2 5 mhz in 100mbps, and 2. 5mhz in 10m bps in mii mode an d 50 mhz in 100mbps, and 5mhz i n 10mb ps in rmii mode. t o prevent b us errors th e ma cb operat ion must be terminat ed befor e entering slee p mode. peripheral bus slave register interface dma interface address checker statistics registers control registers ethernet receive ethernet transmit mdio mii/rmii rx fifo tx fifo high speed bus master 32058k avr32-01/12 439 at32uc3a 29.4 .3 interrupt th e macb interface ha s an interr upt line conn ected to the interru pt controlle r. handlin g the macb i nt errup t req uire s progra mmin g t h e in terr upt con tro ller befo re co nfig urin g th e macb. 29.5 functional description figur e 29- 1 o n pag e 43 8 illustrates th e different blocks o f the macb module. t h e co ntro l reg i ster s driv e th e mdio interface , se tu p dma activity , star t fra me tr an smission and select mode s of operatio n su ch as fu ll- o r half-duplex. th e receiv e bl ock checks for va lid preamble, fcs, ali gnment and length, an d presents received fram es to the addre ss ch ecking bloc k an d dm a interface. the transmit block takes data from th e dma interface, adds preamble and, if necessary, pad and fcs, a nd transmits data accord ing to t he csma/ cd (carrier sense mul tiple access wit h col- lisio n detect) protocol. the star t of transmission is d eferred if crs (carrier sense) is active. if col (collision) becomes activ e du ri ng tr an smiss io n, a ja m se quence is as se rted and the transmission is r etried after a r and om back off. cr s and col have no effec t in fu ll duplex mode. th e dm a bloc k connects t o extern al memo ry through its high spe ed bus (hsb) interface. it con- tains rece iv e an d tra nsmit fifo s fo r buffe rin g fram e da ta. it loads th e transmit fi fo a n d empt ies the receive fifo using hsb b u s master operations. receive d ata is not sent to memo ry until the addr ess checkin g logic has determined t hat the f rame sho uld be copied. receive or transmit frames are sto r ed in one or more buffers . receive buffers have a fixed length of 128 by tes. tran smit buffe rs rang e in leng t h b etwee n 0 an d 2 04 7 by tes , a nd up to 1 28 buff ers ar e permit ted per frame. the dma block m anages the transm it and receive fram ebuffer queues. these queues can hold multiple frames. 29.5.1 memory interface frame dat a is transferred to and from the macb through t he dma interface. all transfers ar e 32- bit word s and may be sing le accesses or bursts of 2, 3 or 4 w ords. burst accesses do no t cross sixteen-byt e boundaries. bursts o f 4 wo r ds are t he defaul t data transfer; single accesses or bu rst s o f le ss t han fo u r wo rds ma y be use d t o t r an sfe r dat a a t th e begi n n ing o r t he en d o f a buffer. th e dm a cont rolle r p erfo r ms six types of operat ion on th e bus . i n or de r of prio rity, th ese a r e: 1. recei ve buf fe r mana ge r write 2. recei ve buf fe r mana ge r re ad 3. transmit dat a dma read 4. receiv e data dm a write 5. transmit buffer manage r read 6. transmit buffer manage r write 29.5.1 .1 fifo th e fi fo dept hs ar e 12 4 bytes. d at a is ty p ical l y t ransfer re d int o a n d out o f t h e fifo s i n bursts of four word s. fo r r e ceiv e, a bus requ est is asserted when the fifo contains four word s an d ha s space for thre e more. for trans- mit , a bu s reques t is generated when ther e is spac e fo r fo ur words, or when ther e is spac e for two word s i f th e nex t transfer is t o b e on ly on e or two wo rds. 32058k avr32-01/12 440 at32uc3a th us th e bu s latency must be less t han the ti me it takes to load th e fifo and transmit or receive three word s (1 2 bytes) o f data. a t 1 0 0 mb it/s, it tak e s 9 6 0 ns t o transmit or re ceive 12 byt e s o f da ta . in additio n , six master cloc k cycles should be allowe d for d ata to b e loaded fro m the bus a nd to propagate through the fifos. for a 6 0 mh z master clock th is takes 100 ns, making the bu s latency requiremen t 860 ns. 29.5.1 .2 receiv e buffers received fr ames, op tionally in cluding crc/fcs, ar e writte n to re ceive buffers stor ed in mem- or y. each re ceive buffer is 12 8 b yte s long. t he start location fo r ea ch re ceive buffer is s tored in memory in a lis t of receive buffer descriptors at a location pointed to by the receive buffer queue poin ter register . th e receive buffer star t location is a wo rd address. for th e first buffe r of a frame, t he star t locati on can be offset by up to three bytes depending on the va lue written t o bits 14 and 15 o f t h e netw ork co nfi guratio n regi ste r . if th e s ta rt l o ca tion of th e buffe r i s o ffs e t the availabl e length of th e first buffe r of a frame is r educe d by the correspondin g number of bytes. each list ent ry co nsists of two word s, the first b ein g th e addr ess of th e receiv e buffe r and the second bei n g the receive s tatus . if the length of a receive frame exceeds the buffer length, the stat us word for th e used buffer is wri tt en with zer oes except for th e ?start of frame? bit and the offset bits, if appropriate. bit zer o of the address field is w ritten to one to sh ow th e buffer has been used. t he receive buffer manager then reads t he location o f t he next receive buf f er and fi lls that wit h receive fram e data. the fi nal buffer descripto r stat us word contains t he complete frame status. refe r to ta ble 29- 1 fo r deta ils of th e re ceive buffe r descripto r list. tabl e 29-1. receive buffer descriptor entry bit function wor d 0 31:2 addres s of beginni ng of buffer 1 wr ap - mar ks last descr iptor in r ece ive b u ff e r des crip tor lis t. 0 ownership - n e eds t o be zero fo r the ma cb to wr ite data to the receive buffer . the ma cb sets this to one o n ce it has successfully writ ten a fr ame to memory. software ha s to clea r this bi t befo re the buff er can be used again. wor d 1 31 globa l all ones broadcas t address detected 30 multicast hash match 29 unic ast ha sh match 28 extern al add ress match 27 reserved fo r future use 26 specific ad dress re gister 1 match 25 specific ad dress re gister 2 match 24 specific ad dress re gister 3 match 23 specific ad dress re gister 4 match 22 type id match 21 vlan tag detected (i. e ., type id of 0x8100) 32058k avr32-01/12 441 at32uc3a to receive f rames, th e bu ffe r desc ripto rs must be initialized by wr it in g a n appro pria te addr ess to b its 31 to 2 i n th e first wor d o f ea c h list e nt ry . bit z e r o must b e writt e n wit h zero . b it o ne i s t h e wrap bit and indicate s th e last entr y in th e list. th e star t locati on o f the receive buffer descripto r list must be written to the re ceive buffer queue pointer register before se tting t he receive enable bit in the network control register to enabl e receive. as so on as t he receive bl ock starts writin g received fram e data to th e re ceive fifo , the receiv e buff er mana ger reads t he first rece ive buffer locatio n pointe d to by the r eceive buffer queu e pointer register. if t h e filter bloc k then indicates that the fra m e should b e co pied to memo ry, the receive data dma operation starts writing data into the receive buf f er. if an error occurs, the buffer is recov- ered. if t he c urrent buffer pointer h as it s wr ap bit se t or is th e 1024 t h descriptor, the next receive buffer location is r ead from the beginning o f th e receive descriptor list. otherwise , the next re ceive buffer location is r ead from th e next word i n memory. t h er e is an 11-b it co u nter to cou nt out the 2 048 word locations of a max i mum le ngth, receive b uf f er d esc ripto r list . thi s is a d ded wit h t he v al ue original ly written to t he rece ive buffer queue pointer register to produce a pointer into th e list. a re ad of the re ceive buffer queue pointer reg- ister return s th e pointer value, which is t h e queu e entr y currentl y being accessed. the counte r is rese t after rece ive status is w ritten t o a descriptor that ha s it s wr ap bit se t or rolls over to zero after 1024 descriptor s have been accessed. th e valu e written to the receive buffer pointer regis- t er may be an y word-aligne d address, provided that there ar e at least 2 0 48 word locations availabl e between the pointe r an d the t op of t he memory. th e system bus s pecificatio n stat es that bursts should not cros s 1k boundaries. as r eceive buf- fer manager writes ar e bur sts o f tw o words , to ensure tha t this d oes not occur, it is b e st to write the pointer register with the l e ast thr e e significan t bits set to ze ro. as receive buffers are used, the re ceive buffe r manage r sets bi t zero of the first w o rd of the de scriptor to indicate used . if a receive erro r is detected the receiv e buffe r currentl y being writte n is recovered. previo us buffers are no t recovered. softwar e sho uld search through the used bi ts in the buffer descriptors to find out how many f r ames have bee n received. it sh ou ld be checkin g the start-of-fra me and end-of- frame bits, and not re ly on the value returned by t he receive buffer queue pointer register which change s continuou sly as more buffers ar e used. 20 prior ity tag detected (i.e ., type id of 0x810 0 and null vlan identifier) 19:17 v lan prior ity (only vali d if bi t 21 is set) 16 concatenation format indi cator (cfi) bi t (only valid if bit 21 is set) 15 end of f ra m e - when se t the buf f e r c o n t ain s the en d o f a fram e. if e n d of frame is n o t set, then the o nly other valid status are b i ts 12, 13 an d 14. 14 star t of fr ame - wh en set the buff er contains th e star t of a frame. if b o th bits 15 a nd 14 are se t, then the buffer contains a whol e frame. 13:12 receive buffer offse t - indicate s the numb er of bytes by which the data in the first buffer is offs et from the wo rd address. updated with the c urrent values of the net work configuratio n register . if jum bo fram e mode is e nabl ed through b it 3 of the networ k configuratio n register , th en bits 13: 12 of th e receive buffer descr iptor entry are us ed to i n dicate bits 13:12 of the fr ame length. 11:0 le ngth of frame includ ing fcs (if selected ). bits 13:1 2 are also used if jumb o frame mo de is selected. tabl e 29-1. receive buffer descri pto r entr y (continued) bit function 32058k avr32-01/12 442 at32uc3a fo r crc errore d frames, e xcessive leng th fram es or leng th field mismatched frames, al l of which are cou nte d in th e statistic s re gister s , it is po ssible th a t a fra me fr ag m en t might b e stored in a s eque nce of re ceive buffers. software can detec t this by looking for star t o f fram e bit set in a buffe r follo wi n g a buffe r wit h n o e n d o f frame bit set. f or a p r operl y w ork ing e the r net s ystem , t h ere s houl d be no e xc es siv e l y long f ram es o r frames greater than 128 bytes with crc / fcs errors. collision fragments a r e le ss tha n 128 by t es long. therefore, it is a rar e occurrence to fin d a frame fragment in a rece ive buffer. if bit zer o is se t wh en th e rece iv e buff er manage r read s t h e loca tio n of th e receiv e b uff e r, then the b u ffer has already be en used an d ca nnot be used a gain until software ha s processe d the fram e an d cleare d bi t zero . in th is case , th e dma bloc k se ts th e buffer no t available bit in the re ceive status register and trigge rs an interrupt. if bit z e ro is se t whe n the receiv e buff er manag er read s the location o f the r eceive buff er and a fram e is being received , the fram e is discard ed and the receive resour ce erro r statistics register is i ncremented. a rece i ve overrun condition occurs when bus wa s no t gr ante d in tim e o r b e cau se hresp wa s no t ok ( bus error). i n a receive ove rrun condition, th e receive overru n interrupt is asserte d and the buffer currently b eing writ te n is r ec o vered. the next frame received with an address that i s recogn ized re uses th e buffer. if bit 17 of th e networ k configuratio n register is s et, the fc s of received fram es sh all not be cop- ied to memory. t he fram e len gth indica ted in the receive status fiel d shal l be reduce d by four bytes in this case. 29.5.1.3 transmit buffer frames to be transmitted are stored in o ne or more transmit buffers. transmit buffer s can be between 0 and 2047 by t es long, so it is p ossible to transmi t frames longer tha n the maximum length specified in i eee standard 802.3. zero length buffers are allowed. the maximu m number of buffers permitte d fo r each transmit fram e is 128. th e start location fo r each transm it buffe r is stored i n mem ory in a list of transmit buffe r descrip- tors at a loca ti on pointed to by t h e transm it buffe r que ue pointe r register. each list entr y consists of two wor ds, th e first being the byt e addres s o f the tra nsmit buffer and t he seco nd containing t he tr ansmit cont rol an d status. frames can b e transmitte d wit h or without auto matic crc gen- eratio n. if cr c is automatically generated , padding is also automa tically generated to take frames to a m inimu m lengt h o f 6 4 bytes. ta ble 29-2 o n page 443 defi nes an entr y i n th e tran smit buffer descriptor list. to t ransmit frames , t he buff er descriptors m ust be initialized by writing a n appropriate byte address to bits 31 to 0 in t he first word of each lis t entry . th e second transmit buffer descriptor is ini t ialized with contro l inform a ti on that indicates the length of the buffer, whether or not it is to be transm itted wi th crc and whether the buffer is t he l ast b u ffe r in th e frame. afte r transmission , th e control bi ts ar e written ba ck to the second word of t h e firs t buffer along with the ?us e d? bit a nd othe r sta tus informatio n. before a tr a nsmission, bit 3 1 is the ?u sed? bit which must be zero when t he cont rol word is read. it is writt en t o one when a frame has been transmitted. bits 27, 2 8 a nd 29 indicate various transmit error conditions. bit 30 is th e ?wrap? bit which c an b e se t fo r any buffer within a frame . if no wrap bit is e ncountered after 1024 descrip- tors, th e queue pointe r ro lls over to the start. th e tran smit buffe r que ue poin ter re gister must no t be written while transm it is ac tive. if a n ew valu e is written to th e transmit buffe r queue pointer register , th e queue pointer resets itse lf to 32058k avr32-01/12 443 at32uc3a poin t to the b eginni ng of the n e w qu eue . i f tr a nsmit is d isable d by writi ng t o bit 3 of the net w ork control , t he transmit buffe r queue pointer register resets to point to the beginning of the transmit queue. note that disabling receive d oes not have the sa me effect o n th e receive queue pointer. onc e th e transmi t queue is i nitializ ed, transmit is activated by writing to bit 9, the transmit start bit of the networ k contro l register. transm it is halted when a bu ffer descriptor with its used bit se t is read , or if a tra nsmit error occu rs, or by w riting to the transmit halt bit of the networ k control register. (transmissio n is suspended if a pause fra me is received while the pause enable bit is set i n the n etw ork configurat ion register. ) rewriting t he star t bit while transm ission is active is allowed. transmission contro l is implemented with a tx_g o variab le which is r eadable in t h e transmit sta- tus register at bit locati on 3. the tx_ go variab le is reset when: ? transmit is dis abled ? a buffer descriptor with its ownershi p bi t set is r ead ? a n ew valu e is writte n to th e transmit buffer queu e pointe r register ? bit 10, tx_halt, o f th e network control register is written ? there is a transmit error such as t o o many retries or a t ransm it underrun. to set tx_go, write to bi t 9 , tx_start, o f t he net work control r egister. transmit halt does not take effec t until an y ongoin g t ransmi t finishes. if a collision occur s du ring transmission of a multi-buf- fer fra m e, transmission a utomatically restar ts fr o m the first buffer of the fra me. if a ?used? bit is read mi dway throug h transmission of a multi-bu ffer frame , this is treated as a tra n smit error. t ran sm i ssi o n stops , tx _e r is a sserted a nd th e fc s i s bad. if transmission stop s due to a t ransmit error, the transmit queue point er resets to poin t to the beginning o f the transmit queue. softwa re needs to re-initialize the transmit queue after a t rans- mit error. if tr ansmission stops due to a ?use d? bi t being re ad at the start of the frame , the transmission queue p oi nter i s no t re set and t ra n smit star ts fro m t h e sam e transmit buff e r d escripto r whe n the tran s mit s t art bit i s writt en tabl e 29-2. transm it buffer descriptor entry bit function wor d 0 31:0 byt e addre ss of buffer wor d 1 31 used . ne eds to be zero fo r the ma cb to re ad data from the t ran smit buffer. the ma cb sets this to one fo r the first buffer of a frame once it has be e n successfu lly transmitted. softw are has to clea r this b it befo re the buff er can b e us ed again. note: t his bit is on ly set fo r the first buffer in a frame unlik e receiv e where all buffers have the used bit set o nce used. 30 wrap. mar ks last descr iptor in transmit buff er descripto r list. 29 retr y limit exceede d, tran smit error detected 28 transmit underrun, occurs either wh en hresp is not ok ( bus error) or the t ransmit data co ul d not be fetched in time or when buff ers are exhauste d in mi d frame. 27 buffers exhausted in mid frame 26:17 reserved 32058k avr32-01/12 444 at32uc3a 29.5.2 transmit block this block transmits fr ames in accordance wit h the ethern et ieee 802.3 csma/cd pro tocol. fr ame ass e mbly sta rts by addin g p ream ble and t he star t fram e delimite r . dat a is take n fr o m the tr ansmit fifo a word at a time . data is transm itt ed least signif icant nibble first. if necessa ry, padd ing is added t o increase the frame length to 60 bytes . crc is c a lculated as a 32-bit polyno- mial . this is inverte d an d appended to th e en d of the frame , taking the fram e lengt h to a minimum of 64 by tes . if the no crc bi t is s e t in th e second word o f the la st buffe r descripto r of a tra nsmi t fr ame, neit he r pa d n o r crc a r e appende d. in full-dup lex mode, fram es are transmitted immediately. back-to- back frames are transmitted at leas t 9 6 bit ti mes apart t o guarantee the interfram e gap. in half - duplex mode , th e tr an smitte r checks ca rr ier sense. if ass erted , i t wait s fo r it to de-asser t and then st arts transmission afte r the interframe gap of 96 bit ti mes. if the collision si gnal is asserte d durin g transmission, the transmitter transmits a ja m seque nce of 32 bi ts take n from the data registe r an d retr ies transmissio n afte r th e ba ck o ff tim e has elapsed. the back-of f time is ba sed on an xo r o f the 10 le ast significant bits o f th e data coming from the trans mi t fif o and a 10 -bi t pse u do rand o m num b er. t he nu m ber of bi ts used depe nds o n the number of co llisions se en. after the first collis ion, 1 bit is used, after the second 2, and so on u p t o 10 . abov e 10, all 1 0 b i ts ar e used . an error is in dicate d an d no further attempts are made if 1 6 attempts c ause c ollision s. if transmit dma u nderruns, ba d crc is automati cally appende d using t he sa me mechanism as jam insert ion and t he tx_er signal is asserted. in a properly configured syst em, this should neve r ha ppen. if th e b a ck pressure bi t is se t in th e netwo rk control register in h alf duplex mode , th e transmit block transmits 64 bits of data, which ca n consist of 16 nibb les of 1011 or i n bit-rate mode 64 1s, when e ver it see s an i n com ing fra m e to fo rc e a col l ision. this p rovi de s a w a y o f i mp l em enting fl ow contro l i n half-duplex mode. 29.5.3 pau se fra me support the star t of a n 802.3 paus e fram e is as follows: t he network configuration register con tains a re ceive paus e enable bit (13) . if a vali d pause fram e is received , t he pause time regist er is updated with the frame?s p ause time, regard less of 16 no crc . wh en set, no crc is append ed to the c urren t frame. this bit o nly n eeds to be set fo r the last buffer of a frame. 15 last buffer. when set, this b i t indi cates the last buffer in the curren t fram e has b een reached. 14:11 reserved 10:0 le ngth of buffer tabl e 29-2. transm it buffer descripto r entr y (continued) bit function tabl e 29-3. start of an 802. 3 paus e frame de stination address source address type (mac contro l frame) p a use opcode paus e time 0x0180c2000001 6 bytes 0x8808 0x0001 2 bytes 32058k avr32-01/12 445 at32uc3a it s current contents an d regardle ss o f th e state o f the configuratio n register bi t 13 . an interrupt (12 ) is trigge red wh en a pause f rame is received, assuming it is en a bled in t he interrupt mask register . if bi t 13 is s e t in the netw ork configur atio n regis te r an d t he valu e of th e pa us e ti me reg- ister is no n-zero, no n ew frame is transmitted until the pause ti me register ha s decremented to zero. th e loading of a ne w pause time, and hence the pausing o f transmission, on ly occurs when the macb is co nfigured for full-dup lex operation. if th e macb is configured for half-duplex , ther e is no transmission pause , but the pause frame received interrupt is st ill triggered. a vali d pa use frame is define d as havin g a destinat ion address that matche s either the address stored in s p ecific addr ess regist er 1 o r matche s 0x0 1 80c2 00 0 001 and has th e mac c ontrol frame typ e id of 0x8 8 08 a nd th e p aus e o pco de of 0x0001. pause fram es that have fcs o r other er rors ar e treate d as invali d a nd ar e discarded . valid pa use frames received increment the paus e fr ame rece ived statistic re giste r. th e p ause time registe r decremen ts every 5 12 bit times (i.e., 128 rx_ clks in nib bl e mode) once transmission ha s stopped. for test purposes, the register decremen ts every rx_clk cycle once transmission ha s stopped if bit 12 (retry test ) is set in the networ k configuration register. if the pause en abl e b it (13 ) is n ot set i n th e n etwork configu rati on register, the n th e d ecrem en tin g occurs regardless of whether transmissi on ha s stopp ed or not. an i nter rupt ( 13 ) i s a sse rted whene ver th e pa us e tim e register decrements t o zer o (ass umin g it is enab led in t he interru pt ma sk register). automatic tran smission of pause fr ames is supported throug h the transm it pause fram e bits o f th e net work con trol registe r and the t x_p ause and tx_pause_zero inputs. if eithe r bi t 11 or bit 12 of t he networ k contro l register is w ritten to with a 1 , or if t he input signal tx_pause is toggled, a pause fram e is transmitte d only if full duplex is selected in t h e net work configuratio n registe r an d tr ansmit is ena bled in the networ k control re g is ter. paus e frame transmission occu rs immedia tely if trans mit is inactive or if t ransmi t is active betwee n the curre nt fram e and th e ne xt fram e du e t o be transmitted. t he transmitte d pause fra me is comprise d of the items in the following list: ? a d estination address of 01-80-c2-00-00-01 ? a sour ce address take n from the specif ic addre ss 1 register ? a type id of 88-08 (mac contro l frame) ? a p a use opcod e of 00-01 ? a p a use quantum ? f ill of 00 to take the f r ame to minimu m fr ame length ? v alid fcs th e pa use quantu m use d in th e generated fra me depe nds on the trigg er source for th e frame as follows: 1. i f bit 1 1 is w ritten wi t h a one, t he pa use quantu m co mes fr om th e tran smi t paus e quan- tum register. the transmit paus e quantum registe r resets t o a va lue of 0xffff giving a m aximu m pause quant um as a default. 2. if bit 12 is w ritten wit h a one, t he pa use quantu m is zero. 3. if the tx_pause input is t o ggle d an d th e tx_pause_zero inpu t is held lo w until the next toggle, t he pa use quantu m co mes from the transmit paus e quantu m register. 4. if the tx_pause inp u t is toggled and th e tx_pause_zero input is he ld high until the next toggle, t he pa use quantu m is zero. 32058k avr32-01/12 446 at32uc3a afte r transmission, no interrupts ar e generated and the on ly statistics registe r that is inc re- mente d is th e paus e frame s t ran smi tted register. 29.5.4 receive block the re ceive block chec ks fo r valid preamble, fc s, align m en t and leng th , pre sents rece ived fram es to the dma bloc k and stores the fra mes destination ad dress for use by the a ddress checking block. if, during fram e reception , the fram e is found to be to o long or rx_e r is asserted, a b ad frame indication is sent t o the dma b lock. t he dma bloc k then ce ases send ing dat a to memory. a t the e nd of frame reception, th e re ceive bloc k indicates to the dm a block whether the frame is good or bad. t he dma block recovers the current receive buf f er if the frame was bad. the receiv e bloc k sign als th e registe r block to incremen t the alignment erro r, th e cr c (fcs) error, th e short frame, long frame, jabbe r error, th e r eceive symb ol erro r statisti cs and th e length field misma t ch statistics. the enab le bi t for jumb o frames in the networ k configuration register allows th e macb to receive jum bo fram es of up to 10240 bytes in size. t his operation does no t f orm part o f the ieee802.3 specification and is disabled by d efault. when jumbo fram es are enabled , frames received with a fram e siz e greate r tha n 10240 byte s ar e discarded. 29.5.5 addres s checki ng block the addr ess checking (or filter) block indicate s to t he dm a block which receive fram es should be copied to memory. whethe r a fra me is copied depe nds on what is e nable d in the network configuratio n register , the st ate o f t he ext ernal match pin , t he contents of the s p ecific address and hash registers and the fram e?s destinat ion address. in this implementation of the macb, the fram e?s sour ce addr ess is no t checked. provided that bit 18 o f the networ k configuratio n regis- ter is not set, a frame is not copied to memory if the macb is transmitting in half duplex mo de at the ti me a destination addr ess is received. if bit 18 of t he network config uration registe r is set, fram es ca n b e received wh ile transmitting in half-duplex mode. ethernet fr ame s are transmitte d a byte at a time, le ast significa nt bi t f i rst. the first six byt es (48 bits) of an ether net fram e mak e up th e de st ina ti on add re ss. t he firs t b it o f t h e d esti nat ion addre ss , t h e ls b of the firs t byt e o f th e frame , is th e g roup/individ ua l bit : th is is one fo r multicast addresses and zero for unicast. the a ll ones ad dress is the broadcast add ress, and a special cas e of m ult icas t. t he ma cb s uppor ts r e cogniti on o f f our spe cific addr esses. each specific address requir es two registe rs, sp ecific add ress register bo ttom an d sp ecific ad dress register to p. sp ecific address register bottom stores th e firs t four byte s of the destination addr ess an d specific address register t op contains th e last tw o bytes. the addre sses stored ca n be specific, group, local o r universal. the des ti nation address of received frames is compared a gainst the data stored in t he specific add ress regi sters once they have been activ ated. t he addresse s are de activate d at reset o r wh en their corresponding specific a ddress register bot tom is writt en. they are activat ed when specif ic address regist er top is wri tten. if a r eceive fram e a ddress matc hes an active address, the fram e is copied to memory. 32058k avr32-01/12 447 at32uc3a t he following exam ple illustra tes th e use of th e addre ss matc h register s for a ma c addre ss of 21:43:65:87:a9:cb. preamble 55 sfd d5 da (octet 0 - lsb ) 21 da(octet 1 ) 43 da(octet 2 ) 65 da(octet 3 ) 87 da(octet 4) a9 da (octet 5 - msb) cb sa (lsb) 00 sa 00 sa 00 sa 00 sa 00 sa (msb) 43 sa (lsb) 21 the sequ ence above shows t he begin ning of a n etherne t frame. byt e ord er o f tran smission is from top to bo ttom as sh own. for a successful ma tch to specific address 1 , the following addr ess matching register s must be set up: ? b ase addr ess + 0x98 0x87654321 (bottom) ? b ase addr ess + 0x9c 0x000 0cba9 (top) an d for a succ essf ul ma tch t o th e type id regist e r, th e foll owing sho u ld be se t u p: ? b ase addr ess + 0xb8 0x00004321 29.5.6 broadcast address th e broadc ast add ress of 0xffffffffffff is rec ognize d un less the ?n o broa dcast? bit in the networ k configuration register is se t. 29.5.7 hash addressing the hash add r ess regist er is 6 4 bits long an d take s up tw o loca tions in t he memory map. the leas t significant bits ar e stored in hash register bottom and th e most significan t bits in hash reg- ister top. th e unicast has h enab le an d th e multicast hash e nab le bits in the network configuration register enable th e reception of hash matched frames. the destination addres s is reduced to a 6 -bit inde x into th e 6 4-bit hash regi st er usin g the followin g hash fun cti on. th e ha sh function is an exclusive o r of ever y sixt h bi t of th e destinatio n address. 32058k avr32-01/12 448 at32uc3a hash_in dex[5 ] = da[5 ] ^ d a [11] ^ d a[ 17] ^ d a[ 23] ^ da[29 ] ^ da[35 ] ^ da [41 ] ^ da[4 7] hash_in dex[4 ] = da[4 ] ^ d a [10] ^ d a[ 16] ^ d a[ 22] ^ da[28 ] ^ da[34 ] ^ da [40 ] ^ da[4 6] hash_in dex[3 ] = da[3 ] ^ d a [09] ^ d a[ 15] ^ d a[ 21] ^ da[27 ] ^ da[33 ] ^ da [39 ] ^ da[4 5] hash_in dex[2 ] = da[2 ] ^ d a [08] ^ d a[ 14] ^ d a[ 20] ^ da[26 ] ^ da[32 ] ^ da [38 ] ^ da[4 4] hash_in dex[1 ] = da[1 ] ^ d a [07] ^ d a[ 13] ^ d a[ 19] ^ da[25 ] ^ da[31 ] ^ da [37 ] ^ da[4 3] hash_in dex[0 ] = da[0 ] ^ d a [06] ^ d a[ 12] ^ d a[ 18] ^ da[24 ] ^ da[30 ] ^ da [36 ] ^ da[4 2] da[0] represents t he least significant bit o f the first byte received , tha t is , the multicast/unicast indicator, and da[47] represents t he most significant bit o f the la st byte received. if the ha sh inde x points to a bi t that is se t in t he hash register , then the fram e is matche d accord- in g to whethe r the fram e is multicas t o r unicast. a mul ticas t match is sig nalle d i f the multicast ha sh enab le bit is se t. da[0] is 1 a nd the ha sh index points to a bi t set in th e hash register. a u nicast match is signal led if the unicast hash enable bi t is set. da[0] is 0 and t he hash index points to a bi t set in th e hash register. to receive all multicas t frames , the hash register shou ld be set with al l on es an d the multicast hash en a ble bi t shou ld be set in t he ne twor k conf igur atio n re giste r. 29.5.8 externa l addres s matching th e exter nal add ress signa l (ea m) is enable d by bit 9 in th e n etwor k configura tion register. when enabled , th e filter bloc k sends the store fram e and t he external addr ess matc h status sig- nal to the dma bl oc k i f th e external addre ss matc h signal is asser ted (fro m a source extern al to t he macb) and t he destinatio n address h as bee n receive d an d the fram e ha s no t completed. fo r th e dma block to be ab le to copy t he frame to memory , the external addr ess sign al must be asserted before four words ha ve be en loade d into the re ceive fifo. 29.5.9 copy al l frames (o r promiscuous mode) if the c op y all fr ame s bit i s se t in th e ne twor k co n figuratio n register , th en a ll non-error ed fram es are copied to mem ory . f or e x ampl e, f ra mes t hat are t oo long , t oo s hort , or hav e fc s erro rs or rx_e r asserte d durin g receptio n ar e discarde d a nd all others a re receive d. fra mes with fcs erro rs ar e copie d to memo ry if bit 19 in th e n etw or k con figur ati on r egister is s e t. 29.5.10 type id checking th e conten ts of th e type_i d registe r ar e compared against th e length /typ e id o f receiv e d fram es (i .e. , byt e s 13 and 14). b it 2 2 i n th e receive buffer de scrip to r sta tus is s e t i f th er e is a ma tch . th e reset state of this register is zero whic h is unlikel y t o match the length/type id of an y valid ether- ne t frame. note: a type id match does no t affect whethe r a fram e is copied to memory. 32058k avr32-01/12 449 at32uc3a 29.5.11 v lan support an e therne t encod e d 8 0 2.1 q v l an t a g loo ks lik e this: th e vlan tag is inse rted at th e 13 th byt e of th e frame, addi ng a n extr a fou r bytes t o th e frame. if t he vi d (vlan identifier ) is nu ll (0x000), th is indicate s a priority-tagged frame. the mac ca n suppor t fra me leng ths up t o 153 6 bytes, 18 byt e s more than t he or iginal ethern et maximum fram e length of 15 18 bytes. th is is achi eved by settin g bi t 8 in th e netw ork configuration register. the following bits in the receive buffer descri ptor stat us word give in formation abou t vlan tagged frames: ? bit 2 1 set if receiv e fra me is vlan tagge d (i.e. typ e id of 0x8100) ? bit 20 set if receiv e fram e is priority tagge d (i.e . ty pe i d of 0x810 0 and nu ll vid). (i f bit 20 is set bit 2 1 is set also.) ? bit 19, 18 an d 17 set t o priority if bit 21 is set ? bit 1 6 se t t o cfi if bi t 21 is s et 29.5.12 phy maintenance t he r eg ist er ma n en able s th e ma cb t o commun i cate wit h a ph y b y m ea ns o f the mdi o inte r- face . i t is us ed duri n g auto-nego tia tion t o ensur e that th e mac b and th e p hy a r e co nf igured for the same spee d an d duplex configuration. th e phy maintenance register is impl emented as a shi ft register. writing to the register starts a shift o p eration which is signa lled as complete when bi t two is se t in th e network status register (about 2000 mck cyc le s later wh en bi t ten is se t t o zero, an d bit elev en is se t to one in t he net- work configuration register). an interrupt is generated as th is bit is se t. duri ng th is time , t he msb of t h e regi ster is output on th e mdio pi n and th e lsb updat ed from th e mdio pi n with each mdc cycle. this causes transmission of a ph y management fr ame on mdio. r eadi ng during th e sh ift op era tio n returns th e c u rrent conten ts o f th e sh ift register . at the en d of management oper ation, th e bits have shifte d ba ck to th eir origin al locations. fo r a read opera- tion, t he dat a bits a re updated with data r ead fr om th e phy. it is impor tant to write t he correct values to the registe r to en sur e a v a lid phy m a nage ment fr am e is pr od uced. the mdi o inte rface can read ieee 802.3 clause 4 5 phys as well as clause 2 2 phys. to rea d clause 45 phys, bits[31:28] should be written as 0x0011. fo r a description of mdc generation, see th e netw or k configuratio n regist er i n the ?netwo rk contro l register? on p ag e 456. 29.5.13 media independent interface the ethernet mac is cap a ble of interfacing to both rmii an d mii interfaces. the rmii bit i n the usri o register controls the interface t hat is selected. when this bit is set , the rmi i int erface is selected , else th e mii interfac e is selected. tabl e 29-4. 802.1q vl an tag tpid ( tag pr otocol identifier) 16 bits tci ( tag contro l info rmation) 16 bits 0x8100 fi rst 3 bits priority , then cfi bit, l a st 12 bi ts vid 32058k avr32-01/12 450 at32uc3a t he mii and rm ii interfac e ar e capab l e of both 10mb/s and 1 00mb /s d ata rate s as de scribed in the ieee 8 02.3u standard. the signals used by th e mii an d rmii interf aces are describ ed in ta ble 29-5. th e intent of th e rmii is to provid e a reduced pin c ount alternat ive to the ieee 802.3u mii. it uses 2 bi ts fo r transmit (etx0 a n d etx1 ) and two bits fo r receiv e (erx0 an d erx1). there is a transmi t enable (etxen), a receive error (erxer), a ca rrier se nse (ecrs_d v), and a 5 0 mhz re ferenc e cloc k (etxck_erefck) fo r 100mb/ s data rate. 29.5. 13.1 rm ii tran smit and receiv e op eratio n the same si g nals are used internally f or both the rmii and the mii operat ions. the rmii maps thes e signa ls i n a m o r e pin-efficie n t ma nner . th e transm it an d rece ive bit s a re converted f ro m a 4-bit parallel forma t to a 2-bi t para llel schem e that is clocke d a t twice th e rate. t he carrier sense and data valid sig n als ar e combined into the ecrsdv si gnal. th is sig nal contai ns information on ca r rier sense, fifo status, and validity of t he dat a. transmit e rror bit (etxer ) a nd collision dete ct (ecol ) ar e not use d in rmii mode. tabl e 29-5. pin co nfiguration pin name mii rmii etxck_erefck etxck: transmit clock erefck: referenc e clock ecrs ec rs: carrie r sense ecol ec ol: collision detect erxdv erxdv : data valid ecrsdv: carrie r sense/data valid erx0 - erx3 erx0 - erx3: 4-bit recei v e data er x0 - erx1: 2-bit receiv e data erxer er x er: receiv e error erxer: receiv e error erxck erxck: receive clock etxen etxen: transm it enable etxen: tr ansm it enable etx0-etx3 e tx0 - etx3: 4-bit transmit data et x0 - etx1: 2-bit transmit data etxer etxer: transm it error 32058k avr32-01/12 451 at32uc3a 29.6 pr ogramming interface 29.6.1 initi a liz ation 29.6.1.1 configuration initializatio n o f th e macb configuration (e .g. frequ ency ratios) must be done wh ile the transmit an d rece ive circuits ar e disabled . see th e description o f th e network contro l register a nd network configuration register late r in th is document. 29.6.1 .2 receiv e buffer list receive data i s writte n to areas of da ta (i.e., buff ers) in syste m memory. thes e buff ers are listed in a noth er da ta structure that also resides i n main me m ory. th is dat a structur e (receive buffer queue) is a sequence o f descriptor entrie s as define d in ?r eceive buff er d e scrip tor entry ? o n pag e 440. it points to th is data structure. figur e 29-2. receive buffer li st t o cre ate th e lis t of buffer s: 1. allocate a n umbe r (n ) of buffer s of 128 byte s in system memory. 2. allocate an area 2n words fo r th e receive buffer descriptor entr y in system memory and create n entries in this li s t. mark all ent ries in t h is list as owned by macb, i.e. , bit 0 of wor d 0 set t o 0. 3. if le ss than 10 24 bu ffers ar e defin e d, th e la st descrip tor must b e mar ke d wi th th e wra p bit (b it 1 in wor d 0 se t to 1). 4. write addre ss of receive buffer descripto r entr y to macb registe r receive_buffer queue pointer. 5. th e receive circuits ca n the n be enabled by writing to th e address recognitio n registers and then to th e networ k contr ol register. receive buffer queue pointer (mac register) receive buffer 0 receive buffer 1 receive buffer n receive buffer descriptor list (in memory) (in memory) 32058k avr32-01/12 452 at32uc3a 29.6.1.3 transmit buffe r list tr an smit dat a is read fro m t h e syst em memory th ese buffer s ar e liste d in ano the r d ata structure that also r eside s in ma in memory. this data structur e (transmit buffer queue) is a s eque nce of descripto r entries (as define d in tabl e 29- 2 o n pa ge 443 ) that poin ts to this da ta structure. to cr eate th is list of buffers: 1. allocate a n umber (n) of buffers of between 1 a n d 2047 bytes o f data t o be transmitted in system memory. up to 128 buffers per fram e ar e allowed. 2. allocate an area 2 n words for the transmit buffe r descripto r entr y in system memory and create n entri e s i n t hi s l is t. mark al l en tri es in this list as owned by macb , i.e. bit 31 of word 1 set t o 0. 3. if fewe r th an 1024 buffer s ar e defined, the last descriptor m ust be marke d with the wrap bit ? bit 30 in wor d 1 set t o 1. 4. write addre ss o f transmit buffer descripto r entry to macb register transmit_buffer queu e pointer. 5. th e transmit circuits can then b e enabled by writin g to the network contro l register. 29.6.1.4 address matching th e macb register-pair ha sh addr ess and the four specif ic address register-pairs must be writ- t en with the req uired values . eac h r egis ter-pair co mprises a b ot t om r egister an d t op r egister, with th e botto m r egiste r b ein g w r itte n first. th e address matching is disabled for a particula r reg- ister-pair after the bottom-register has been wri t ten and re-enabled when the top regist er is written. se e sectio n ?29.5. 5? on pag e 446. for details of ad d ress matching. each register-pai r ma y be writte n at an y time, regardless of whether th e re ceive circui ts ar e enabled or disabled. 29.6.1.5 interrupts ther e a r e 14 in terr upt conditio ns tha t ar e detect ed withi n th e macb. th es e ar e o r ed t o make a single interrup t. th is interrup t is passed to th e interrupt co ntroller . on receipt of t he interr upt sig- na l, th e cpu enters th e interrupt handler. to ascertai n which interrupt h as been generated , read the interrupt status register . note that this register clears itself when read . at reset, all i nterrupts ar e disabled . t o enab le an interrupt, write to interrupt enable register with the pertinent interrupt bit set t o 1. to disable an interrupt , write t o interrupt di sable register with t he pertinent interrupt bit set to 1. t o che c k wh ether a n in terrup t is enable d or disabled, rea d in terrupt mas k re gist er: if the bi t is set to 1 , the interrup t is disabled. 29.6.1.6 transmitting frames to set u p a frame for transmission: 1. enable transmit in th e network control register. 2. allocate an are a of syste m memory for transmit data. this d oes not have to be co ntigu- ous, varying byte length s ca n b e use d as lon g as they conclud e on byte borders. 3. set-u p t he trans mit buffer list. 4. set th e ne tw or k control reg ister t o e nabl e transmissio n an d e nab l e interrupt s. 5. write data for transmission into these buffers. 6. write th e address to transmit buffer descriptor queue pointer. 7. write control a nd length to wor d o ne of the transmit buffe r descripto r entry. 8. write to th e transm it star t bit in th e network control register. 32058k avr32-01/12 453 at32uc3a 29.6.1.7 rece ivin g frames when a fram e is rece ived and the re ceive circuits ar e enabled , the macb ch ecks the address and, i n the f ollo wi n g cases, th e fram e is wri tte n to syste m m emory: ? i f it matche s on e of th e four specifi c ad dr e ss r e gister s. ? if it matches the h ash address function. ? i f it is a b ro adcast addre ss (0xffffffffffff) a nd broa dcasts ar e allowed. ? i f t he m acb i s confi gu re d t o cop y a ll frames. ? i f th e ea m is ass erted before four word s have been load e d in to th e r e ceiv e fifo. the registe r receive buffer que ue point er points to the ne xt entry (see table 29-1 o n page 440) and t h e mac b us es this a s th e addre ss i n system me mory to writ e th e fram e to . on ce t h e frame has bee n complet ely and successfully received an d written t o system memory , t he macb then updates the rece ive buffer descriptor entry with the reason for the addre ss match and marks the area as being owned b y software. once th is is complete an interrup t rece ive complete is set. softwar e is then responsible for handling the dat a in th e buffer and then releasing the buffer by writing th e ownership bi t back to 0. if t he macb is unable to wri te the dat a at a r ate to match t he incoming frame, the n an interrupt re ceive overr un is set. if ther e is no receive buffer available, i.e. , the next buffe r is still owned by software , t he interr upt receive buff er not avail able is set. if the f r ame is n ot successfully received, a statisti c register is i ncremented and the fram e is discarde d without informing s oftw are. 32058k avr32-01/12 454 at32uc3a 29.7 ethernet mac (mac b) user interface tabl e 29-6. etherne t mac (macb) register mapping offset register name access reset value 0x00 networ k contro l register ncr read/write 0 0x04 networ k co nfiguration re gister ncfg rea d/write 0x800 0x08 networ k status register nsr read-only - 0x0c reserved 0x10 reserved 0x14 tran smit status register tsr read/write 0x0000_0000 0x18 receiv e buffer queue pointe r register rbqp read/write 0x0000_0000 0x1c tran smit buffer queue pointe r register tbqp read/write 0x0000_0000 0x20 receiv e status register rsr read/write 0x0000_0000 0x24 interrup t status register isr read/write 0x0000_0000 0x28 interr upt enab le register ier write-only - 0x2c interr upt disable register idr write-only - 0x30 interrup t mask register imr read-only 0x0000_3fff 0x34 ph y mainten ance register man read/write 0x0000_0000 0x38 pa use time register ptr read/write 0x0000_0000 0x3c pause fr ames receiv ed register pfr read/write 0x0000_0000 0x40 fr ames tran smitt e d ok r egister fto read/write 0x0000_0000 0x44 single collision frames register scf read/write 0x0000_0000 0x48 multiple collision fr ames register mcf read/write 0x0000_0000 0x4c fr ames receiv ed ok register fro read/write 0x0000_0000 0x50 fr ame chec k sequ ence errors register fcse read/write 0x0000_0000 0x54 alignmen t errors register ale read/write 0x0000_0000 0x58 deferred transmission frames register dtf read/write 0x0000_0000 0x5c la te collisions register lcol read/write 0x0000_0000 0x60 excessive collisions register excol read/write 0x0000_0000 0x64 tran smit u nderr u n errors register tund read /w ri te 0x0000_00 00 0x68 carr ier sense errors reg ister cse read/write 0x0000_0000 0x6c receive res o ur ce er ror s r egis t er rre re a d/write 0 x00 0 0_00 00 0x70 receiv e overru n erro rs register rov read/write 0x0000_0000 0x74 receiv e symbo l errors register rse read/write 0x0000_0000 0x78 excessive length errors reg ister ele read/write 0x0000_0000 0x7c receive jabbers register rja read/write 0x0000_0000 0x80 undersize frames register usf read/write 0x0000_0000 0x84 sqe test errors register ste read/write 0x0000_0000 0x88 receiv ed len gth fie ld mismatch re gister rle rea d/wr ite 0x0000_0000 32058k avr32-01/12 455 at32uc3a 0x8c transmitted pause frames register tpf read/write 0x0000_0000 0x90 hash regis ter bottom [31 :0] register hrb read/write 0x0000_0000 0x94 ha sh register t op [63:32] r e g i s ter hrt re ad/ w r i te 0x000 0 _00 00 0x98 sp ecific ad dress 1 bottom reg i s t er sa1b re ad/ w r i te 0x000 0 _00 00 0x9c sp ecific ad dress 1 top register sa1t read/write 0x0000_0000 0xa0 sp ecific ad dress 2 bottom re gister sa2b re ad/ w r i te 0x000 0 _00 00 0xa4 sp e c ifi c a d d r e s s 2 top register sa2t read/write 0x0000_0000 0xa8 sp ecific ad dress 3 bottom register sa3b read/write 0x0000_0000 0xac sp e c ifi c a d d r e s s 3 top register sa3t read/write 0x0000_0000 0xb0 sp ecific ad dress 4 bottom register sa4b read/write 0x0000_0000 0xb4 sp ecific ad dress 4 top register sa4t read/write 0x0000_0000 0xb8 type id che cking register tid read/write 0x0000_0000 0xbc transmit pause quantum regist er tpq r ead/wri te 0x0000_f fff 0xc0 us er input/output register usrio read/write 0x0000_0000 0xc4 wak e o n lan re gister wol read/write 0x0000_0000 0xc8 - 0xfc reserved ? ? ? tabl e 29-6. etherne t mac (macb) register mappin g (continued) offset register name access reset value 32058k avr32-01/12 456 at32uc3a 29.7.1 networ k control register register name: ncr acces s type: read/write ? lb: loopback asserts the loop back signal to t he phy. ? llb : loopback lo cal connects txd to rxd , tx_en to rx_dv, fo rces fu ll dup lex an d drives rx_clk and tx _clk wit h pclk div ide d by 4 . rx_clk and tx _ clk ma y g litc h a s t he mac b i s s witched into and out of inter nal loop back. it is important that receive and transm it circui ts have already been disabled whe n making the switch in to an d ou t of internal loop ba ck. this function ma y not be supported by some instantiations of th e macb. ? r e: receiv e enable when se t, enables t he macb to receive da ta. when reset, frame reception st ops immediat ely an d the receive f i fo is cleared. th e re ceive queu e pointe r register is unaffected. ? te : tra nsmi t ena ble when set, en a bles the ethernet transmitter to send data. wh en reset, transmissi o n stops immediately, the transmit fifo an d contr ol register s ar e cleare d and the transmit queu e pointer registe r resets t o point to th e start o f th e transm it descrip- to r list. ? mpe : ma n a ge men t po r t ena b le set to one t o enab le th e management port. when zero, fo rces mdio t o hi gh imped ance stat e an d md c low. ? clrstat: clea r statistics registers th is bi t is writ e only. writin g a one clears t he statistics registers. ? incstat: incremen t statistics registers this bi t is write only. writ ing a one incremen ts all th e statisti cs register s by one for te st purposes. ? westat: writ e enable for statisti cs registers setting this bi t to o ne makes th e statisti cs registe r s writ ab le fo r fu nctional tes t p ur poses. ? b p: back pressure if set in ha l f duplex mode, forces co llisions on all received frames. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? tzq tpf thalt tstart bp 7 6 5 4 3 2 1 0 westat incstat clrstat mpe te re llb lb 32058k avr32-01/12 457 at32uc3a ? tstart: start transmission writing one to this bi t starts transmission. ? tha lt: transm it ha lt writing one to th is bit halts tran smission as soo n as any ongoing frame tran smission ends. ? tpf: transmit paus e frame writing one to t his bit tran smits a pau se fr ame with the p ause quan tum from t he tra nsmit pause quantum registe r at the ne xt available transmitter id le time. ? tzq: transmit zer o quant um paus e frame writing a on e to th is bi t transmits a pa use frame wit h zer o pau se qu ant um a t t he nex t available transmitte r idl e ti me. 32058k avr32-01/12 458 at32uc3a 29.7.2 networ k configurat ion register register name: ncfgr acces s type: read/write ? spd: speed set to 1 to indicat e 10 0 mb it/s operation, 0 f o r 1 0 mbit/s. the valu e of this pin is r eflecte d on the speed pi n. ? fd: fu ll duplex if se t to 1, the transmit block ignore s the state of collision and carrier sense and allo ws receive wh ile transmitting. also con- trols the half_duplex pin. ? b it rate: if set t o 1 to configure the interface for serial operation. must be set before receive and transmit enable in the network con- trol register. if set a seri al interf ace is configur ed with transmit an d receiv e dat a bein g driven ou t on txd[0 ] an d received on rxd[0] serially. also t he crs an d rx_d v ar e logically ored together so either may be use d as the data va lid signal. ? caf: co py a ll frames when set t o 1, all va lid fr ames are rece ive d. ? jframe: jumbo frames set to one t o enab le jumb o frames of u p t o 102 40 byt es t o b e accepted. ? nbc : no broadcast when set to 1, frames addressed to t he broadcast address of all o nes ar e not received. ? mti : multicast hash enable when set, multicas t fram es are received when the 6-bit hash functio n o f the de stinatio n add re ss po ints to a bi t t hat i s s e t in th e has h register. ? uni: unicast hash ena ble when set, unicas t fram es are received when th e 6-bit hash function o f the destination address points to a bi t that is s e t in th e has h register. ? big : receive 1536 byte s frames settin g this bit mea ns th e macb receives fram es up t o 15 36 b yte s in length. norma lly, th e ma cb wo uld reject any frame ab ove 151 8 bytes. ? eae : exte rnal add re s s m a tc h enable when set , t he eam pi n ca n b e u se d t o c o py frames t o m e mory. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? irxfcs efrhd drfcs rlce 15 14 13 12 11 10 9 8 rbof pae rty clk eae big 7 6 5 4 3 2 1 0 un i mti n b c c af j frame bi t rate fd spd 32058k avr32-01/12 459 at32uc3a ? c lk: mdc cloc k divider set accordin g to system clock speed. this determine s by what number system clock is divide d t o generat e mdc. fo r conforma nce wit h 802.3, mdc mu st no t exceed 2. 5mhz (mdc is on ly acti ve durin g mdio rea d and writ e operations). ? rty : retry test must be set to ze ro for normal operation. if set to one, the ba ck off between collision s is always one slot time. setting thi s bi t t o o n e h elp s test in g th e t oo m an y r etrie s cond ition . also used in t he pause fr ame tests to reduce the pause counters decrement time from 51 2 bit time s, to every rx_clk cycle. ? pae: pause enable when set, transmission pau ses when a valid pause fram e is received. ? rb of: r eceiv e buffer offset indicates th e numbe r of byte s by which th e received dat a is offset from the star t of the first receive buffer. ? r lce: receiv e lengt h fiel d checki ng enable when se t, fr ames with measured lengths shorte r th an th eir length fiel ds ar e di s ca r ded . f rame s c on t aini ng a typ e i d i n byte s 13 an d 14 ? length/type id = 0600 ? a r e not b e coun ted as lengt h erro rs. ? drfcs: discar d receiv e fcs when se t, the fcs field of received frames will not be copied to memory. ? efrh d: enable frames to be received in half-duplex mode wh ile transmitting. ? irxfc s: ignore rx f cs when set , frames with fcs/crc errors ar e no t reject ed and no fcs e rro r statisti cs ar e counted. fo r normal operation, this bit must be set t o 0. clk mdc 00 mc k divided by 8 ( m ck up to 20 mhz) 01 mc k divided by 16 (mck up to 40 mhz) 10 mc k divided by 32 (mck up to 80 mhz) 11 mc k divided by 64 (mck up to 160 mhz) rbof offset 00 no offset fr om star t of receive buffer 01 one-byt e of fset from star t of receive buffer 10 two-by te offset from star t of receive buffer 11 three-byte of fset from star t of receive buffer 32058k avr32-01/12 460 at32uc3a 29.7.3 networ k status register register name: nsr acces s type: read-only ? mdio return s stat us of th e mdio_i n pin. use t he phy maintenanc e register fo r read ing managed fra mes rather than th is bit. ? idle 0 = th e phy l o gic is running. 1 = th e phy management logi c is idle (i.e., ha s completed). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? idle mdio - 32058k avr32-01/12 461 at32uc3a 29.7.4 tra nsm it statu s r eg i ster register name: tsr acces s type: read/write t hi s registe r , whe n read, provide s det ail s o f th e sta tu s of a transmit . once read, individual bits may be cleared by writing 1 to them. it is n ot possibl e to se t a bi t t o 1 by writin g to th e register. ? ubr : used bit read set when a tr ansmit buffe r descriptor is r ead with its u se d bit set. cleare d by writin g a on e to this bit. ? col: collisi on occurred se t by th e assertio n of colli s ion . cle ared by wr iting a one to this bit. ? rle: retr y limit exceeded cleared by w ritin g a on e to th is bit. ? tgo: transmit go i f hi gh tr ansm it is acti ve. ? b ex: buffers exhauste d mid frame if the buffers run out during tran smission of a f rame, then transmission stops, fcs sh a ll be bad and tx_er asserted. cleared by writin g a on e to th is bit. ? comp: transmit complete set wh e n a fram e has bee n tra nsmit ted . clear ed by w r itin g a o n e t o th is bi t. ? und: tr ansmit underrun set whe n tra nsm it dm a w as no t able t o read da ta from memory, either be caus e th e bu s wa s no t g ranted in time , be cau se a not ok hresp(bu s error) was r eturned or because a used bi t was re ad midway t hrough frame transmission . if this occurs, the transmit te r forces bad crc . cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? und comp bex tgo rle col ubr 32058k avr32-01/12 462 at32uc3a 29.7.5 rece i ve buf f er qu eu e pointe r registe r register name: rbqp acces s type: read/write this r egister points t o the ent ry in the r eceive buff er queue (descriptor list) current ly being used. it is writ t en with t he start location o f t he receiv e buffer descripto r list. t he lowe r orde r bits increment as bu ffers are used up a n d wr ap to thei r original values afte r either 10 24 buffers or when th e wra p bit of the entr y is set. reading t his regist er returns t he locati on o f t he descripto r current ly bein g accessed. this value inc rement s as buff ers are used . softwar e shou ld not use th is register fo r determining wher e to remove received frames from th e queu e as it co n- stan tly chang es as new frames ar e re ceived. softwar e shou ld instea d work its way through th e bu ffer descripto r queue checking th e used bits. receive buffer writ es also comprise bursts of tw o word s and, as wi th transmit buffer reads, it is r ecommended that bi t 2 is alwa ys writte n with zero to preven t a burst crossing a 1 k boundary, in violation o f the system bus s pecification. ? ad dr: receive buff er que ue pointer address written wit h th e addr ess of th e start o f the receiv e queue, re ads as a pointer t o th e current buffer being used. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr ? ? 32058k avr32-01/12 463 at32uc3a 29.7.6 transmit buffer queue pointe r register register name: tbqp acces s type: read/write th is register points to the entry in the transmit buffer queue (descriptor list) currently being used. it is w ritte n with the start location o f the transmit buffer descripto r list. t he lower order bits increment as buffers are used up a nd wrap to their original values aft er eit her 102 4 buffers or when t he wrap bit of t he entr y is s et. th is registe r ca n only be written when bit 3 in th e transmit status register is low. as transmit buffe r read s co nsist of bursts of two word s, it is recommended that bi t 2 is alwa ys written wit h zero to prevent a burst cr ossing a 1k boundar y, in violatio n o f the syst em bus specification. ? ad dr: tran smit buffe r queue point e r ad dress written with t he address of th e star t o f t he transm it queue, rea ds as a pointer to the first buffe r of the frame be ing transmit- te d o r about to be transmitted. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr ? ? 32058k avr32-01/12 464 at32uc3a 29.7.7 recei ve statu s register register name: rsr acces s type: read/write this register , whe n read, provides details of t he status of a r eceive. onc e read, individu al bits ma y be cleare d by writing 1 to them. it is n ot possibl e to se t a bi t t o 1 by writin g to th e register. ? bna : buff er not available an a ttempt wa s made t o get a ne w buffer a nd the pointe r indicated that it wa s owne d by the processor. th e dma rereads the pointe r each tim e a new fram e starts un til a valid pointer is found. this bit is set at each attempt that fails even if it has not h ad a successful pointer re ad since it has been cleared. cleared by w ritin g a on e to th is bit. ? r ec: frame received on e or mor e frames h ave been receive d and placed in m emory . cleared by w ritin g a on e to th is bit. ? ov r : rec eiv e overr un the dma block w a s unable to st ore the receive frame t o memory , eithe r because t he bus w a s not grant ed in ti me or be cause a no t ok hresp(bus error) w a s ret urne d. the buffe r is recove re d if this happ ens. cleared by w ritin g a on e to th is bit. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ovr rec bna 32058k avr32-01/12 465 at32uc3a 29.7 .8 interrupt status register register name: isr acces s type: read/write ? mfd : manageme nt fra me done th e phy maintena nce registe r ha s complete d its operation. cleared on read. ? rcomp: rec eiv e complete a f ram e has be en store d in memory. cleared o n read. ? rxu br: receive used bi t read set whe n a receive buffer descriptor is r e ad wit h its use d bi t set. cleared on read. ? txubr: tr ansmit used bi t read set when a tr ansmit buffe r descriptor is r ead with its u se d bit set. cleare d o n read. ? tund : ethernet tr ansmit buff er underrun th e transmit dm a di d no t fetch frame data in time for i t t o be transmitted or hresp returned no t ok. also se t if a use d bit i s re a d mid-fra me o r whe n a n ew trans mit queu e pointer is wr itte n. cleared o n read. ? rle: retr y limit exceeded cleare d o n rea d. ? txerr: transmit error trans m it b uffer s exhausted in mid -fr am e - transmit erro r. clea re d on read. ? t comp: transm it co m p lete set when a fr am e ha s been transmitted. cleare d on read. ? rovr: receiv e overrun set when th e rece ive overru n status bit g ets se t. cleare d on read. ? hre sp: hresp not ok set when the dma bl oc k sees a bus error. cleared o n read. ? pfr: pau se fram e received indicates a v a lid paus e ha s been received. clear ed on a read. ? ptz: pause time zero set when th e paus e time register , 0x3 8 decremen ts to zero. clear ed on a read. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr - ? 7 6 5 4 3 2 1 0 tcomp txerr rle tund txubr rxubr rcomp mfd 32058k avr32-01/12 466 at32uc3a 29.7 .9 interrupt enable register register name: ier 32058k avr32-01/12 467 at32uc3a acces s type: write-only ? mfd : manageme nt fram e sent enable management don e interrupt. ? rcomp: rec eiv e complete enable receive c omplete interrupt. ? rxu br: receive used bi t read enabl e r e ceive use d bi t rea d interr upt. ? txubr: tr ansmit used bi t read enable transmit used bit read interrupt. ? tund : ethernet tr ansmit buff er underrun enable transmit underrun interrupt. ? rle: retr y limit exceeded enable retry limit exceede d interrupt. ? txerr: transmit error enable transmit buffers exhaust ed in mid-frame interrupt. ? t comp: transm it co mplete ena ble trans m it complete interrupt. ? rovr: receiv e overrun enabl e re ceive overr un interrupt. ? hre sp: hresp not ok enable hresp not ok interrupt. ? pfr: pau se fram e received enabl e pause frame received interrupt. ? ptz: pause time zero enab le pause time zero interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? 7 6 5 4 3 2 1 0 tcomp txerr rle tund txubr rxubr rcomp mfd 32058k avr32-01/12 468 at32uc3a 29.7.10 interrup t disabl e register register name: idr acces s type: write-only ? mfd : manageme nt fram e sent di sabl e m anageme nt don e i nterrupt. ? rcomp: rec eiv e complete disable receive com p lete interrupt. ? rxu br: receive used bi t read disabl e rece ive use d bit read interrupt. ? txubr: tr ansmit used bi t read disable transmit use d bit read interrupt. ? tund : ethernet tr ansmit buff er underrun disable transmit underru n interrupt. ? rle: retr y limit exceeded disabl e retr y limit exceed ed interrupt. ? txerr: transmit error disable transmit buffers exhausted i n mid-frame interrupt. ? t comp: transm it co m p lete disabl e transmit complete interrupt. ? rovr: receiv e overrun disabl e receiv e overr un interrupt. ? hre sp: hresp not ok disable hr esp no t ok interrupt. ? pfr: pau se fram e received disabl e paus e fram e received interrupt. ? ptz: pause time zero disabl e paus e time zero interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr - ? 7 6 5 4 3 2 1 0 tcomp txerr rle tund txubr rxubr rcomp mfd 32058k avr32-01/12 469 at32uc3a 29.7.11 interrup t ma sk register register name: imr acces s type: write-only ? mfd : manageme nt fram e sent ma nag eme nt don e inte rrup t m a sked. ? rcomp: rec eiv e complete receive complete interrupt masked. ? rxu br: receive used bi t read receiv e use d bi t read interrup t masked. ? txubr: tr ansmit used bi t read transmit used bit r ead interrup t masked. ? tund : ethernet tr ansmit buff er underrun transm it underr un interrupt masked. ? rle: retr y limit exceeded retry limit ex ce eded interrupt masked. ? txerr: transmit error trans m it b uffer s exhausted in mid -fr am e inte rru p t m aske d. ? t comp: transm it co m p lete transmit c omple te interrup t ma sked. ? rovr: receiv e overrun receive ov err un interrupt masked. ? hre sp: hresp not ok hresp not ok interrup t masked. ? pfr: pau se fram e received pause fram e received interrup t masked. ? ptz: pause time zero pause time zero interrup t masked. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr - ? 7 6 5 4 3 2 1 0 tcomp txerr rle tund txubr rxubr rcomp mfd 32058k avr32-01/12 470 at32uc3a 29.7.12 p hy maintenan ce register register name: man acces s type: read/write ? data fo r a writ e ope ratio n t h is is wri tte n wit h th e d at a to be writte n t o th e phy . afte r a rea d operatio n th is contains th e data read from t he phy. ? code: must be writte n to 10. reads as written. ? r ega: register address specifies the register in th e phy to access. ? phy a: ph y address ? rw: read/write 10 i s read; 01 is write. an y other va lue is an invalid phy management frame ? sof: start of frame must be written 01 for a valid frame. 31 30 29 28 27 26 25 24 sof rw phya 23 22 21 20 19 18 17 16 ph ya rega code 15 14 13 12 11 10 9 8 data 7 6 5 4 3 2 1 0 data 32058k avr32-01/12 471 at32uc3a 29.7.13 pau se ti me register register name: ptr acces s type: read/write ? p time : pa u se time stores th e c u rrent val u e o f the paus e ti me registe r whic h is decreme nte d e very 51 2 b i t tim es. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ptime 7 6 5 4 3 2 1 0 ptime 32058k avr32-01/12 472 at32uc3a 29.7.14 has h register bottom register name: hrb acces s type: read/write ? addr: bits 31:0 o f the hash a ddress register. see ?hash ad dressing ? o n page 447. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 473 at32uc3a 29.7.1 5 has h register top register name: hrt acces s type: read/write ? addr: bits 63: 32 of th e has h add ress register. see ?hash addressing ? on pa ge 447. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 474 at32uc3a 29.7.16 specifi c addres s 1 bott om register register name: sa1b acces s type: read/write ? addr leas t significant bits o f the destinatio n address. bi t zero indicate s whethe r th e address is multicast or unicast and corre- sponds to the leas t significant bi t of th e first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 475 at32uc3a 29.7.17 specifi c addres s 1 to p register register name: sa1t acces s type: read/write ? addr th e most signific ant bits of th e destinat ion addr ess, tha t is bi ts 47 to 32. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 476 at32uc3a 29.7.18 specifi c addres s 2 bott om register register name: sa2b acces s type: read/write ? addr leas t significant bits o f the destinatio n address. bi t zero indicate s whethe r th e address is multicast or unicast and corre- sponds to the leas t significant bi t of th e first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 477 at32uc3a 29.7.19 specifi c addres s 2 to p register register name: sa2t acces s type: read/write ? addr th e most signific ant bits of th e destinat ion addr ess, tha t is bi ts 47 to 32. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 478 at32uc3a 29.7.20 specifi c addres s 3 bott om register register name: sa3b acces s type: read/write ? addr leas t significant bits o f the destinatio n address. bi t zero indicate s whethe r th e address is multicast or unicast and corre- sponds to the leas t significant bi t of th e first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 479 at32uc3a 29.7.21 specifi c addres s 3 to p register register name: sa3t acces s type: read/write ? addr th e most signific ant bits of th e destinat ion addr ess, tha t is bi ts 47 to 32. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 480 at32uc3a 29.7.22 specifi c addres s 4 bott om register register name: sa4b acces s type: read/write ? addr leas t significant bits o f the destinatio n address. bi t zero indicate s whethe r th e address is multicast or unicast and corre- sponds to the leas t significant bi t of th e first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 481 at32uc3a 29.7.23 specifi c addres s 4 to p register register name: sa4t acces s type: read/write ? addr th e most signific ant bits of th e destinat ion addr ess, tha t is bi ts 47 to 32. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr 32058k avr32-01/12 482 at32uc3a 29.7.24 type id checking register register name: tid acces s type: read/write ? tid: type id checking fo r use in compar isons with received frames typeid/length field. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 tid 7 6 5 4 3 2 1 0 tid 32058k avr32-01/12 483 at32uc3a 29.7.25 transmit pause quantum register register name: tpq acces s type: read/write ? tpq: transmit paus e quantum used in h ardwar e generati on of transmitte d pause frames as valu e fo r pa use quantum. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 tpq 7 6 5 4 3 2 1 0 tpq 32058k avr32-01/12 484 at32uc3a 29.7.26 user input/outpu t register register name: usrio acces s type: read/write ? rmii whe n set, this bi t en ab les th e mi i ope rat ion m ode . whe n r e set, i t selec ts th e rm ii m od e . ? eam whe n set, th is bit causes a f ram e t o b e copied to memory , if th is f eatu re is e na bl ed b y t h e e a e b it i n ncfgr . oth erwis e, no frame is copi ed. ? tx_pause togg ling th is bit causes a pause f rame t o be tran smitted. ? tx_pause_zero selec t s e ither zer o o r the tra nsmit qu an t um reg is te r as the tr a nsmitt e d pau se fram e quantu m. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? tx_pause_ zero tx_pause eam rmii 32058k avr32-01/12 485 at32uc3a 29.7.27 wake-on-l an register register name: w ol acces s type: read/write ? ip: ar p request ip address written to define t he least significant 16 bits of the target ip address that is matched to generat e a wake-on- lan event. a valu e of ze ro do es not generat e a n event, even i f th is is match ed by t he received frame. ? mag : magic packet event enable when set, ma gic packet events causes the wol output t o be asserted. ? arp: arp request even t enable when set, arp request events causes the wol output t o be asserted. ? sa1: specific addres s register 1 event enable when set, specific addre ss 1 even ts caus es the wol outp ut t o b e asserted. ? mti : multicast hash event enable when se t, multicast ha sh even ts causes the wol output to b e asserted. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? mti sa1 arp mag 15 14 13 12 11 10 9 8 ip 7 6 5 4 3 2 1 0 ip 32058k avr32-01/12 486 at32uc3a 29.7.28 macb statistic registers th ese registers reset to zero on a r e ad an d st ick at a ll on es when th ey count to thei r maximum value. th ey shou ld b e read frequent ly enough to prevent loss of data. the re ceive statistics register s are on ly increment ed wh en the re ceive ena ble bit is se t i n th e ne two rk con tr ol r eg ister . t o write to these re gisters, b it 7, westat, i n t he network cont ro l re gis ter , ncr, must be set. the statistics register block c ontains the following registers. 29.7.28.1 pause fram es receiv ed register register name: pfr acces s type: read/write ? frok: pause frames received ok a 1 6-b it re gist er cou nti ng th e numb er of good p ause fr ames received . a g ood fram e has a length o f 64 t o 1518 (1 536 if bit 8, big, i n networ k configuratio n register, ncfgr, is se t, 1024 0 if bit 3, jframe in n etwor k configuratio n register, ncfgr, is s et) an d ha s no fcs, alignment o r re ceive symbol errors. 29.7.28.2 frames transmitte d ok register register name: f to acces s type: read/write ? f t ok: fr a mes t r ansmit ted ok a 24 -bit register counting th e number of fram es successfully transmitted, i.e. , n o underru n an d no t to o many retries. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 frok 7 6 5 4 3 2 1 0 frok 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ftok 15 14 13 12 11 10 9 8 ftok 7 6 5 4 3 2 1 0 ftok 32058k avr32-01/12 487 at32uc3a 29.7.28.3 single colli sion fr ames register register name: scf acces s type: read/write ? s cf: single collision frames a 16-bit registe r counting the number of frames experiencing a single collision be f ore being successf ully transmitt ed, i.e., no underrun. 29.7.28 .4 m ul tico l li si o n f rames r egister register name: mcf acces s type: read/write ? m cf: multicollis ion frames a 16-bit regi st er counting th e number of frames experienci ng between two an d fifteen collisions prio r to being successfully transmitted , i.e. , no und erru n a nd n ot to o m any r et ries. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 scf 7 6 5 4 3 2 1 0 scf 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 mcf 7 6 5 4 3 2 1 0 mcf 32058k avr32-01/12 488 at32uc3a 29.7.28.5 frame s received ok regis ter register name: fro acces s type: read/write ? frok: frame s receiv ed ok a 24-bi t register count ing th e number of go o d fra mes receiv ed, i.e., addre ss reco gnize d and s u ccessfully copied t o mem- or y. a good fram e is of lengt h 64 to 1518 bytes (15 36 if bit 8, big, in networ k configuratio n register , ncfg r, is set, 10240 if bit 3, jframe i n n etwor k configuration register , ncfg r, is set) an d ha s no fcs, alignment o r re ceive symbol errors. 29.7.28.6 frame s chec k seque nce errors register register name: fcse acces s type: read/write ? fcse: fr am e chec k sequence errors an 8 -bi t register counti ng frames that ar e a n integral number of bytes, h ave bad crc an d ar e between 6 4 and 1518 bytes in len gth (153 6 if bi t 8, big, in networ k configuration register, ncfgr, is s et, 102 40 if bi t 3, jframe in netw ork configura- tion register , ncfgr , is set) . this register is also increment ed if a sym bol e rro r is d etecte d a nd t he fram e is o f valid len gth an d ha s a n integr al number of bytes. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 frok 15 14 13 12 11 10 9 8 frok 7 6 5 4 3 2 1 0 frok 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 fcse 32058k avr32-01/12 489 at32uc3a 29.7.28 .7 a lign me n t err ors r eg i st er register name: ale acces s type: read/write ? a le: alignm en t e r r o rs an 8- bit register counting frames that are no t an integral number of byt es lo ng and have ba d crc when their lengt h is trun- cated t o a n in teg r al nu mb er of byte s and ar e be tw ee n 64 an d 1518 by te s in length (1 536 i f bit 8 , bi g , in n etwork configurat ion register, ncfg r, is set, 10240 if bit 3, jframe in networ k configuration regis ter, ncfgr, is se t). this regis- ter is als o incremented if a symbo l erro r is detecte d and the frame is of valid length and does not have an integral number of bytes. 29.7.28.8 deferred transmission frames register register name: dtf acces s type: read/write ? d tf : defe r r ed tr an sm i s sion fram es a 16 -bi t r egi ster countin g th e numbe r o f fr ame s expe riencin g de ferra l due to carrier se nse being activ e on their first attempt at transmis s ion. frames invo lved in any collis ion are not c ounted nor are fr ames that experienced a tran sm it underrun. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ale 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 dtf 7 6 5 4 3 2 1 0 dtf 32058k avr32-01/12 490 at32uc3a 29.7.28.9 late collisions register register name: lcol acces s type: read/write ? lcol: late collisions an 8-bit regi ster co unting the number of frames that ex perience a collis ion after the slot time (512 bits) ha s expired. a lat e collision is counted t w ice; i.e., both as a collision and a late collision. 29.7.28.10 exce ssiv e collisions regi ster register name: excol acces s type: read/write ? excol: excessive collisions an 8-bit register counting the number of frames that failed to be transmitted be cause t hey experienced 16 collisions. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 lcol 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 excol 32058k avr32-01/12 491 at32uc3a 29.7.28 .11 t ran smit underrun errors r eg is ter register name: tund acces s type: read/write ? tund: tr ansmit underruns an 8- bi t regist er counting t he numb er of frames not transmitte d d ue to a t ransmit dma un derrun . if this register is inc re- mented, the n n o othe r st atisti cs re g iste r is incr emente d. 29.7.28 .12 carrie r sens e e r r ors r eg i ster register name: cse acces s type: read/write ? c se: carrier sense er rors an 8 -b it reg iste r cou ntin g th e n umber of frame s t ransm itte d wher e carrier se nse was not se en during transmission or where carrier sense was deasse rted after bein g as serted in a transmit frame without collis ion (no underrun). on ly incremented i n half-duplex mode. the only ef fect of a carrier s e nse error is to increment t his register . the behavior o f t he other statistics register s is unaffecte d by th e detectio n of a carrier se nse error. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 tund 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 cse 32058k avr32-01/12 492 at32uc3a 29.7.28.13 receive resource e r ror s reg iste r register name: rre acces s type: read/write ? rre: receiv e resource errors a 1 6-bit register counting the number o f frames that wer e add r ess matched but coul d no t be copi e d to me mory becau se no r eceive buffer was available. 29.7.28 .14 rece i v e ov err u n errors r eg i ster register name: rovr acces s type: read/write ? rovr: receiv e overrun an 8 -bit register counting the numbe r of frames tha t are address recognized but were not copi ed to memory due to a recei ve dma overr u n. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rre 7 6 5 4 3 2 1 0 rre 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 rovr 32058k avr32-01/12 493 at32uc3a 29.7.28.15 receive symbol erro rs register register name: rse acces s type: read/write ? r se: receive symbol errors an 8-bit register counting the number of fram es that had rx_er asser te d durin g r eception . receiv e symb o l e rr or s ar e also counte d as an fcs or alignmen t error if th e fram e is betwee n 64 an d 1518 by tes in leng th (1536 if bi t 8, big , i n network config uration regist er, ncfgr, is set , 10240 if bit 3, jframe in n etw ork configurat ion register, ncfg r, is set). if the frame is larger, it is r ecorded as a jabbe r error. 29.7.28.1 6 exc essiv e le n gth e r rors r eg is ter register name: ele acc es s typ e: read /w ri te ? exl: excessive lengt h errors an 8 -bit register counting t he number of frames receive d exceedin g 151 8 bytes (153 6 if bi t 8, big, in n etwor k configuration register , ncfgr, is set, 10240 if bit 3, jframe in netw ork configuration register, ncfgr, is s et) in l ength but do not have either a crc e rror, a n alignment erro r no r a re ceive symb ol error. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 rse 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 exl 32058k avr32-01/12 494 at32uc3a 29.7.28.17 receive jabber s register register name: rja acces s type: read/write ? r jb: re ce ive ja bb e rs an 8 -bit register counting t he number of frames receive d exceedin g 151 8 bytes (153 6 if bi t 8, big, in n etwor k configuration register , ncfgr, is s et, 1024 0 if bit 3, jframe in networ k configuratio n register , ncfgr, is s et) in l ength and have either a crc e rror, a n alignment erro r o r a receive symbol error. 29.7.28.18 undersize fram es register register name: usf acc es s typ e: read /w ri te ? u sf: und e rsiz e f r ames an 8- bi t r egi ster countin g th e num ber o f frames re ceive d less tha n 6 4 byt e s i n l ength but d o not hav e either a c r c er r or, an alignment error o r a re ceive symbol error. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 rjb 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 usf 32058k avr32-01/12 495 at32uc3a 29.7.28.19 sqe test erro rs register register name: ste acc es s typ e: read /w ri te ? sqer: sqe test errors an 8- bi t registe r countin g the number o f frames where c o l was not ass e rted within 96 bit time s (an interframe gap ) of tx_en bein g deasserte d in ha lf duplex mode. 29.7.28.20 received lengt h fiel d mismat ch register register name: rle acc es s typ e: read /w ri te ? rlfm: receiv e length field mism atch an 8 -bit re gist e r counting th e num be r o f f rame s receiv ed that have a m easured lengt h shorter than that extracted fro m its length field. checking is e nabled throu gh bit 16 o f the networ k configuration register. frames containi ng a ty pe id in bytes 13 and 1 4 (i.e., length/typ e id 0x0600 ) ar e no t count ed as length fiel d errors, neithe r ar e excessive length frames. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 sqer 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 rlfm 32058k avr32-01/12 496 at32uc3a 29.7.28.21 transmitted pause fram es register register name: tpf acc es s typ e: read /w ri te ? t pf : t r ansmit t e d paus e fr am es a 16 -bit register counting th e number of pause frames transmitted. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 tpf 7 6 5 4 3 2 1 0 tpf 32058k avr32-01/12 497 at32uc3a 30. usb on-the-go interface (usbb) re v: 3.1.1.1 30.1 features ? usb 2.0 co mplian t, full-/low -speed (f s/ls) and on- the-go (o tg), 12 mbit/s ? 7 pi pes/endpoints ? 960 byte s of e m bedd ed dual-por t ram (dpram) fo r pipes/endpoints ? up to 2 memor y ban ks pe r pipe/endpoin t (not fo r contro l pipe/endpoint) ? flexibl e pipe/endpoint configuratio n an d management with dedica ted dma channels ? on-chip transceiver s including pull-ups/pull-downs. ? on-chip ot g pa d includi ng vb us analog comparator 30.2 description th e universal serial bus (usb) mc u device comp lies with the un iversal serial bus (usb) 2.0 specification, bu t it does not featur e high-speed usb ( 48 0 mbit/s). ea ch pipe/endpoint can b e co nfigure d i n on e of severa l tr ansfer types. it ca n b e ass oci ate d wit h one or more banks o f a dual-p o rt ram used to store t he curr ent data payload. i f seve ral banks ar e u s e d ( ?ping-po ng ? mode), th e n on e dpra m ba nk is read or writte n b y th e cpu o r t he dma w hile th e o the r is rea d o r writte n b y th e us b macr o core . t h is featur e is manda tory fo r isochro- no us pipes/endpoints. ta ble 30-1 descr ibe s th e h ard war e c onfigur at io n of t h e usb m c u d evic e. the theoretica l maximal pipe/endpoint configuratio n (1600 bytes) exceeds t he re al dpram size (960 bytes). the user needs t o be aware of this wh e n configuring pipes/endpoints. to fully use t he 960 byte s of dpram , the user could for example use th e configuration described in table 30-2. tabl e 30-1. descrip tio n of us b p ip es/endp oints pipe/endpoint mnemonic max. size max. n b . banks dma type 0 p ep0 6 4 by tes 1 n co ntrol 1 pep1 bytes y isochronous/bulk/interrupt 2 pep2 bytes y isochronous/bulk/interrupt 3 pep3 64 bytes y bulk/interrupt 4 pep4 64 bytes y bulk/interrupt 5 pep5 bytes y isochronous/bulk/interrupt 6 pep6 bytes y isochronous/bulk/interrupt tabl e 30-2. exampl e of configuratio n of pipes/endpoints using the whol e dpram pipe/endpoint mnemonic size nb. banks 0 pep0 64 bytes 1 1 pep1 64 bytes 2 2 pep2 64 bytes 2 3 pep3 64 bytes 1 32058k avr32-01/12 498 at32uc3a 4 pep4 64 bytes 1 5 pep5 256 bytes 1 6 pep6 256 bytes 1 tabl e 30-2. exampl e of configuratio n of pipes/endpoints using the whol e dpram pipe/endpoint mnemonic size nb. banks 32058k avr32-01/12 499 at32uc3a 30.3 block diagram th e usb controlle r provides a ha rdwar e device to interf ace a usb link to a data flow stored in a dual-port ram (dpram). th e usb controller requir es a 48 mhz 0 .25% reference clock, which is t h e usb gener ic clock generated from one of the po we r manager oscillators , optionally through one of the po we r man- ager plls. th e 48 mhz cl oc k is used to gene rat e a 12 mhz full-speed (or 1. 5 mhz low-speed) bi t clock from the rec eived usb differential da ta and to transmi t dat a acco rding to full- or low-spee d usb device tolerance. clock r eco very is achieved by a digita l phase-locked loop (a dpll , not repre- sented), which co mplies with th e usb jitter spe cifications. figur e 30-1. block diagram interrupt controller usb interrupts d- vbus usb_vbo f usb gpio controller usb_id d+ user interface power manager usb gclk @ 48 mhz pb dpram usb 2.0 core pep allocation dma hsb mux local hsb slave interface hsb1 hsb0 master slave domain usb clock system clock domain 32 bits hsb 32058k avr32-01/12 500 at32uc3a 30.4 a pplication bloc k diagram depe nding on the usb operat ing mode (device- only, reduced-host or otg mode) and th e powe r source (bus-powere d or self-powered) , there are different typical hardware implemen tations. 30.4.1 device mode 30.4.1.1 bus-powere d device figur e 30-2. bus-po wered device ap plication bloc k diagram 30.4.1 .2 self-powered device figur e 30-3. self-p owered device ap plication bloc k diagram usb usb_id d+ d- usb_vbof vbus usb connector id d+ d- vbus gnd 39 1% 3.3 v regulator vdd 39 1% usb usb_id d+ d- usb_vbof vbus usb connector id d+ d- vbus gnd 39 1% 39 1% 32058k avr32-01/12 501 at32uc3a 30.4.2 host and ot g modes figur e 30-4. host and otg application bloc k diagram 30.5 i /o lines description tabl e 30-3. i/o lin es descripti on name description type active l evel usb_vbof usb vbus on/off: bu s po we r control port output vbuspo vbus vbu s: bus powe r measurement port input high d- d at a - : dif feren t i a l data l i n e - po rt i n put/o u t p ut n /a d+ data +: differential dat a line + port input/output n/a usb_id usb identification: mini connector identification port input low: mini-a pl ug hig h z: mini -b plug usb usb_id d+ d- usb_vbof vbus usb connector id d+ d- vbus gnd 5 v dc/dc generator vdd 39 1% 39 1% 32058k avr32-01/12 502 at32uc3a 30.6 p roduct dependencies 30.6.1 i/ o li nes th e usb_vbof an d usb_id pins are multiplexe d wit h gpio lin es an d may also be multiplexed wit h lines o f othe r peripherals. i n order to u s e them wi th th e usb, th e programme r must first pro- gram t he gpio controll er t o assign them to their usb pe ripheral function s. moreover, if usb_id is used, th e gpio controller must be configured t o enable t he intern al pull-u p resistor of it s pin. if usb_ vbof or usb_id is not used by t he applicatio n, th e correspondin g pin can be used fo r othe r p urpo ses by th e g pi o contr o ller o r by oth e r periphe rals. 30.6.2 power management th e 48 mh z usb clo ck is generate d by a d edicate d gene ric clock from the powe r manager. before using the usb, t he programmer mu st ensure that th e usb gener ic clock (u sb gclk) is enab led at 48 mhz in t h e powe r manager. 30.6 .3 interrupts the usb inter f ace has an interrupt line connected to the interrupt c ontroller. i n order t o handle usb i nterrupts , the interrup t controlle r must be programmed first. 32058k avr32-01/12 503 at32uc3a 30.7 functional description 30.7 .1 usb genera l operation 30.7.1.1 introduction afte r a hardware rese t, the usb controlle r is disabled . when enabled , the usb controlle r runs eithe r i n devic e mode or in ho st m od e accord in g to th e id de tection. if the usb_id pin is not connected to ground, the id bi t is set by hardware (t he internal pull-up resistor of the usb_id pi n must be enabled by the gpio controller) and device m ode is engaged. the id bi t is clear ed by hardware when a l o w level has been detect ed on t he usb_id pin. host mo de is th en engaged. 30.7.1.2 power-on an d reset figure 30-5 describes t he usb controlle r ma in states. figur e 30-5. general states after a h ardware rese t, the usb controlle r is in the reset state. in this state: ?the m acro is disable d (u sbe = 0); ?the macr o cloc k is stoppe d in order t o minimize powe r consumptio n ( frzclk = 1); ?th e pad is in suspend mode; ?the inter nal states an d registers of the devic e an d ho st mo des ar e reset; ?the dpram is not clear ed an d is accessible; ?the i d an d v b u s read-onl y bi ts refle c t th e states o f th e u sb_ id a n d vbu s inpu t pins; ?the otgp ade, vbuspo , frzclk, u sbe, uid e, uimo d and ls bits can be w r itten by software, so that t he user can progra m pads and spe ed befor e enabling th e macro, bu t their valu e is only take n into account once t he macr o is enable d and unfrozen. after setting usbe, the usb con t roller enters the device or the host mode (according to the id detection) in idle state. the usb control l er can be disabl ed at any ti me by clearing usbe. in fact, clearing usbe acts as a ha r dware reset, except t h a t the o tgpade, v bus po, fr zc lk , u ide, uimod a nd ls bits ar e not reset. device reset usbe = 0 504 at32uc3a 30.7.1.3 interrupts on e interrup t vect or is assigned to th e usb interface. figur e 30-6 shows t he structure of the usb i nterrupt system. figur e 30-6. interrup t system usbcon.idte usbsta.idti usbsta.vbusti usbcon.vbuste usbsta.srpi usbcon.srpe usbsta.vberri usbcon.vberre usbsta.bcerri usbcon.bcerre usbsta.roleexi usbcon.roleexe usbsta.hnperri usbcon.hnperre usbsta.stoi usbcon.stoe usb general interrupt usb device interrupt usb host interrupt usb interrupt asynchronous interrupt source udinte.suspe udint.susp udint.sof udinte.sofe udint.eorst udinte.eorste udint.wakeup udinte.wakeupe udint.eorsm udinte.eorsme udint.uprsm udinte.uprsme udint.epxint udinte.epxinte udint.dmaxint udinte.dmaxinte uhinte.dconnie uhint.dconni uhint.ddisci uhinte.ddiscie uhint.rsti uhinte.rstie uhint.rsmedi uhinte.rsmedie uhint.rxrsmi uhinte.rxrsmie uhint.hsofi uhinte.hsofie uhint.hwupi uhinte.hwupie uhint.pxint uhinte.pxinte uhint.dmaxint uhinte.dmaxinte ueconx.txine uestax.txini uestax.rxouti ueconx.rxoute uestax.rxstpi ueconx.rxstpe uestax.underfi ueconx.underfe uestax.nakouti ueconx.nakoute uestax.nakini ueconx.nakine uestax.overfi ueconx.overfe uestax.stalledi ueconx.stallede uestax.crcerri ueconx.crcerre uestax.shortpacket ueconx.shortpackete uestax.nbusybk ueconx.nbusybke upconx.rxine upstax.rxini upstax.txouti upconx.txoute upstax.txstpi upconx.txstpe upstax.underfi upconx.underfie upstax.perri upconx.perre upstax.nakedi upconx.nakede upstax.overfi upconx.overfie upstax.rxstalldi upconx.rxstallde upstax.crcerri upconx.crcerre upstax.shortpacketi upconx.shortpacketie upstax.nbusybk upconx.nb usybke uddmax_control.eot_irq_en uddmax_status.eot_sta uddmax_status.eoch_buff_sta uddmax_control.eobuff_irq_en uddmax_status.desc_ld_sta uddmax_control.desc_ld_irq_en uhdmax_control.eot_irq_en uhdmax_status.eot_sta uhdmax_status.eoch_buff_sta uhdmax_control.eobuff_irq_en uhdmax_status.desc_ld_sta uhdmax_control.desc_ld_irq_en usb device endpoint x interrupt usb host pipe x interrupt usb device dma channel x interrupt usb host dma channel x interrupt 32058k avr32-01/12 505 at32uc3a see section 30.7.2.17 on pag e 520 and section 30.7.3.13 o n page 528 for further deta ils about devic e a nd ho st interrupts. there a re two kind s of general interr upts: processing, i.e. th eir generatio n is part of the normal processing , an d exception, i.e. errors (not related to cpu exceptions). th e processing gener al interrupts are: ?the id transition interrupt (idti); ?the vbus transition interrupt (vbusti); ?the sr p interrup t (srpi); ?the role exchange inter r upt (roleexi). th e except io n g ene ra l in ter rupts are: ?the vbu s error interrupt (vberri); ?the b-connection error interrupt (bcerri); ?the h n p error interr upt (hnperri); ?the suspe nd time-out interrupt (stoi). 30.7.1.4 mcu power modes 30.7.1.4.1 run mode in this mode , all mcu cloc ks ca n run, includin g th e usb clock. 30.7.1.4.2 idle mode in this m ode, the cpu is ha lted, i.e . the cpu clock is stop p ed. the id le mo de is ente red what- ever th e stat e of the usb macro. th e mcu wakes u p on any usb in terrupt. 30.7.1.4.3 frozen mode same as t h e idle mode, except tha t t he hsb mo dule is stopped , so th e usb dma, which is a n hsb master, can n ot be used. moreover, th e usb dm a must be sto pped b efore entering thi s slee p mode in o rde r t o avoi d erra tic behavio r. t he mcu wake s u p on a n y usb int err upt. 30.7.1.4.4 standby, stop, deepsto p and stat ic modes sam e as the fr ozen mode, excep t that the usb ge ner ic cloc k and other clocks a re stopped, so t he usb macro is f rozen. 30.7.1.4 .5 usb clock frozen i n th e run, idle and frozen mc u modes , t he usb macr o ca n be froze n when th e usb lin e is in t he suspe nd mode , by se ttin g th e frzclk bit , wha t red uce s powe r co nsum ptio n. in this case, it is st ill poss ible to access the following elements, b u t only in run mode: ?the otgp ade, vbuspo , frzclk, usbe, uide, uimod and ls bits; ?th e d pra m (through th e usb_fifox _d at a reg isters , b ut not thro ug h usb bu s trans fer s w h ic h ar e fr ozen). moreover , when frzc lk is se t, only the asynchrono us interrup t sources may trigge r th e usb inte rr upt: ?the id transition interrupt (idti); 32058k avr32-01/12 506 at32uc3a ?the vbus transition interrupt (vbusti); ?the wake-u p interr upt (wakeup); ?the host wak e-u p interrupt (h wupi). 30.7.1.4 .6 usb suspend mode : in p eripheral mode , th e udint.s usp bit indicate s th at th e us b line is in t h e suspen d mode . in this cas e, the usb data transceiver is auto matical ly set in s usp end mo de to re duce the consumption. 30.7.1.5 speed control 30 .7 .1.5 .1 devic e m o de when t he usb inte rf ace is in de vice mode , th e spe e d selectio n (fu ll - /low-speed ) depe n ds on which of d + an d d - i s p ul l ed up . t he ls b i t al low s to c onne c t an int e rna l pul l -up r esisto r either on d+ (f ul l-speed mode) or on d- (low-speed mode). the ls bi t should be co nf igured before attachin g th e device, what ca n b e done by cle aring th e detach bit. figur e 30-7. speed selection in devi ce mode 30 .7 .1.5 .2 ho st m ode when t he usb interf ace is in host mode , internal pull-down resistor s ar e connected on both d+ an d d- an d th e inte rface det ec ts the sp e ed of th e conne cted device, whic h is r eflecte d by the spee d bit- field. 30.7.1.6 dpram management pipe s an d endpoin t s c a n onl y b e a lloca te d in a sce nd in g o rd e r ( fr o m t h e p ipe /endpoin t 0 t o t he last pipe/endpoint to be allocated). the firmwa re sha ll therefore configure them in t he same order. t h e a ll o c a tion o f a p ipe /end p oint k i star ts wh en its alloc bit is set. then , the hardwa re allo- cates a me mory area in t he dpram and insert s it between th e k i-1 and k i+1 p ipes/e ndpoin ts. th e k i+1 pipe/endpoint memo ry windo w slides up a nd it s data is los t . note that the following pipe/end- point memo ry window s (from k i+ 2 ) d o not slid e. r pu udcon.detach d+ d- udcon.ls vbus 32058k avr32-01/12 507 at32uc3a disab ling a pipe (penx = 0 ) o r an endpoint (epenx = 0) rese ts neither its a l loc bit nor its configuration (pbk/epb k, psize/epsize, ptoken/epdir , ptype/eptype , pepnum, int- frq). to free its me mory, the firmware should clear i t s alloc bit. the k i+1 pipe/endpoint memo ry windo w th en slid es down an d its data is l o st. no te that the following pipe/endpoint memory windo ws (from k i+2 ) do n o t slide. figure 30-8 illustrates the allocation and reorganization of the dpram in a typical e xample. figur e 30-8. allocation and reorganization of th e dpram ? firs t, the pipes/endpoints 0 to 5 are enabled, configured and allocat ed in ascending order. each pi pe/endpoint then ow ns a memory ar ea in the dpram. ? then, th e pipe/endpoint 3 is disabled, but its memory is kept allocated by th e controller. ? in order to fr ee it s memory , it s allo c bit is the n cleared by the firmware . th e pipe/endpoint 4 me mor y windo w slides d own, but th e p ipe/e ndp oint 5 does not move. ? finally, if the firmware chooses to reconfigure th e pipe/endpoint 3 wit h a la rger size, the controller allocate s a memory area after the pipe/endpoint 2 memory area and automatically slide s u p th e pipe/endpoint 4 me mory win dow. th e pip e/en dpoi nt 5 d oes no t mo ve an d a me mor y co nf lict app ear s as t he me mory win do ws of the pipes/endpoints 4 a nd 5 overlap. the data o f these pipes/endpoint s is potent ially lost. note that: ?there is no way th e data of th e pipe/endpoint 0 c an be lost ( excep t if it is de-allocated) as memory allocatio n a nd de-allocatio n may affect only higher pipes/endpoints; ?deactivating then reactivatin g a same pipe/endpoint with the same configuratio n on ly modifies t em po raril y th e con tr oller dpram p ointer an d si z e fo r th is p ipe/e ndpoint, bu t no thing change s in th e dpram, so h ighe r endpoint s seem to not hav e been moved and their dat a is preserve d as far as n othing ha s bee n writte n or received into th em while changing the allocati on stat e o f the first pipe/endpoint; ?when th e fir m ware se ts t he a llo c bit , the c fgok b it is s et b y hard ware on l y i f the configured siz e and numbe r o f bank s ar e correct compared to thei r maxima l allowe d values fo r t he endpoin t and t o th e maxima l fi fo size (i.e . th e dpram size) , so t h e va lue o f cfgok do es not consider memory allocati on conflicts. fre e memo ry pep0 pep1 pep2 pep3 pep4 pep5 u(p/e)rst.(e) penx = 1 u (p /e )c fgx .a ll o c = 1 fre e me mory pep0 pep1 pep2 pep4 pep5 f r ee memory pep0 pep1 pep2 pep4 pep5 pipe/endpoint 3 disabled pipe/endpoint 3 memory freed fr ee memory pep0 pep1 pep2 pep 3 (lar ge r size) pep5 pipe/endpoint 3 activated pep 4 lo s t m emo ry pep4 conflict u(p /e) rst. ( e) p en3 = 0 pep 3 (alloc stays at 1) u(p/e)cfg3.allo c = 0 u(p/e) r st.(e )pen 3 = 1 u(p/e)cfg3.allo c = 1 pipes/endpoints 0..5 activated 32058k avr32-01/12 508 at32uc3a 30.7.1.7 p ad s u spe nd figure 30-9 shows t h e pad behavior. figur e 30-9. pad behavior ? i n the id le state, th e pa d is put in lo w powe r consumptio n mode. ? i n th e active state, t he pa d is working. fig ur e 30-10 illust rate s t he pad e vents le ading to a pad state change. figur e 30-10. pad events the suspe n d interru pt flag (susp) is set and the wake -u p interrupt flag (wakeup ) is cleare d when a usb ?susp end ? stat e has bee n detected on the usb bu s. th is even t automati cally puts the usb pad in the idl e state. the detection of a non-i d le event sets wakeu p, clears susp and wakes up th e usb pad. moreover , the pa d goes to the idle stat e if the macr o is disabled or i f the detach bi t is s et . it returns t o the act ive stat e when usbe = 1 and detach = 0. idle active usbe = 1 & deta ch = 0 & s uspend usbe = 0 | d eta ch = 1 | suspend susp suspend detected cleared by hardwar e on wake-up wake-up detected cleared by softwar e to acknow ledge the interrupt wakeup p ad state active idle active 32058k avr32-01/12 509 at32uc3a 30.7.1 .8 cust omizin g of ot g ti mers it is possible to re fi ne some otg timers t hank s to the tim page and tim valu e b i t-f iel ds , as show n by figure 30-4. timpage i s us ed to select the otg timer t o access while timvalue indicat es the time-out value of the selec t ed timer. ti mp ag e an d ti m va l u e ca n be rea d o r writte n . befo r e wr itin g t he m, the fi rmw are s hould unlo ck write accesses b y settin g the unlock bit. th is is no t required fo r read accesses, except bef ore accessing ti mpage if it has t o be writt en in ord er to r ead the ti mvalue bit -field of anothe r otg timer. 30.7.1 .9 plug-in detection th e usb c onnection is det ecte d f rom th e vbu s pad. figu re 30-11 shows the architecture o f the plug-i n detector. figur e 30-11. plug -i n de tect ion in put blo c k diagram th e contro l lo gic o f the vbus pa d o utput s two signals: ?the session_valid sign al is high when the voltage on the vbus pad is hi gher than or equa l to 1.4 v; ?the va_vbus_va lid signa l is hi gh when the voltage on t he vbus p ad is higher tha n or equa l to 4.4 v. i n de vi ce m ode, th e vbus bi t follows th e sessio n _vali d comp arato r output: ?it is s e t when the voltag e on t he vb us pa d is higher tha n or equal t o 1.4 v; tabl e 30-4. customizing of otg timers timpage 00b: aw aitvrise time-out ([o tg] chapte r 6.6.5.1) 01b: vbbuspulsing time-out ([otg] ch apter 5.3.4) 10b: pdtmoutc nt time-out ([o tg] chapter 5.3.2) 11b: srpdettmout time-ou t ([o tg] chapter 5.3.3) timvalue 00b 20 ms 15 ms 93 ms 10 s 01b 50 ms 23 ms 10 5 ms 100 s 10b 70 ms 31 ms 11 8 ms 1 ms 11b 1 00 ms 40 ms 13 1 ms 11 ms vbusti usbsta vbus vbus usbsta gnd vdd pad lo gic logic session_valid va_vbus_valid r pu r pd vbus_pulsing vbus_discharge 32058k avr32-01/12 510 at32uc3a ? it is c lear e d w hen the voltag e o n th e v bu s p a d is l o w er tha n 1.4 v. in host mode , the vbus bi t f oll ows a n hysteresis base d on session_va lid and va_vbus_valid: ?it is s e t when the voltag e on t he vb us pa d is higher tha n or equal t o 4.4 v; ? it is c lear e d w hen the voltag e o n th e v bu s p a d is l o w er tha n 1.4 v. the vb us transition interrup t (vbu sti) is raise d on each transitio n of the vbus bit. th e vbus bit is effective whether th e usb macr o is enabled or not. 30.7.1.10 id detection figure 30-12 show s how the id transitions ar e detected. figur e 30-12. id detectio n inpu t bloc k di agram the usb mode (device or host) can be either detecte d fr om th e usb_id pin or so ftware selected from th e uimod bit, according t o th e uide bit. this allows t h e usb_id pin t o be used as a g ener al p urp ose i/ o pi n eve n when the usb interface is enabled. by default , th e usb_id pin is s electe d (uid e = 1) and th e usb macr o is i n devic e mo de (id = 1 ), what correspond s to th e case wher e no mini-a pl ug is connected, i.e. no plug or a min i -b plug is connected and the usb_ id pin i s kept high by t h e intern al pull-up resistor from the gpio con- trolle r (w hich must be enabled if usb_id is used ). the id transition interrupt (idti) is raised on each transition of the id bit, i.e. when a mini-a plug (host mode) is connected or disconnected. thi s does not occur wh e n a mi ni-b plug (device mode) is con nect ed or disconnected. th e id bit is effective whether th e usb macr o is enabled or not. r pu uimod usbcon usb_id id usbsta vdd uide usbcon 1 0 idti usbsta g p io c o ntroll er 32058k avr32-01/12 511 at32uc3a 30.7.2 usb d evice operation 30.7.2.1 introduction in de vice mode, th e usb controlle r suppor ts full- and low-speed data transfers. in a ddition to the default control endpo int, six endpoints a re provided, which can be config ured with th e type s isochronous, bulk or interrupt, as describ ed in tabl e 30-1 on p ag e 497. th e device mo de starts in th e id le state, so t he pa d consumpt ion is reduced to th e minimum. 30.7.2.2 power-on an d reset fi gur e 30-13 descr ib es th e usb contr olle r device mod e ma in state s. figur e 30-13. devic e mode states afte r a hardware rese t, the usb controlle r devic e mode is in t h e reset stat e. in th is state: ?the macr o cloc k is stoppe d in order t o minimize powe r consumptio n ( frzclk = 1); ?the internal registers of t he devic e mod e ar e reset; ?the endpoint ban ks ar e de-allocated; ?neith er d+ nor d- is pull e d u p (detac h = 1). d+ or d- will be pulled up accor d ing to the sele ct ed speed as soon a s the detac h bit i s cleared an d vbus is present. see section 30.7.1.5.1 o n page 506 for furthe r details. when the usb ma cro is ena bled (usbe = 1) in devic e m ode (id = 1), it s device mode state goes to t he idle state wit h minimal power consumption. this does not require the usb clock t o be activated. th e usb controller device mo de can be disabl ed an d reset at any time by disabling th e usb macro (usbe = 0) or when host m ode i s engaged (id = 0). 30.7.2 .3 usb reset th e usb bus reset is ma nag ed by hardware. it is i nitiat ed by a connect ed host. when a usb r eset is de tecte d o n the usb line , th e following operatio ns ar e perfor med by the controller: ?all t he e ndp oints ar e disab led, excep t th e default co nt rol endpoin t; ?the default control endpoint is reset (see section 30.7.2. 4 o n pag e 512 fo r mo r e de ta ils ); ?the data toggle sequen ce o f th e default contro l endpoint is cleared; ?a t th e en d o f the reset process , the en d of reset interrup t (eorst) is raised. reset idle hw reset usbe = 0 | id = 0 512 at32uc3a 30.7.2 .4 endpoi nt reset an en dpoint ca n be reset at a ny ti me by setting it s eprstx bit in t he uerst register. this i s recommended befor e using an endpoint upo n hardware reset or wh e n a usb bus reset has bee n received . this resets: ?the inter nal stat e machin e of th is endpoint; ?th e receiv e an d transmit ban k fifo counters; ?all the register s o f th is endpoint (uecfgx, u es t ax , ueconx), exc ep t i ts configuratio n (alloc , epbk, e psize, epdir , eptype ) and it s da t a toggl e sequenc e bi t-f iel d (d tse q ). n ote that the interrup t source s lo cate d i n th e u es ta x reg iste r ar e not cleare d whe n a u s b bu s reset h as be en received. the endpoint configuration remains active and the e ndpoint is still enabled. th e endp oint reset m a y be associa te d with a clear o f the da ta to gg l e seque nce as an an swer to t he clear_feature usb request. th is ca n be achi eved by settin g th e rstdt bit (b y setting t he rstdts bit). in th e en d, the fi rmwa re has t o clear th e eprstx bit to complet e the reset ope rat ion an d to s tart usin g t h e f i fo. 30.7.2 .5 endpoi nt activation the e ndpoint is maintain e d inacti ve an d reset (see section 30 .7. 2.4 o n p age 512 f or more detai ls) as long as it is disabled (epenx = 0). th e data t o ggle seq uence bit-field (dtseq) is also reset. th e algorith m represente d on figur e 30-14 must be followe d in orde r to activat e a n endpoint. figur e 30-14. endpoint activation algorithm as lon g a s t he endpoint i s n o t cor rectly co nfigur ed ( cfg o k = 0) , t he c o n t rolle r doe s n ot acknowledge th e packets sent by t he host to this endpoint. th e cfgok bi t is set by hardware on ly if the configured size and numb er of banks a re correct compared to their maximal allowed values for the endpoint (see table 30-1 on page 497) an d to t he m a xi mal fi fo s iz e (i.e. th e dpra m size). endpoint activation cfgok == 1? error yes endpoint activated e nable t he en dpoi n t. epenx = 1 test if the endpoi nt configuration is co rre ct. uecfgx eptype epdir epsize epbk alloc c onf i gure the endpoi nt: - type ; - d irection; - size; - number of banks. allo cate the configured dpram banks. no 32058k avr32-01/12 513 at32uc3a see sectio n 30.7.1.6 o n pag e 506 fo r m o r e deta ils ab out dpram managemen t. 30.7.2 .6 a ddres s setup th e usb device addr ess is set up according to t he usb protocol: ?afte r a ll kinds of r esets , th e usb devic e ad dres s is 0; ?the host sta r ts a setu p transac tion with a set_addr ess(addr) request; ?the firmwar e records th is addr ess into the ua dd bit-field, leav ing th e adde n bit cleared, so the a c tual address is still 0; ?the firmware send s a zero-length in pa cke t from t he contro l endpoint; ?the firmwar e enables the recorded usb d e vice address by setti ng adden. once t h e usb de vice addres s is configured, t he controller filters t he packets t o only accept those targetin g th e addr ess stored in uadd. uadd and a dden shall not be written all at once. uadd a n d adden are cleare d by hardware: ?on a h ardware reset; ?w hen the usb macro is disabl ed (usbe = 0); ?whe n a usb reset is detected. whe n uadd o r a dde n i s clea red , th e defaul t d evic e a ddr es s 0 is u se d. 30.7.2.7 suspen d and wake-up whe n an id le usb b u s state has b e en d et ecte d fo r 3 ms , th e c ontr olle r ra ises t he susp e nd int er- rupt (susp). t h e firmware may then se t the frzclk bit to red uce powe r consumptio n. the mcu ca n also en ter the id le or froz en sleep mode to lowe r agai n power consumption. to recove r from the suspen d mode , th e firmware shou ld wait for the w ake-u p interrupt (w akeup), which is raised when a non-idle event is detected, then clear frzclk. as the wa keup interr upt is r aised when a non-idle ev en t is de t ect ed , it c an occu r whe ther the controller is in the s u spend mode or not. th e su sp and wakeup interr upts are thus indepen- dent o f ea ch ot he r excep t tha t on e?s fla g is clea re d by hardwa re wh en the othe r is ra i se d. 30 .7 .2.8 det a ch th e rese t valu e o f the detach bi t is 1. it is possible to initia te a device re-enumeration simply b y setting then clearin g detach. detach ac ts on the pull-up connections of th e d+ and d- pad s. see section 30.7.1.5. 1 on pag e 506 for further details. 30 .7 .2.9 remo t e w ake- up t he remo te wake-u p reque st (als o know n as upstream resume ) is th e on ly on e th e device ma y send on i t s own initiative, but th e de vice shou ld have beforehand been allowed to by a device_remote_wake up request from th e host. ? firs t, th e usb controller mu st have detecte d a ?suspend? stat e on the bus , i.e. the remote wake-up request ca n on ly be sent after a susp interrup t has been raised. 32058k avr32-01/12 514 at32uc3a ? th e firmwar e may then set th e rmwkup bit t o send a n upstrea m resume to the host for a remote wake-up. this w ill automati cally be done by the controller a f ter 5 ms of inactivity on th e usb bus. ? whe n th e controlle r sen ds th e upstrea m resume, the upstream resu me interrupt (uprsm ) is raised an d su s p is cl eare d by h ardware. ? r mwkup is cleared by hardwar e at th e end o f th e upstream resume. ? if the controller detect s a va lid ?en d of resume ? signa l from the host, the en d of resume interr upt (eorsm) is raised. 30.7.2.10 stall request fo r eac h endpoint, th e stal l management is performe d using: ?the stal l request bi t (st allrq) to initiat e a stall re quest; ?th e stall ed interrup t (stalledi) raise d whe n a stal l handshak e ha s been sent. to an swer th e nex t re qu est wit h a stal l handsh ake, stal lr q h a s to b e se t by se tt in g the stallr qs bi t . all follow i ng re que s ts will be discarded (rxout i, etc. w ill not be set) and hand- shaked with a s tall un til the st allrq bit is clear ed , wha t is d one by hardwar e wh en a new setup packet is r eceived (for control endpoints ) or when th e stallrqc bit is set. each ti me a stal l h andshake is sent, the stall edi flag is se t by th e usb cont roller an d the epxint interrupt is raised. 30.7.2.10.1 special considerations for contro l endpoints if a setup packet is received into a control endpoin t for which a sta l l is requested, the rece ived setup interru pt (rxstpi) is rais ed an d stallr q an d stalle di are cleared by hardware . th e setup has t o be acked. this management simplifies the enumeration process management . if a command is not sup- port e d or co ntain s an e rror, the f i rmwa re re ques t s a st all a nd c a n retu rn to t h e m ai n ta sk, waiting for th e next setu p request. 30.7.2.10.2 stall handshake an d retr y mechanism the retr y mechanism has priority over the stall handshake. a stall handshake is sent i f the stallr q bit is s et a nd i f there is n o retr y required. 30.7.2 .11 ma nag emen t of cont rol en dpoin ts 30.7.2 .11 .1 over view a setup r equ est is alwa ys acked. when a n e w setup packe t is received, th e received setup interrupt ( r xstpi) is raised , bu t not the received ou t data interrupt (rxouti). the fifocon a nd rwall bi ts are irrelevant fo r control endpoints. th e firmware shall therefore neve r use them on thes e endpoints. wh en read, their value is always 0. contr ol endpoints ar e manage d using: ?the recei v ed setu p interr upt (r xstpi) whic h is ra ised when a new setup pa cke t is received an d which sha ll be cleared by firmware to acknowledge the packet and to free the bank; 32058k avr32-01/12 515 at32uc3a ?the received out data interrupt (rxouti ) wh ic h is raise d w hen a n e w ou t p ack et is received an d which sha ll be cleared by firmware to acknowledge the packet and to free the bank; ?the transmitted in data interrupt (txini ) which is raised when t he current ba nk is read y to accept a n e w in packet a nd which shall be cleared by firmware to send the packet. 30.7.2 .11 .2 contr ol w rite fi gur e 30 - 15 shows a contr o l write transaction . during th e sta tus stage, the controlle r will not necessarily se nd a nak o n the fir st in token: ?if t h e firmwa re know s the exact number of descriptor byte s that must be read, it can then anticipat e th e status stag e a nd sen d a zero-lengt h packet after th e next in token; ?or it ca n read the byte s and wait for t he nake d in interr upt (nakini ) which tells that all th e byt es hav e be en sent by th e h ost and that the transaction is n o w in th e status stage. figur e 30-15. control write 30.7.2.11.3 contr ol read figure 30-16 shows a control re a d transaction. the usb controller has to m anage the simulta- neou s writ e requests from the cpu an d the usb hos t. figur e 30-16. control read a n ak h andshake i s always ge nerated o n th e firs t statu s stag e co mm and. when th e controller detect s th e status stage, all the data written by th e cpu is lost an d clearing txin i ha s no effect. th e firmware checks i f th e transmission or th e receptio n is complete. setup rxstpi rxouti txini usb bus hw sw out hw sw out hw sw in in nak sw data setup status setup rxstpi rxouti txini usb bus hw sw in hw sw in out out n ak sw sw hw wr enable host wr enable cpu data setup status 32058k avr32-01/12 516 at32uc3a the out re try is always acke d. this recept i on sets rxouti and txini. handle this wi t h the following so ftware algorithm: set txini wait for rx outi or txini if rxouti, then cl ear flag and return if txini, then continue once the out status stag e ha s be en received, th e usb controlle r waits fo r a setu p request. th e setup req u est ha s p r iority over an y ot her re quest an d ha s to be acked . this me an s that any oth er flag sh ou l d b e clear e d and the fif o rese t whe n a setup is received. the firmwar e has to take care of t he fac t tha t t he byte counter is reset when a ze ro-length out pack et is received. 30.7.2.12 management o f in endpoints 30.7.2 .12 .1 over view in packets are sent by the usb device contr oller upon in reques ts from t he host. all th e data can be writte n by th e firmware which ac knowledges or not th e ba nk wh en it is f ull. th e endpoint m ust be configured first. the txini bi t is set by ha rdware at the same time as fif ocon when the current bank is free . this trigger s an epx int interrup t if txin e = 1. txin i shall be cleared by s oftware (b y setting th e txinic bit) to acknowledge th e interrupt, what has n o effect on th e endpoint fifo. the firmware the n writ es into t he fi fo an d clears t he fifocon bit t o allow t he usb controller t o send t he data. if th e in endpoint is com pose d o f multiple banks, this also switches to th e next ba nk. th e txini an d fif ocon bits ar e updated by hardwa re in accordan ce with the sta tus of the ne xt bank. txin i shall alwa ys be cleare d befor e clearing fifocon. th e rwall bit is set by hardware when th e cu rrent ban k is no t fu ll, i.e. the software can write furthe r data into the fifo. figur e 30-17. exampl e of an in endpoint wit h 1 data bank in data (bank 0) ack txini fifocon hw write data to cpu ba n k 0 sw sw sw sw in nak writ e data t o cp u bank 0 32058k avr32-01/12 517 at32uc3a figur e 30-18. exampl e of an in endpoint wit h 2 data banks 30 .7.2.1 2.2 d e taile d de scription th e data is w ritte n by th e firmware, following th e nex t flow: ?w hen the bank is empty, txini and fifocon are set, what t riggers an epxint inter r upt if txine = 1; ?the firmware acknowledges the interrupt by clearing txini; ?the firmware writes the data into th e current bank by usin g th e usb pipe/endpoin t x fifo data register (usb_fifox_data) , un til all t he da ta fram e is written or the bank is f ull (in which case rwal l is cleared by hardware an d byct reaches th e endpoint size); ?the firmware allows t he controller to send the ba nk and swit ches t o t he nex t bank (i f a ny ) by clear ing fifocon. if the endpoint uses severa l banks, the current o ne can be writte n by the firmware while th e pre- viou s on e i s bein g r ea d b y t he host . the n , w h en th e firmwar e c lea r s fif ocon , t he follow ing ba nk may alr ead y b e fr ee a nd txin i is se t imm edia tely. an ?abort ? stage can b e pr oduced when a zero-len gth out packet is received during an in stage of a control or isochron o us in transaction. t he killbk bi t is used to kill the last writ ten bank. th e best way t o manage this abort is t o apply th e algorithm represente d on figure 30-19. in data (bank 0) ack txini fifocon writ e data to cpu ban k 0 sw sw sw sw in data (bank 1) a ck writ e data to cpu bank 1 sw hw wr it e dat a t o cpu bank0 32058k avr32-01/12 518 at32uc3a figur e 30-19. abort algorithm 30.7.2.13 management o f out endpoints 30.7 .2.13.1 overview o ut pac kets are sent by th e h ost. a l l th e dat a c an be rea d by th e firm ware whic h ackn owledge s or not th e ban k w he n i t is em pty. th e endpoint m ust be configured first. th e rxou ti bit is se t by ha rdwa re at th e sa me time as fifocon when th e current ban k is full. this trigger s an epx int interrup t if rx oute = 1. rxou t i s hal l b e clea r e d by softwar e (b y sett ing the r xouti c b it ) t o ack no wledg e t he inter rup t, what ha s n o effect on th e endpoint fifo. the firmware the n re ads from t he fi fo and clears the fifocon bi t to fr ee th e bank. if the out endpoin t is composed of multiple b a nks, this also switches to th e next ba nk. th e rxou ti and fifoco n bits are update d by hardware i n accord ance wit h th e status of th e next bank. r xo ut i shal l a lw a ys b e cleared b efor e cle a rin g fif ocon. th e rwall bi t is set by hardware when t he current b ank is not empty, i.e. th e softwa re can read furthe r data fro m th e fifo. endpoint abort abort done abort is based on the f act that no bank is busy, i.e. that nothi ng has to be sent. disabl e the txini interrupt. eprstx = 1 nbusybk == 0? yes txinec = 1 no killbks = 1 killbk == 1? yes kill the last wr itten bank. w ait fo r the end of th e proc edur e. no 32058k avr32-01/12 519 at32uc3a figur e 30-20. exa mp l e o f an o ut end point w it h 1 da ta b ank figur e 30-21. exampl e of an out en dpoint wit h 2 data banks 30 .7.2.1 3.2 d e taile d de scription th e data is r e ad by the firmware, following th e nex t flow: ?w hen the bank is full, rxouti and fifocon are set, what t r iggers an epxint interr upt if rxoute = 1; ?the firmwar e acknowledges the interrupt by clearing rxouti; ?the firmware can read the byte count of th e current bank fr om byct to know ho w many bytes to read, ra ther than polling rwall; ?the fi rmware rea ds th e dat a from th e current bank by usin g th e u sb p ipe/e n dpoint x f ifo data register (usb_fifox_data), until all the expect ed data fram e is rea d or th e ban k is empty (i n wh ich case rwal l is cleared by hardware and byct r eache s 0); ?the fi rmware fr ees th e ban k an d switch e s t o the ne xt b ank (if any) b y clearin g f i foco n. if the endpoint uses s everal banks, th e current on e can be read by the firmware while t he follow- ing o ne is b eing written by t he host . then, whe n th e firmware clear s fifocon, the following ba nk ma y alread y b e read y and rxouti is set immediately. 30.7.2.14 underflow this error exists only for isochro n ous in/o u t endpoint s. it raises the underflow interrupt (underf i), what triggers an epx int interrupt if un derfe = 1. an u nderfl ow ca n occu r during in sta ge i f th e ho st attempts t o read from an em pt y ba nk. a zero- lengt h packet is the n automatically sent by th e usb controller. out data (bank 0) ack rx outi fifocon hw out data (bank 0) a ck hw sw sw sw r ead data from cpu ba n k 0 r ead data from cpu b an k 0 nak out data (bank 0) ack rxouti fifocon hw out data (bank 1) ack sw sw rea d data from cpu ban k 0 hw sw rea d data from cpu ban k 1 32058k avr32-01/12 520 at32uc3a an u nderflow can n o t occur during out st a ge on a cp u action , since th e firmware ma y read on ly if th e ban k is not empt y (rxouti = 1 o r rwal l = 1). an underflow can als o occur during out stage if the hos t sends a packet while the bank i s already fu ll. typically, th e cpu is no t fast enough . th e packet is lost. an un derflow can not occur during in sta ge on a cpu action, since t he firmware ma y write only if the ban k is not full (txini = 1 or r wall = 1). 30 .7 .2.1 5 overfl ow th is error ex ists for al l endpoint types. it raises the overflow interrup t (overfi), wh at triggers an epxint interrupt if ove r fe = 1. an ove rflow can occur d uring out stage i f t he host attempts to write into a ba nk that is t o o small for t he packet. the packet is acknowledged and t he received out dat a int errupt (rxouti ) is raised as if no o v erflow had occu rred. the bank is filled with all th e first by tes o f th e p acke t tha t fit in. an overfl ow can not occur during in stag e on a cpu ac tion, since the firmware may write only i f the b ank is no t full (txini = 1 o r rwall = 1 ). 30.7.2.1 6 crc error this error exists only for isochronous o u t endpoints. it raises the crc er ror interrupt (crcerri), wh at triggers an epxint interrupt if crc e rre = 1. a crc e rro r can occur during ou t stage i f the usb c ontroller detects a corrupted received packet. th e out packet is s tored in th e bank as i f no crc e rror ha d occurred (rxout i is raised). 30.7.2.17 interrupts se e th e structure of the usb d evice interrup t syste m on figur e 30- 6 o n pag e 504. there are two kinds o f device in terrupt s: processing, i.e . t heir generat ion is part o f t he normal processing , an d exception, i.e. errors (not related to cpu exceptions). 30.7.2.17.1 globa l interrupts th e processing devic e globa l interrup ts are: ?the suspe nd interrupt (susp); ?the start of fram e interrupt (sof) wit h no frame number crc erro r (fncerr = 0); ?th e end o f rese t i n terr upt (e orst ); ?the wake-u p interr upt (wakeup); ?the end of resume interrupt (eorsm); ?the upstream resume interrup t (uprsm); ?the endpoint x inter r upt (epxi nt); ?the dma c hann el x interr upt (dmaxint). th e exceptio n de vice glob al interrupts are: ?the start of fram e interrupt (sof) wit h a frame number crc error (fncerr = 1). 32058k avr32-01/12 521 at32uc3a 30.7.2.17.2 endpoin t interrupts th e processing devic e endpoint interrupts are: ?the transmitted in data interrupt (txini); ?the recei v ed out dat a inter r upt (rxouti); ?the recei v ed setup interr upt (rxstpi); ?the s hort packe t i nterrupt (shortpacket); ?the number of bu sy ba nks interr upt (nbusybk). th e exceptio n de vice endpoint interrup ts are: ?the underfl o w interr upt (underfi); ?the nake d out interrupt (nakouti); ?the nake d in interrupt (nakini); ?th e overflow interrup t (overfi); ?the stall ed interrupt (stalledi); ?th e crc e r ro r in terrupt (crcerr i); 30.7.2.17.3 dma interrupts th e processing device dma in terrupts are: ?the end of usb transfer stat us interrup t (eot_sta); ?th e end of channe l buffer status interrupt (eoch_buff_sta); ?the descriptor load ed status interrupt (desc_ld_sta). ther e is n o exception device dma in terrupt. 32058k avr32-01/12 522 at32uc3a 30.7.3 usb hos t operation 30.7.3 .1 description of pipes for the usb con troller in host mode, t he te rm ?pip e? is used inst ead of ?endpoint ? (used in device mode). a hos t pipe c orresp onds to a device endpoint, as described by th e figure 30 -22 from th e usb specification. figur e 30-22. usb communi c ation flow in ho st mode , t he usb controller associates a pi pe to a device endpoint, consider ing the device configur at ion de scriptors. 30.7.3.2 power-on an d reset figu re 30- 23 descr ib es th e usb con trolle r h os t mode ma i n stat es. figur e 30-23. host mode states afte r a hardware rese t, the usb c ontroller hos t mode is in t he reset state. when the u sb macro is enabled (u sbe = 1) in host mode (id = 0), its host m o de state goes to th e idl e st a te. i n t h is s ta te, the c ont roller w ait s for d evi ce co nnec ti o n w it h m inima l p owe r c on- sumption. t he usb pad should be in the idle state. on ce a device is connect ed, the macro ente rs th e read y state, what d oes no t require the usb cl oc k to be ac tivated. ready idle dev ice disconnection 523 at32uc3a th e controlle r enters t he suspend stat e when the usb bu s is in a ?suspend? state, i.e. when the host mode does not generate the ?start of frame? . in th is state , the usb c onsumpt ion is mini- mal. the host m ode exits t he suspe nd state when starting to generate the so f over t he usb li ne. 30.7.3 .3 device detection a device is det ecte d by th e usb controlle r ho st mo de when d+ or d- is no longe r tied low, i.e. when the device d+ or d- pull-up resistor is conn ected. to enable th is detection, the ho st con- troller has to provide th e vbus power supply t o the de vice by setti ng th e vbusrq bit (b y setting the vbus r qs bit). th e device disconnection is d etected by t h e ho st contro ller when bo th d+ an d d - are pulled down. 30.7.3 .4 usb reset the usb co nt roller sends a usb bus reset w h en the firmwar e sets t he reset bit. the us b rese t sen t interru p t (rsti ) is ra ised when th e usb rese t has be e n s en t. in th is case , a ll the pipe s are disabled an d de-allocated. if th e bu s wa s pr evi ousl y i n a ?su spen d ? st a t e (sof e = 0), th e u sb contr oll e r automa tical ly switches it to the ?resume? state, the hos t wake-u p interrup t (hwupi) is raise d and the sofe bit is set by hardware in o rder to generat e sofs immediat ely after the usb res et. 30.7.3 .5 pi p e reset a pipe can b e r e set at an y tim e by setting its prstx bit in th e uprst re gi ster. th is is recom- mende d before using a pi p e upon hardwar e reset or wh en a usb b us reset has been sent. this resets: ?the inter nal stat e machin e of th is pipe; ?th e receiv e an d transmit ban k fifo counters; ?all the register s o f th is pip e (upcfgx, upstax, upconx), except its configurat ion (alloc, pbk, psize, p tok en, ptype, pepn um, intfrq) a nd its data toggle sequence bit-fiel d (dtseq). the pipe co nfiguration re m ains acti ve and the pipe is st ill enabled. the pipe reset may be associa t ed with a cle ar of t he data t oggle sequence. this can b e achi eved by settin g th e rstdt bit (b y setting the rstdts bi t). in the end , the firmware has t o clear th e prstx bit to complete th e reset operatio n an d to start u sin g th e f ifo. 30.7.3 .6 pipe activation the pi pe is maintained inactive an d rese t (see s ecti on 3 0.7.3. 5 o n p age 52 3 fo r more details ) as lon g a s it is dis able d ( penx = 0). the data toggle sequenc e bit-fiel d (dtseq ) is als o reset. th e algorith m represente d on figur e 30-24 must be followe d in orde r to activat e a pipe. 32058k avr32-01/12 524 at32uc3a figur e 30-24. pipe activati on algorithm a s l ong as th e p i pe i s no t co r rectl y config ure d (cf go k = 0) , the con tr oller ca n no t sen d pa ckets t o th e d evi ce throug h th is pipe. th e cfgok bi t is set by hardware on ly if the configured size and numb er of banks a re correct compar ed to thei r ma ximal allowed values for th e pipe (see table 30-1 on pa ge 497 ) and to the maxima l fifo size (i.e . the dpram size). see sectio n 30.7.1.6 o n pag e 506 fo r m ore details ab out dpram manag em e n t. once t he pi pe i s co rrect ly c on figur ed (c fgo k = 1 ), onl y t he ptoke n an d intfrq bit-fie ld s can b e modified by s oftware . in tfrq is meaningless fo r non-interrupt pipes. when s tarti ng an enumeration, the firmware gets the device descriptor by se nding a get_descriptor us b request. this descriptor co n tai ns th e maxim a l p acke t s iz e o f the device default control e n dpoint (bmaxpacketsize0) a nd the firmwa re re-configures the size o f the default contro l pipe with th is size parameter. 30.7.3 .7 addres s setup on ce th e device has answered the first host requests with th e defaul t devic e addr ess 0 , the host assigns a n e w address to the device. the host controller has to send a usb rese t to the device and t o send a set_address(addr) setup request with the new address t o be used by the de vice . once thi s setu p tra n sac ti o n is o ver, the firmware writes the new addres s into the had dr bit-field. all following requests , on all pipes, w ill be performed us ing this new address. when the hos t cont roller se nds a usb re set, the haddr bit-field is re set by hardware and the follow ing host reques ts will be performed using the de f ault device addres s 0. 30 .7.3.8 r em ote wake- up the controlle r host mode enters the suspen d state wh en the sofe bi t is cleared. no more ?start o f fr ame? is sent on the usb bus a nd the usb d evice enter s the suspend state 3 m s later. the device awakes the host by sending an upstream resume (remot e wake-up feature). wh en the host cont roller detects a non-idle s t ate on t he usb bus, it raises the host wake-up pipe activation cf gok = = 1? error yes pi pe ac tiv ated enab l e the pi pe. pe n x = 1 test if the pi pe configuration is correct. upcfgx intfrq pepnum ptype ptoken psize pbk alloc confi gure the pipe: - i nterrupt request frequency; - endpo i nt number; - type ; - token ; - size; - number of banks. allo cate the configured dpram banks. no 32058k avr32-01/12 525 at32uc3a interrupt (hwupi). if the non -id le bus st ate corresponds to an upst ream resume (k state) , the upstream resume received int errupt (rxrsmi) is raised . the firmware has to generate a downstre am resume within 1 ms an d for at least 20 ms by setting th e resume bit. it is manda- tory to set sofe before set t ing resume to enter t he ready stat e, else resume will have no effect. 30.7.3 .9 ma nag emen t of cont rol pip es a c ontrol transaction is c ompos ed of thre e stages: ?setup; ?dat a ( in or out); ?statu s (ou t o r in ). t he fi rmware ha s t o change th e pipe token accordin g t o each stag e. fo r th e contro l pipe, an d on ly fo r it, each toke n is assigned a specific in itial da ta toggle sequence: ?setup: data0; ?in: data1; ?out: data1. 30.7.3.10 management o f in pipes in packets are sent by the usb device contr oller upon in reques ts from t he host. all th e data c an be rea d b y the fi rmwar e whic h ackn owle d ges o r not the b an k wh en it is empty. th e pipe must b e configure d first. when the hos t requir es da ta fro m the device , the firmware has to se lect beforehand th e in requ est mode wit h the inmode bit: ?w hen inmode is cleared, the usb controller w ill perfor m (inr q + 1) in request s be for e freezing th e pipe; ?w hen in mode is set, the usb controller will perfor m in requests endlessly wh en the pipe is not frozen by th e firmware. th e generatio n of in requests starts when t he pipe is unfrozen (pfr eeze = 0). the rxini bi t is se t by h ardware at th e same time as fifocon whe n the cur rent b ank is full. this triggers a pxint interrupt if r xine = 1. rxini sha ll be cleared by s oftware (b y setti ng th e rxinic bit) to acknowled ge th e interrupt, what has no effect on th e pip e fifo. the firmware then read s from the fifo a nd clears th e fifo con bi t to free the bank . if the in pipe is co mposed of multiple banks , this also switches to the ne xt bank. t he rxini and fifo- con bi ts ar e update d by hardware in acco rdance with the status o f th e next bank. rxini shall always be cleared befor e cl e ari ng fifoc on. th e rwall bi t is set by hardware when t he current b ank is not empty, i.e. th e softwa re can read furthe r data fro m th e fifo. 32058k avr32-01/12 526 at32uc3a figur e 30-25. exampl e of an in pipe wit h 1 data bank figur e 30-26. exampl e of an in pipe wit h 2 data banks 30.7.3.11 management o f ou t pipes out packets a r e sent by the host. all the data c a n be writ ten b y t he fir m ware wh ic h a ck nowl- edge s o r no t th e b ank whe n it is f ul l. th e pipe must b e configure d an d unfrozen first. the txouti bi t is set by hardware at th e sa me tim e as fifoco n when th e current bank is free. this triggers a pxint interrupt if txoute = 1. txouti sha ll be cleared by software (b y setting th e txouti c bit) to acknowledge th e interrupt, what ha s n o effect on th e pi pe fifo. the firmware the n writ es into t he fi fo an d clears t he fifocon bit t o allow t he usb controller to send the d ata . if the out pipe is com posed of multiple b anks, th is also switches to th e next ba nk. the txout i an d fif oco n bits ar e up date d by hardware in acc ord ance with th e status of the ne xt bank. txouti shall alwa ys be cleare d befor e clearing fifocon. th e rwall bit is set by hardware when th e cu rrent ban k is no t fu ll, i.e. the software can write furthe r data into the fifo. not e tha t if th e fi r mwar e d ec ide s t o s witc h to th e s uspen d stat e (b y c lear ing the sof e bit ) wh ile a bank is r eady to be sent, t he usb con trolle r automati cally exits th is state and the b ank is sent. in data (bank 0) ack rxini fifocon hw in data (ba nk 0) ack hw sw sw sw read da ta from cpu bank 0 rea d data from cpu ban k 0 in data (b ank 0) ack rxini fifocon hw in data (bank 1) ack sw sw r ead data from cpu ban k 0 hw sw r ead data from cpu ban k 1 32058k avr32-01/12 527 at32uc3a figur e 30-27. exampl e of an out pip e wit h 1 data bank figur e 30-28. exampl e of an out pip e wit h 2 data banks an d n o bank switchi n g delay figur e 30-29. exampl e of an out pip e wit h 2 data banks an d a ba nk switching delay 30.7.3.1 2 crc error this er r or exists only f or isochronous in pipes. it raises t he crc er ror interrupt (crcerri), what trigger s a pxi nt in terrupt if crcerre = 1. a crc erro r ca n occur during in s tage if t h e usb controller detects a co rrupted received packet. th e in packet is stored in the b ank as if no crc erro r h ad occurred (rxini is raised). out data (bank 0) ack txouti fifocon hw write data to cpu ba n k 0 sw sw sw sw out wri t e dat a t o cpu bank 0 out data (bank 0) ack txouti fifocon wri t e dat a t o cpu ba n k 0 sw sw sw sw writ e da t a t o cpu ba n k 1 sw hw writ e da t a t o cpu bank0 out data (bank 1) ack out data (bank 0) ack txouti fifocon write data to cpu ban k 0 sw sw sw sw out data (bank 1) ack write data to cpu ba nk 1 sw hw write data to cpu bank0 32058k avr32-01/12 528 at32uc3a 30.7.3.13 interrupts see the structure of t he usb ho st interrupt syst em on figur e 30- 6 o n pa ge 504. th er e ar e two kinds o f host in ter rup ts : proc essing , i. e . thei r generatio n is part o f t he no rma l pr o- cessing, and exception, i.e. errors (not related to cpu exce ptions). 30.7.3.13.1 globa l interrupts th e processing host glo bal interrupts are: ?the d evice connectio n interr upt (dconni); ?the device disconnecti on interrupt (ddisci); ?the us b rese t sent interrupt (rsti); ?the d ownst ream resume sent interrup t (rsmedi); ?the upstream resume receiv ed interr upt (rxrsmi); ?the host s tart of fram e interrupt (hsofi); ?the host wake -up interrupt (hwupi); ?the pipe x inter r upt (pxint); ?the dma c hann el x interr upt (dmaxint). ther e is n o exception h ost global interrupt. 30.7.3.13.2 pip e interrupts th e p r ocessin g host pip e interru pts are: ?the recei v ed in data interrupt (rxini); ?the transmitted out data interrupt (txouti); ?the transmitted setu p interr upt (txstpi); ?the short packe t i nterrupt (shortpacketi); ?the number of bu sy ba nks interr upt (nbusybk). th e exceptio n host pi pe interrupts are: ?the underfl o w interr upt (underfi); ?the pipe error inter r upt (perri); ?the n ake d interr upt (nakedi); ?th e overflow interrup t (overfi ); ?the received stalle d interrupt (rxstalldi); ?th e crc erro r in terrupt (crcerr i). 30.7.3.13.3 dma interrupts th e proc e ssing ho st d ma i nte rrup ts ar e: ?the end of usb transfer stat us interrup t (eot_sta); ?th e end of channe l buffer status interrupt (eoch_buff_sta); ?the descriptor load ed status interrupt (desc_ld_sta). th er e is n o exception ho st dma in terr upt. 32058k avr32-01/12 529 at32uc3a 30.7.4 usb dma operation usb p ackets of any length m ay be transferred when r e quired by the usb controller. these transf ers always f eature sequent ial addressing. these tw o characteristics mea n that in case of high u s b controller throughput, both hs b ports will benefit from ?inc rementing burs t of unspeci- fi ed length? since th e averag e acce ss latenc y of hsb sl av es can th en b e reduced. th e dma uses word ?incrementin g burst of unspecif ied length? of up to 256 beats for bot h data transfers a nd channel descriptor loading. a b urst may l ast on the hsb busses for the durati on of a w h ole usb packe t transfer, un less othe rwise broken by t he hsb arbitration or the hsb 1 kbyte boundar y crossing. packet data hsb bursts may b e locked on a dma bu ffer basis for drastic overa ll hsb bu s band- widt h per formance boost with p aged memori es. th is is because t hese memories row ( or bank) changes, whic h are ve ry clock-cyc le consuming, wil l th e n l ik el y n o t occ ur or o ccur o nce i n stead of dozens of time s durin g a singl e bi g usb packet dma transfer in cas e other hsb m asters ad dress the memo ry. th is me ans up t o 1 28 word s single cycle u nbroken hsb b u rsts fo r bulk pipes/endpoints a nd 256 word s si ngle cycl e unbroke n bu rsts for isochronous pipes/endpoints. this maximal burst lengt h is then controlle d by the lowest programm ed usb pipe/endpoint size (psiz e/epsiz e) and d ma c hannel by te length (ch_byte_length). the usb con trolle r averag e throughput may be up to nearly 1. 5 mbyte/s. it s avera ge access lat ency decreas es as bu rst lengt h increases due t o th e 0 wait-stat e sid e effect of unchanged pipe/endpoint. word access allows reducing t he hsb bandwidth required for th e usb by 4 com- pared to na tiv e byt e access. if at least 0 w ait-stat e wor d burst capabilit y is a ls o p rovided by th e othe r dma hsb bu s slaves, each of both dma hsb bu sses ne ed less than 1.1% bandwidth allocation for fu ll usb bandwidth usag e at 33 mhz, a n d less than 0. 6% at 66 mhz. figur e 30-30. exam pl e o f dma ch aine d li st data buffer 1 data buffer 2 data buffer 3 memory area transfer descriptor next descriptor address hsb address control transfer descriptor transfer descriptor usb dma channel x registers (current transfer descriptor) next descriptor address hsb address control null status next descriptor address hsb address control next descriptor address hsb address control 32058k avr32-01/12 530 at32uc3a 30.8 u sb user interface tabl e 30-5. usb pb memory map offset register name access reset value 0x0000 device gene ral control register udcon read/write 0x00000100 0x0004 device glob al interrupt register udint read-only 0x00000000 0x0008 device glob al interrupt c lear register udintclr write-only 0x00000000 0x000c device glob al interrupt se t register udintset write-only 0x00000000 0x0010 device glob al interrupt enabl e register udinte read-only 0x00000000 0x0014 device glob al interrupt enabl e cl ear re gister udinteclr write-only 0x00000000 0x0018 device global int e rrupt enable set register udinteset write-only 0x00000000 0x001c endpoint enab le/reset register uerst read/write 0x00000000 0x0020 device frame numb er register udfnum read-only 0x00000000 0x002 4 - 0x00fc reserved ? ? ? 0x0100 endpoint 0 co nfiguration register uecfg0 read/write 0x00000000 0x0104 endpoint 1 co nfiguration register uecfg1 read/write 0x00000000 0x0108 endpoint 2 co nfiguration register uecfg2 read/write 0x00000000 0x010c endpoint 3 co nfiguration register uecfg3 read/write 0x00000000 0x0110 endpoint 4 co nfiguration register uecfg4 read/write 0x00000000 0x0114 endpoint 5 co nfiguration register uecfg5 read/write 0x00000000 0x0118 endpoint 6 co nfiguration register uecfg6 read/write 0x00000000 +0 x00 4 - 0x 0 12c res e rved ? ? ? 0x0130 endpoint 0 st atus register uesta0 read-only 0x00000100 0x0134 endpoint 1 st atus register uesta1 read-only 0x00000100 0x0138 endpoint 2 st atus register uesta2 read-only 0x00000100 0x013c endpoint 3 st atus register uesta3 read-only 0x00000100 0x0140 endpoint 4 st atus register uesta4 read-only 0x00000100 0x0144 endpoint 5 st atus register uesta5 read-only 0x00000100 0x0148 endpoint 6 st atus register uesta6 read-only 0x00000100 +0 x004 - 0x 015c res e rved ? ? ? 0x0160 endpoint 0 st atus cl ear register uesta0clr write-only 0x00000000 0x0164 endpoint 1 st atus cl ear register uesta1clr write-only 0x00000000 0x0168 endpoint 2 st atus cl ear register uesta2clr write-only 0x00000000 0x016c endpoint 3 st atus cl ear register uesta3clr write-only 0x00000000 0x0170 endpoint 4 st atus cl ear register uesta4clr write-only 0x00000000 0x0174 endpoint 5 st atus cl ear register uesta5clr write-only 0x00000000 0x0178 endpoint 6 st atus cl ear register uesta6clr write-only 0x00000000 +0 x04 - 0x01 8c reser ved ? ? ? 0x0190 endpoint 0 st atus set reg ister uesta0set write-only 0x00000000 32058k avr32-01/12 531 at32uc3a 0x0194 endpoint 1 st atus set reg ister uesta1set write-only 0x00000000 0x0198 endpoint 2 st atus set reg ister uesta2set write-only 0x00000000 0x01 9c en dpoint 3 st atus set register uesta3set write-only 0x00000000 0x01a0 endpoint 4 st atus set reg ister uesta4set write-only 0x00000000 0x01a4 endpoint 5 st atus set reg ister uesta5set write-only 0x00000000 0x01a8 endpoint 6 st atus set reg ister uesta6set write-only 0x00000000 +0x04 - 0 x01bc reserved ? ? ? 0x01c0 endpoint 0 co ntrol register uecon0 read-only 0x00000000 0x01c4 endpoint 1 co ntrol register uecon1 read-only 0x00000000 0x01c8 endpoint 2 co ntrol register uecon2 read-only 0x00000000 0x01cc endpoint 3 co ntrol register uecon3 read-only 0x00000000 0x01d0 endpoint 4 co ntrol register uecon4 read-only 0x00000000 0x01d4 endpoint 5 co ntrol register uecon5 read-only 0x00000000 0x01d8 endpoint 6 co ntrol register uecon6 read-only 0x00000000 +0x04 - 0 x01ec reserved ? ? ? 0x01f0 endpoint 0 co ntrol set reg ister uecon0set write-only 0x00000000 0x01f4 endpoint 1 co ntrol set reg ister uecon1set write-only 0x00000000 0x01f8 endpoint 2 co ntrol set reg ister uecon2set write-only 0x00000000 0x01fc endpoint 3 co ntrol set reg ister uecon3set write-only 0x00000000 0x0200 endpoint 4 co ntrol set reg ister uecon4set write-only 0x00000000 0x0204 endpoint 5 co ntrol set reg ister uecon5set write-only 0x00000000 0x0208 endpoint 6 co ntrol set reg ister uecon6set write-only 0x00000000 +0 x04 - 0x021c r ese rv ed ? ? ? 0x0220 endpoint 0 co ntrol cl ear register uecon0clr write-only 0x00000000 0x0224 endpoint 1 co ntrol cl ear register uecon1clr write-only 0x00000000 0x0228 endpoint 2 co ntrol cl ear register uecon2clr write-only 0x00000000 0x022c endpoint 3 co ntrol cl ear register uecon3clr write-only 0x00000000 0x0230 endpoint 4 co ntrol cl ear register uecon4clr write-only 0x00000000 0x0234 endpoint 5 co ntrol cl ear register uecon5clr write-only 0x00000000 0x0238 endpoint 6 co ntrol cl ear register uecon6clr write-only 0x00000000 +0 x04 - 0x030c r ese rv ed ? ? ? 0x0310 devic e dm a c h a nne l 1 n e x t des c ri pt or addres s register uddma1_ nextdesc read/write 0x00000000 0x0314 device dma ch anne l 1 hsb address register uddma1_ addr read/write 0x00000000 0x0 318 dev ice dm a ch annel 1 co ntrol regi ster uddma1_ control read/write 0x00000000 tabl e 30-5. usb pb memory map offset register name access reset value 32058k avr32-01/12 532 at32uc3a 0x031c device dm a channel 1 status reg ister uddma1_ status read/write 0x00000000 0x0320 d e v i c e d m a cha nne l 2 n e x t d es cri pto r addres s register uddma2_ nextdesc read/write 0x00000000 0x0324 device dma ch anne l 2 hsb address register uddma2_ addr read/write 0x00000000 0x0328 dev i ce dm a ch a nnel 2 co ntrol register uddma2_ control read/write 0x00000000 0x032c device dm a channel 2 status reg ister uddma2_ status read/write 0x00000000 0x0330 d e v i c e d m a cha nne l 3 n e x t d es cri pto r addres s register uddma3_ nextdesc read/write 0x00000000 0x0334 device dma ch anne l 3 hsb address register uddma3_ addr read/write 0x00000000 0x0338 dev i ce dm a ch a nnel 3 co ntrol register uddma3_ control read/write 0x00000000 0x033c device dm a channel 3 status reg ister uddma3_ status read/write 0x00000000 0x0340 d e v i c e d m a cha nne l 4 n e x t d es cri pto r addres s register uddma4_ nextdesc read/write 0x00000000 0x0344 device dma ch anne l 4 hsb address register uddma4_ addr read/write 0x00000000 0x0348 dev i ce dm a ch a nnel 4 co ntrol register uddma4_ control read/write 0x00000000 0x034c device dm a channel 4 status reg ister uddma4_ status read/write 0x00000000 0x0350 d e v i c e d m a ch an n e l 5 n e x t d es cri pto r addres s register uddma5_ nextdesc read/write 0x00000000 0x0354 device dma ch anne l 5 hsb address register uddma5_ addr read/write 0x00000000 0x0358 dev i ce dm a ch a nnel 5 co ntrol reg ist er uddma5_ control read/write 0x00000000 0x035c device dm a channel 5 status reg ister uddma5_ status read/write 0x00000000 0x0360 d e v i c e d m a ch an n e l 6 n e x t d es cri pto r addres s register uddma6_ nextdesc read/write 0x00000000 0x0364 device dma ch anne l 6 hsb address register uddma6_ addr read/write 0x00000000 0x0368 dev i ce dm a ch a nne l 6 co ntrol reg ist er uddma6_ control read/write 0x00000000 0x036c device dm a channel 6 status reg ister uddma6_ status read/write 0x00000000 0x037 0 - 0x03fc reserved ? ? ? tabl e 30-5. usb pb memory map offset register name access reset value 32058k avr32-01/12 533 at32uc3a 0x0400 host ge ne ral contro l register uhcon read/write 0x00000000 0x0404 host gl obal interrupt reg ister uhint read-only 0x00000000 0x0408 host gl obal interrupt cle ar register uhintclr write-only 0x00000000 0x040c host gl obal interrupt set r egister uhintset write-only 0x00000000 0x0410 host gl obal interrupt enab l e register uhinte read-only 0x00000000 0x0414 host gl obal interrupt enab l e clear register uhinteclr write-only 0x00000000 0x 0 418 h o st g l obal i n t e r r u p t en a b l e set register uhinteset write-only 0x00000000 0x0041c pipe enable/re set register uprst read/write 0x00000000 0x0420 host frame num b er register uhfnum read/write 0x00000000 0x0424 host address 1 reg ister uhaddr1 read/write 0x00000000 0x0428 host address 2 reg ister uhaddr2 read/write 0x00000000 +0 x04 - 0x 04fc rese rv ed ? ? ? 0x0500 pip e 0 configurati on register upcfg0 read/write 0x00000000 0x0504 pip e 1 configurati on register upcfg1 read/write 0x00000000 0x0508 pip e 2 configurati on register upcfg2 read/write 0x00000000 0x050c pip e 3 configurati on register upcfg3 read/write 0x00000000 0x0510 pip e 4 configurati on register upcfg4 read/write 0x00000000 0x0514 pip e 5 configurati on register upcfg5 read/write 0x00000000 0x0518 pip e 6 configurati on register upcfg6 read/write 0x00000000 +0 x04 - 0x05 2c reser ved ? ? ? 0x0530 pip e 0 status reg ister upsta0 read-only 0x00000000 0x0534 pip e 1 status reg ister upsta1 read-only 0x00000000 0x0538 pip e 2 status reg ister upsta2 read-only 0x00000000 0x053c pip e 3 status reg ister upsta3 read-only 0x00000000 0x0540 pip e 4 status reg ister upsta4 read-only 0x00000000 0x0544 pip e 5 status reg ister upsta5 read-only 0x00000000 0x0548 pip e 6 status reg ister upsta6 read-only 0x00000000 +0 x04 - 0x05 5c r eser v ed ? ? ? 0x 0 560 pip e 0 st atu s cl ear r e g i st er upsta 0 clr w r it e-on ly 0x00 0000 00 0x 0 564 pip e 1 st atu s cl ear r e g i st er upsta 1 clr w r it e-on ly 0x00 0000 00 0x 0 568 pip e 2 st atu s cl ear r e g i st er upsta 2 clr w r it e-on ly 0x00 0000 00 0 x0 5 6c pip e 3 st atu s clea r r e g i st er upsta 3 clr w r it e-on ly 0x00 0000 00 0x 0 570 pip e 4 st atu s cl ear r e g i st er upsta 4 clr w r it e-on ly 0x00 0000 00 0x 0 574 pip e 5 st atu s cl ear r e g i st er upsta 5 clr w r it e-on ly 0x00 0000 00 0x 0 578 pip e 6 st atu s cl ear r e g i st er upsta 6 clr w r it e-on ly 0x00 0000 00 +0 x04 - 0x05 8c r eser v ed ? ? ? tabl e 30-5. usb pb memory map offset register name access reset value 32058k avr32-01/12 534 at32uc3a 0x0590 pip e 0 status set r egister upsta0set write-only 0x00000000 0x0594 pip e 1 status set r egister upsta1set write-only 0x00000000 0x0598 pip e 2 status set r egister upsta2set write-only 0x00000000 0x059c pip e 3 status set r egister upsta3set write-only 0x00000000 0x05a0 pip e 4 status set r egister upsta4set write-only 0x00000000 0x05a4 pip e 5 status set r egister upsta5set write-only 0x00000000 0x05a8 pip e 6 status set r egister upsta6set write-only 0x00000000 +0x04 - 0 x05bc reserved ? ? ? 0x05c0 pip e 0 co ntrol register upcon0 read-only 0x00000000 0x05c4 pip e 1 co ntrol register upcon1 read-only 0x00000000 0x05c8 pip e 2 co ntrol register upcon2 read-only 0x00000000 0x05cc pip e 3 co ntrol register upcon3 read-only 0x00000000 0x05d0 pip e 4 co ntrol register upcon4 read-only 0x00000000 0x05d4 pip e 5 co ntrol register upcon5 read-only 0x00000000 0x05d8 pip e 6 co ntrol register upcon6 read-only 0x00000000 +0x04 - 0 x05ec reserved ? ? ? 0x05f0 pip e 0 co ntrol set register upcon0set write-only 0x00000000 0x05f4 pip e 1 co ntrol set register upcon1set write-only 0x00000000 0x05f8 pip e 2 co ntrol set register upcon2set write-only 0x00000000 0x 05fc p ip e 3 contro l se t r eg i st er u p c on3 set w r it e-on ly 0 x00 0000 00 0x0600 pip e 4 co ntrol set register upcon4set write-only 0x00000000 0x0604 pip e 5 co ntrol set register upcon5set write-only 0x00000000 0x0608 pip e 6 co ntrol set register upcon6set write-only 0x00000000 +0 x04 - 0x061c rese rv ed ? ? ? 0x0620 pip e 0 co ntrol clear register upcon0clr write-only 0x00000000 0x0624 pip e 1 co ntrol clear register upcon1clr write-only 0x00000000 0x0628 pip e 2 co ntrol clear register upcon2clr write-only 0x00000000 0x062c pip e 3 co ntrol clear register upcon3clr write-only 0x00000000 0x0630 pip e 4 co ntrol clear register upcon4clr write-only 0x00000000 0x0634 pip e 5 co ntrol clear register upcon5clr write-only 0x00000000 0x0638 pip e 6 co ntrol clear register upcon6clr write-only 0x00000000 +0 x04 - 0x064c rese rv ed ? ? ? 0x0650 pip e 0 in req u est register upinrq0 read/write 0x00000000 0x0654 pip e 1 in req u est register upinrq1 read/write 0x00000000 0x0658 pip e 2 in req u est register upinrq2 read/write 0x00000000 0x065c pip e 3 in req u est register upinrq3 read/write 0x00000000 tabl e 30-5. usb pb memory map offset register name access reset value 32058k avr32-01/12 535 at32uc3a 0x0660 pip e 4 in req u est register upinrq4 read/write 0x00000000 0x0664 pip e 5 in req u est register upinrq5 read/write 0x00000000 0x0668 pip e 6 in req u est register upinrq6 read/write 0x00000000 0x0 66c - 0x067c reserved ? ? ? 0x0680 pip e 0 error re gister uperr0 read/write 0x00000000 0x0684 pip e 1 error re gister uperr1 read/write 0x00000000 0x0688 pip e 2 error re gister uperr2 read/write 0x00000000 0x068c pip e 3 error re gister uperr3 read/write 0x00000000 0x0690 pip e 4 error re gister uperr4 read/write 0x00000000 0x0694 pip e 5 error re gister uperr5 read/write 0x00000000 0x0698 pip e 6 error re gister uperr6 read/write 0x00000000 +0 x04 - 0x070c rese rv ed ? ? ? 0x0710 host dma chann el 1 ne xt descriptor address register uhdma1_ nextdesc read/write 0x00000000 0x0714 host dma c hanne l 1 hsb addre ss register uhdma1_ addr read/write 0x00000000 0x0718 host dma c hanne l 1 control register uhdma1_ control read/write 0x00000000 0x071c host dma c hanne l 1 status register uhdma1_ status read/write 0x00000000 0x0720 host dma chann el 2 ne xt descriptor address register uhdma2_ nextdesc read/write 0x00000000 0x0724 host dma c hanne l 2 hsb addre ss register uhdma2_ addr read/write 0x00000000 0x0728 host dma c hanne l 2 control register uhdma2_ control read/write 0x00000000 0x072c host dma c hanne l 2 status register uhdma2_ status read/write 0x00000000 0x0730 host dma chann el 3 ne xt descriptor address register uhdma3_ nextdesc read/write 0x00000000 0x0734 host dma c hanne l 3 hsb addre ss register uhdma3_ addr read/write 0x00000000 0x0738 host dma c hanne l 3 control register uhdma3_ control read/write 0x00000000 0x073c host dma c hanne l 3statu s register uhdma3_ status read/write 0x00000000 0x0740 host dma chann el 4 ne xt descriptor address register uhdma4_ nextdesc read/write 0x00000000 0x0744 host dma c hanne l 4 hsb addre ss register uhdma4_ addr read/write 0x00000000 tabl e 30-5. usb pb memory map offset register name access reset value 32058k avr32-01/12 536 at32uc3a 0x0748 host dma c hanne l 4 control register uhdma4_ control read/write 0x00000000 0x074c host dma c hanne l 4 status register uhdma4_ status read/write 0x00000000 0x0750 host dma chann el 5 ne xt descriptor address register uhdma5_ nextdesc read/write 0x00000000 0x0754 host dma c hanne l 5 hsb addre ss register uhdma5_ addr read/write 0x00000000 0x0758 host dma c hanne l 5 control register uhdma5_ control read/write 0x00000000 0x075c host dma c hanne l 5 status register uhdma5_ status read/write 0x00000000 0x0760 host dma chann el 6 ne xt descriptor address register uhdma6_ nextdesc read/write 0x00000000 0x0764 host dma c hanne l 6 hsb addre ss register uhdma6_ addr read/write 0x00000000 0x0768 host dma c hanne l 6 control register uhdma6_ control read/write 0x00000000 0x076c host dma c hanne l 6 status register uhdma6_ status read/write 0x00000000 0x077 0 - 0x07fc reserved ? ? ? 0x0800 general c ontrol register usbcon read/write 0x03004000 0x0804 genera l status register usbsta read-only 0x00000400 0x0808 genera l status clear register usbstaclr write-only 0x00000000 0x080c general status set r egister usbstaset write-only 0x00000000 0x0810-0x0814 reserved ? ? ? 0x0818 ip versi o n register uvers read-only 0x00000311 0x081c ip features re gister ufeatures read-only 0x00012467 0x0820 ip pb address size reg ister uaddrsize read-only 0x00001000 0x0824 ip n ame re gister 1 uname1 read-only 0x48555342 (? husb?) 0x0828 ip n ame re gister 2 uname2 read-only 0x004f5447 (?\0otg?) 0x082c usb fi n ite state machin e stat us register usbfsm read-only 0x00000009 0x0830 - 0x0bfc reserved ? ? ? tabl e 30-5. usb pb memory map offset register name access reset value 32058k avr32-01/12 537 at32uc3a in the followin g subsections , th e bit and bit-fi eld access ty pes use the following flags: ??r?: r eadable; ??w?: w ritable; ??u?: ma y be updated by hardware. tabl e 30-6. usb hsb memory map offset register name access reset value 0x00 000 - 0x0fffc pip e /e ndpoi nt 0 fif o d a ta r e gister usb_ fifo0_data read/write undefined 0x10 000 - 0x1fffc pip e /e ndpoi nt 1 fif o d a ta r e gis t er usb_ fifo1_data read/write undefined 0x20 000 - 0x2fffc pip e /e ndpoi nt 2 fif o d a ta r e gis t er usb_ fifo2_data read/write undefined 0x30 000 - 0x3fffc pip e /e ndpoi nt 3 fif o d a ta r e gis t er usb_ fifo3_data read/write undefined 0x40 000 - 0x4fffc pip e /e ndpoi nt 4 fif o d a ta r e gis t er usb_ fifo4_data read/write undefined 0x50 000 - 0x5fffc pip e /e ndpoi nt 5 fif o d a ta r e gis t er usb_ fifo5_data read/write undefined 0x60 000 - 0x6fffc pip e /e ndpoi nt 6 fif o d a ta r e gis t er usb_ fifo6_data read/write undefined +0x000 04 - 0xffffc reserved ? ? ? 32058k avr32-01/12 538 at32uc3a 30.8.1 us b ge neral registers 30.8.1.1 usb genera l contro l registe r (usbcon) offset: 0x0800 regis te r nam e: usbcon acces s type: read/write reset value: 0x03004000 ? idte: id transition interrupt enable set to enable th e id transition interrup t (idti). clear to disable th e id transit ion interrupt (idti). ? vbu ste: vbus transiti on interrupt enable set to enable the vbus t ransition interrup t (vbusti). clear t o disable the vb us transition interrup t (vbusti). ? srpe: sr p interrupt enable set to enable the srp i nterrupt (srpi). clear t o disable the sr p interrupt (srpi). ? vberr e: vbus erro r interrupt enable set to enable the vbus er ror interrupt (vberri). cl ear to di sab l e th e v b us error int errup t (vber ri ). ? bc e rre: b-c o nnect ion erro r interr upt enable set t o en a ble the b-conn ectio n error inter rup t (bcerri). clear to disable th e b-connection erro r interrupt (bcerri). ? roleexe: ro le exchange interrupt ena ble set to enable the role e xchange interrupt (roleexi). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? uimod uide rw rw 1 1 23 22 21 20 19 18 17 16 ? unlock timpage ? ? timvalue rw rw rw 0 0 0 0 0 15 14 13 12 11 10 9 8 usbe frzclk vbuspo otgpade hnpreq srpreq srpsel vbushwc rw rw rw rw rwu rwu rw rw 0 1 0 0 0 0 0 0 7 6 5 4 3 2 1 0 stoe hnperre roleexe bcerre vberre srpe vbuste idte rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 32058k avr32-01/12 539 at32uc3a cl ear to di sab l e th e role exchange interrupt (roleexi). ? hnp erre: hn p erro r interrupt enable set to enable th e hnp error interrupt (hnperri). clear to disable th e hnp error interrup t (hnperri). ? sto e: suspen d time -out interru pt enable set to enable the suspend time-out interrupt (stoi). clear t o disa ble th e s uspend ti me-ou t int errup t (stoi ). ? vbushwc : vbus hardware control set t o disabl e th e h ardware con tr ol ov e r th e u sb_ vb o f output p i n. clear t o enabl e th e hardware contro l over th e usb_vbo f output pin. if cleared , then t he usb ma cro consider s vbus problems and resets the usb_vbof output pin in that event. ? srps el: sr p selection set to ch oose vbus pulsing as srp me thod. clear to choos e data lin e pulsing as srp method. ? s rpr eq: sr p requ est set to initiate an srp when the controller is in device mode. cleare d by hardware when th e co ntroller is initiating an srp. ? hnpreq: hnp request whe n th e controller is in devic e mode: set to in itiate an hnp. cleared by hardware when the co ntroll er is initiating an hnp. when the controller i s in ho st mode: set t o accept a n hnp. clear otherwise. ? otgpade: otg pa d enable set to enable the ot g pad. clear t o disable the ot g pad. note that this bit can be s e t/cleared even if u sbe = 0 or frzclk = 1. disabli ng the us b controller (by clearing the usbe bi t) does not rese t this bit. ? vb uspo: vbus polarity when 0 , th e usb_vbo f outpu t sign al is in its defaul t mode (active high). when 1 , th e usb_vbo f outpu t sign al is inverte d (active low). t o be gener ic. ma y b e usef ul to control an extern al vbus power module. note that this bit can be s e t/cleared even if u sbe = 0 or frzclk = 1. disabli ng the us b controller (by clearing the usbe bi t) does not rese t this bit. 32058k avr32-01/12 540 at32uc3a ? f rzclk: freez e usb clock set to d i sable the clock inputs (the res um e d et ect io n i s stil l a cti ve). th is r ed uce s power consumption. unless explicitly stated, all registers the n become read-only. clear to enable the clock inp uts. note that this bit can be s e t/cleared even if u sbe = 0 or frzclk = 1. disabli ng the us b controller (by clearing the usbe bi t) does not rese t this bi t, but this freezes the clock inputs whatever its value. ? us be: us b macr o enable set to enable the usb c ontroller. clear to disable an d rese t t he usb controller, to disa ble th e usb transceiver an d to disabl e th e usb controlle r clock inputs. unle ss explicit ly stated, all register s the n becom e read- only an d ar e reset. not e t hat th is b it can be set/c lea red even if u sbe = 0 or frzclk = 1. ? timva lue: timer value set to initialize t he ne w valu e o f th e special time r register select ed by timpage. ? t i m pa ge : time r pa ge write th e page value to access a sp ecial timer register. ? unlock: timer access unlo ck set to unloc k th e ti mpage an d timvalue fields before writing them. reset to lock t he ti mpage an d timvalue fields. note that th e ti mpage an d timvalue fields ca n alwa ys b e read, whatever the va lue of unlock. ? uid e: usb_id pin ena ble set to select th e usb mode (device/host) from th e usb_ id input pin. clea r t o s ele ct th e usb m ode (device /h ost) wi th the uim o d bit. note that this bit can be s e t/cleared even if u sbe = 0 or frzclk = 1. disabli ng the us b controller (by clearing the usbe bi t) does not rese t this bit. ? u imod: usb m acr o mode th is bi t ha s no effect when ui de = 1 (usb_id input pin activated). set to select th e usb devic e mode. clear to select th e usb ho st mode. note that this bit can be s e t/cleared even if u sbe = 0 or frzclk = 1. disabli ng the us b controller (by clearing the usbe bi t) does not rese t this bit. 32058k avr32-01/12 541 at32uc3a 30.8.1.2 usb gene ra l status re gister (usbsta) offset: 0x0804 regis te r nam e: usbsta acces s type: read-only reset value: 0x00000400 ? idti: id transition interrupt flag asynchrono us interrupt. set by hardwa re when a transitio n (high t o low, low t o high) h as be en detect ed on the usb_ id inp ut pin. this triggers a usb interrupt if idte = 1. shall be cleare d by softwar e (by setting the idtic bi t) to acknowledge the interr upt (usb clock in puts must be enabled before). note that th is interrup t is generate d even if t he clock is froze n by the frzclk bit. ? vbu sti: vbus transi tion inte rrupt flag asynchrono us interrupt. set by h ardware when a transition (high to low, low t o high) ha s bee n detected on th e vbus pad. this trigger s a usb inter- rupt if vbuste = 1. shall be cleared b y software (b y setting the vbustic bit) to acknowledge th e interrupt (u sb clo ck inputs must be enabled before). note that th is interrup t is generate d even if t he clock is froze n by the frzclk bit. ? s rpi: srp inte rrupt flag shal l only be us e d i n hos t mode. set by hardwar e whe n an srp h as bee n detected. this triggers a usb i nterrup t if srpe = 1. shall b e clear e d by software ( by setting t h e sr pic b it) t o a ckno wledg e th e i nterrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? speed vbus id vb usrq ? ru ru ru ru 0 0 0 1 0 7 6 5 4 3 2 1 0 sto i hnperr i ro leex i bcerr i v berri srp i vb usti idti ru ru ru ru ru ru ru ru 0 0 0 0 0 0 0 0 32058k avr32-01/12 542 at32uc3a ? v berri: vbus erro r interrupt flag in host mode, set by hardware when a vbus drop has been detected. this t r iggers a us b interrupt if vber re = 1. shall be cleare d by softwar e (b y settin g th e vberri c bit) to acknowledge th e interrupt. note that if a vbus problem occurs, then the vbe rri in ter rup t is ge nerated even if the usb macro does not go to an error stat e becau se of vbushwc = 1. ? bcerri: b-conn ectio n error interru pt flag in host mode, set by hardwar e when a n error occu rs during t he b-connection. th is triggers a usb i nterrupt if bcerre = 1. shall be cleare d by softwar e (b y settin g th e bcerric bit) to acknowledge the interrupt. ? roleex i: role exchange inte rrupt flag set by hardware when the usb controller h as successfully switched its mode because of an hnp negotiation (hos t to device or device to h o st). this triggers a usb interrupt if ro leexe = 1. shall be cleared by soft ware (by setting the roleexic bit) to ackno w ledge the interrupt. ? hnperri: hn p erro r interrupt flag in device mode , se t by hardware when an error ha s been detect ed during an hnp n egotiation. this triggers a usb in terrupt if hnpe rre = 1. shall be cleare d by softwar e (b y settin g th e hnperri c bit) to acknowledge the interrupt. ? stoi: suspend t ime-out interrupt flag in ho st mode , se t by ha rdwar e wh en a ti me-out erro r (mor e than 200m s) has b ee n dete ct ed afte r a susp end . th is trig gers a usb i nterrup t if st oe = 1. shall b e cleare d by software ( by settin g t he s toic b it) to ackno wledg e th e i nterrupt. ? vbu srq: vbus request in h o st mode , set by softwar e (b y setting th e vbusrqs bi t) to asser t th e usb_vbof outpu t pin in orde r to enable the vbus p owe r supp ly generatio n. cleare d b y software b y setting th e vbusrqc bit. cleare d b y hardware when a vbu s erro r occurs when vbushwc = 0. ? id: usb_id pi n state set/cleared by hard wa re and re flects the state of the usb_id input p i n, even if usbe = 0. ? vbu s: vbus le vel set/c lear e d by hardware and re flect s the leve l of th e vbu s line , e ve n if usb e = 0. th is bi t can be used in device mode to monitor th e usb bu s connecti on stat e o f th e application. ? speed: sp eed status set by hardwar e according to the controlle r spe ed mode: shal l only be us e d i n hos t mode. speed speed s tatus 0 0 ful l -speed mode 1 0 low-speed mode x 1 reserved 32058k avr32-01/12 543 at32uc3a 30.8.1.3 usb gene ra l status c lear register (usbstaclr) offset: 0x0808 regis te r nam e: usbstaclr acces s type: write-only rea d value: 0x00000000 ? i dtic: id tr ansitio n interr u pt fla g cl e ar set to clea r idti. clea rin g has n o e ffect. alway s r e ad as 0. ? vbustic: vbus transition interrup t flag clear set to clear vbusti. clea rin g has n o e ffect. alway s r e ad as 0. ? srpic: srp interrupt fl ag clear set to clear srpi. clea rin g has n o e ffect. alway s r e ad as 0. ? vberric : vbus erro r interrupt flag clear set to clear vber ri. clea rin g has n o e ffect. alway s r e ad as 0. ? bcerric: b-conn ection erro r interrupt flag clear set to clear bce rri. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? vbusrqc ? w 0 7 6 5 4 3 2 1 0 stoic hnperric roleexic bcerric vberric srpic vbustic idtic w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 544 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? roleexic: role ex change in terrupt flag clear set to clea r r oleex i. clea rin g has n o e ffect. alway s r e ad as 0. ? hnp erric: hnp erro r interrupt flag clear set to c lear hnp erri. clea rin g has n o e ffect. alway s r e ad as 0. ? sto ic: susp end time-out inter rupt flag clear set to clea r stoi. clea rin g has n o e ffect. alway s r e ad as 0. ? vbu srqc: vbus request clear set to clear vbus rq. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 545 at32uc3a 30.8.1.4 usb gene ra l status se t register (usbstaset) offset: 0x080c regis te r nam e: usbstaset acces s type: write-only rea d value: 0x00000000 ? i dtis: id tr an sitio n inter r upt fl a g set set to set idti, what may be useful for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? vbu stis: vbus transi tion inter rupt flag set set to se t vbusti, what may be useful for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? srpis: srp in terrupt flag set set to se t srpi, what may b e useful for test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? vberr is: vb us erro r interrupt flag set set to set vbe r ri, what may be useful for test or debug purposes . clea rin g has n o e ffect. alway s r e ad as 0. ? bcerris: b-conn ectio n erro r interru pt flag set set t o se t bcerri , what may b e usef ul fo r te st or debu g pur poses. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? vbusrqs ? w 0 7 6 5 4 3 2 1 0 stois hnperris roleexis bcerris vberris srpis vbustis idtis w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 546 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? roleex is: role exchange inte rrupt flag set set to set rol eexi, what may be useful for te st o r debug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? hnperris: h np erro r interrupt flag set set to se t hnperri, what may be useful for test o r deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? sto is: suspend time-out inte rrupt flag set set to se t stoi, what may b e useful for test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? vbu srqs: vbus request set set to set vb usrq. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 547 at32uc3a 30.8.1 .5 usb ip version register (uvers) offset: 0x0818 regis te r nam e: uve rs acces s type: read-only rea d value: 0x00000260 ? version_num: ip version number this fi eld indicat es the version num b er of the usb mac ro ip, encod ed with 1 vers ion digit per nibble, e. g. 0x0 260 for ver- sion 2.6.0. ? metal_fix_num: number of metal f ixes this field indicate s th e number of metal fixes of t he usb macro ip. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? metal_fix_num r 0 0 0 15 14 13 12 11 10 9 8 version_num r 0 2 7 6 5 4 3 2 1 0 version_num r 6 0 32058k avr32-01/12 548 at32uc3a 30.8.1.6 usb ip featur es registe r (ufeatures) offset: 0x081c regis te r nam e: ufeatures acces s type: read-only rea d value: 0x00012467 ? ept_nbr_max: maximal n u mber of pipes/endpoints this field indicate s th e number of hardware-implemente d pipes/endpoints: ? d ma_channel_nbr: nu mber of dma channels this field indicate s th e number of hardware-implemente d dma channels: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 byte_write _dpram fifo_max_size dma_fifo_word_depth r r r 0 0 1 0 0 1 0 0 7 6 5 4 3 2 1 0 dma_buffer _size dma_channel_nbr ept_nbr_max r r r 0 1 1 0 0 1 1 1 ept_nbr_max maxima l numbe r of pipes/endpoints 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 ... 1 1 1 1 15 dma_channel_nbr number of dma ch annels 0 0 0 reserved 0 0 1 1 0 1 0 2 ... 1 1 1 7 32058k avr32-01/12 549 at32uc3a ? d ma_buffer_size: dma buffer size this field indicate s th e siz e of the dma b uffer: ? dma_fifo_word_depth: dma f ifo de pth in words this field indicate s t h e dma fi fo depth contro ller in words: ? f ifo_max_size: maximal fifo size this field indicate s t h e maxima l fifo s ize, i.e. the dpram size: ? byt e_w rite_dpram : d p ra m byte-write capability this field indicate s whethe r th e dpram is byte-write capable: dma_buffer_size d ma buff er size 0 16 bits 1 24 bits dma_fifo_word_depth dma fifo depth in words 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 ... 1 1 1 1 15 fifo_max_size maxima l fifo size 0 0 0 < 256 bytes 0 0 1 < 512 bytes 0 1 0 < 1024 bytes 0 1 1 < 2048 bytes 1 0 0 < 4096 bytes 1 0 1 < 8192 bytes 1 1 0 < 16384 bytes 1 1 1 > = 16 38 4 b y t es byte_write_dpram dpra m byte -write capability 0 dpram by te wr ite lanes have shadow logi c implemented in the us b macro ip interface. 1 d pram is natively byte-wri te capable. 32058k avr32-01/12 550 at32uc3a 30.8.1 .7 usb ip pb addres s size register (uaddrsize) offset: 0x0820 regis te r nam e: uaddrsize acces s type: read-only rea d value: 0x00001000 ? u addr size : i p pb ad dr ess size this field indicate s th e size o f the pb a ddre ss space reserved fo r th e usb macr o ip interface ( 2 a t t he power o f the number of bits r eserve d t o en cod e the pb addre ss es of th e us b m acr o i p interface relative ly to its bas e a dd ress). 31 30 29 28 27 26 25 24 uaddrsize r 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 uaddrsize r 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 uaddrsize r 0 0 0 1 0 0 0 0 7 6 5 4 3 2 1 0 uaddrsize r 0 0 0 0 0 0 0 0 32058k avr32-01/12 551 at32uc3a 30.8.1 .8 usb ip name register 1 (uname1) offset: 0x0824 regis te r nam e: u name1 acces s type: read-only rea d value: 0x48 555342 (? husb ?) ? un ame 1: ip name pa r t 1 this field indicate s the 1 st p art of th e ascii-encode d na me of th e usb macro ip. 31 30 29 28 27 26 25 24 uname1 r ?h? 23 22 21 20 19 18 17 16 uname1 r ?u? 15 14 13 12 11 10 9 8 uname1 r ?s? 7 6 5 4 3 2 1 0 uname1 r ?b? 32058k avr32-01/12 552 at32uc3a 30.8.1 .9 usb ip name register 2 (uname2) offset: 0x0828 regis te r nam e: u name2 acces s type: read-only rea d value: 0x004f544 7 (?\0otg?) ? un ame 2: ip name pa r t 2 this field indicate s the 2 nd part of th e ascii-encod ed na me of t he usb macro ip. 31 30 29 28 27 26 25 24 uname2 r ?\0? 23 22 21 20 19 18 17 16 uname2 r ?o? 15 14 13 12 11 10 9 8 uname2 r ?t? 7 6 5 4 3 2 1 0 uname2 r ?g? 32058k avr32-01/12 553 at32uc3a 30.8.1.10 usb finite stat e machine status register (usbfsm) offset: 0x082c regis te r nam e: usbfsm acces s type: read-only rea d value: 0x00000009 ? drdstate this fiel d indicates the stat e of th e usb controller. refe r to th e otg specificatio n for mor e details. 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 - - - - - - - - 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - drdstate r 0 0 0 0 1 0 0 1 usbfsm description 0 a_idle state : this is th e star t stat e fo r a-d e vices ( w hen the id pi n is 0) 1 a_wait_vri se : in this state, the a-device waits fo r the voltage on vbus to ri se abov e th e a- de vice vbus val id threshol d (4.4 v). 2 a_wait_bcon : i n this st ate, th e a-device waits fo r the b-de vice to signal a connection. 3 a_ host : i n this st at e , th e a-d ev i ce th a t oper ates in h o st mode is ope ra tio nal. 4 a_suspen d : th e a-devic e o perating as a host is in the suspend mode. 5 a_peri pheral : the a-de vice opera tes as a peripheral. 6 a_wait_vfal l : in this stat e, th e a-device waits fo r the volta ge on vbus t o drop belo w the a- de vice session val id threshol d (1.4 v). 7 a_ vbus_ e r r : i n t h is state , the a - d e vice wa its fo r rec o ve ry of t he ov ercurrent conditi on that caused it to enter t h is state. 8 a_wait_discha rge : in th is state, the a-device waits fo r th e data usb lin e to discha rge (100 u s). 9 b_idle : t his is the sta r t state fo r b-device (wh en th e id pi n is 1). 10 b_peri pheral : in th is state, the b-de vice acts as the p eripheral. 32058k avr32-01/12 554 at32uc3a 11 b_ wait_ b e g in_h n p : i n thi s st a t e, t h e b-de vi c e i s i n s u s pe n d mo d e a nd wa it s unt il 3 ms be f or e in i t i ating th e h np p r ot oco l if r e qu es t e d. 12 b_wait_discha rge : in th is state, the b-device waits fo r th e data usb lin e to discha rge (100 us) be for e becomin g host. 13 b_wait_acon : i n this st ate, th e b-device waits fo r the a-de vice to signal a connect before beco ming b-host. 14 b_ host : in this st ate, th e b-device ac ts as th e host. 15 b_srp_i nit : in this state, the b-d e vice attemp ts to start a session using the srp protoco l. usbfsm description 32058k avr32-01/12 555 at32uc3a 30.8.2 usb d evice registers 30.8.2.1 usb d e vice general co ntrol register (udcon) offset: 0x0000 regis te r nam e: udcon acces s type: read/write reset value: 0x00000100 ? uadd: usb address set to configure the devic e address. cleared by hardware upo n receiving a usb reset. ? add en: ad dress enable set to activate th e uadd fiel d (usb address). cleared by hardware upo n receiving a usb reset. clearin g by software has no effect. ? d eta ch: detach set to physically detach t he devic e (disconnect intern al pull-u p resistor from d+ a n d d-). clear to reconnect th e device. ? rm wku p: remote w ake-up set to se nd an upstre am resume to t he host fo r a remote wake-up. cleared by hardware upo n receiving a usb reset o r once t he upstream resume ha s be en sent. clearin g by software has no effect. ? l s : low-spe e d m o de force set to force t he low-spee d mode. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ls ? ? rmwkup detach rw rwu rw 0 0 1 7 6 5 4 3 2 1 0 adden uadd rwu rwu 0 0 0 0 0 0 0 0 32058k avr32-01/12 556 at32uc3a clear t o unfor ce th e low-speed mode. then, the full-spee d mod e is active. note that this bit can be s e t/cleared even if u sbe = 0 or frzclk = 1. disabli ng the us b controller (by clearing the usbe bi t) does not rese t this bit. 32058k avr32-01/12 557 at32uc3a 30.8.2 .2 usb device global interrupt register (udint) offset: 0x0004 regis te r nam e: udint acces s type: read-only reset value: 0x00000000 ? s usp: suspe nd interrupt flag set by hardware when a usb ?suspend? idle bu s stat e has been detect ed fo r 3 fram e periods (j state fo r 3 ms). this t rig- ge rs a usb interrupt if suspe = 1. shall be cleare d by softwar e (b y settin g th e suspc bit) to acknowledge the interrupt. cl eared by h ar d ware w hen a wake-up interrup t (wakeu p) is raised. ? sof : star t of fr ame interrupt flag set by hardware when a usb ?start of frame? pi d (sof) ha s been detected (eve ry 1 ms). this trigge rs a usb interrupt if sofe = 1 . t he fnum fiel d is updated. shall be cleare d by softwar e (b y settin g th e sofc bit) to acknowledge the interrupt. ? eor s t: e n d of r e se t inter rupt fl ag set by hardwar e whe n a usb ?e nd of reset ? ha s bee n detected. this trigge rs a usb interrupt if eorste = 1. shall be cleare d by softwar e (b y settin g th e eorstc bit) t o acknowledge t he interrupt. ? wakeup: wake -up inte rrupt flag asynchrono us interrupt. set by hardwa re when th e usb controller is reactivate d by a filtered non-id le signal from th e lines (not by an upstream resume). this triggers a n interrupt if wakeu p e = 1. shall be cleare d by softwar e (b y setting the wakeupc bi t) t o acknowledge the interru pt (usb clo ck inputs must be enab led before). cleare d by hardware when a su spend interrup t (su sp) is raised. 31 30 29 28 27 26 25 24 dma6int dma5int dma4int dma3int dma2int dma1int ? ru ru ru ru ru ru 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ep6int ep5int ep4int ru ru ru 0 0 0 15 14 13 12 11 10 9 8 ep3int ep2int ep1int ep0int ? ? ? ? ru ru ru ru 0 0 0 0 7 6 5 4 3 2 1 0 ? uprsm eorsm wakeup eorst sof ? susp ru ru ru ru ru ru 0 0 0 0 0 0 32058k avr32-01/12 558 at32uc3a note that th is interrup t is generate d even if t he clock is froze n by the frzclk bit. ? e orsm: end of resu me interrupt flag set by hardwa re when t he usb controller detect s a valid ?en d of resume? sign al initiat ed by t he host. th is triggers a us b interrupt if eorsme = 1. shall be cleare d by softwar e (b y settin g th e eorsmc bit) t o acknowledge t he interrupt. ? u prsm: upstream resume interrupt fl ag se t by hardware when the u sb controller sends a resume signa l called ?upstream resume?. this triggers a usb interrup t if uprsme = 1. shall be cleared by software (by setting the uprsmc bit) to acknowledge the interrupt (usb clock inputs must be enabled before). ? epxint , x in [0..6]: endpoint x interru pt flag set by h ardwa re wh en an interru pt is triggere d by t he endp oint x (uest ax, ueco nx). this triggers a usb i nterrupt if epxinte = 1. cleare d by hardware when th e interrupt source is s erviced. ? dmax in t, x in [1. .6] : dm a channel x interrup t flag set by hardwar e whe n an interrupt is triggere d by the dma cha n nel x. this trigge rs a usb interrupt if dmaxi nte = 1. cleared by hardware when t he udd max_stat us i n terr upt source is cleared. 32058k avr32-01/12 559 at32uc3a 30.8.2.3 usb d e vice global interrup t clear registe r (udintclr) offset: 0x0008 regis te r nam e: udintclr acces s type: write-only rea d value: 0x00000000 ? s uspc: suspe nd inter rupt flag clear set to clear susp . clea rin g has n o e ffect. alway s r e ad as 0. ? sof c: start of fram e inter rupt flag clear set to clear sof . clea rin g has n o e ffect. alway s r e ad as 0. ? e orstc: end of re set inte rrupt flag clear set to clear eo rst. clea rin g has n o e ffect. alway s r e ad as 0. ? w ak eupc: wa ke-u p i n ter rup t flag c lear set to clear wake up. clea rin g has n o e ffect. alway s r e ad as 0. ? e orsmc: end of r esume interr upt flag clear set to clear eo rsm. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? uprsmc eorsmc wakeupc eorstc sofc ? suspc w w w w w w 0 0 0 0 0 0 32058k avr32-01/12 560 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? u prsmc: upstr eam resu me interrupt flag clear set to c lear uprsm. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 561 at32uc3a 30.8.2 .4 usb device global interrupt set register (udintset) offset: 0x000c regis te r nam e: udintset acces s type: write-only rea d value: 0x00000000 ? s usps: suspe nd inte rrupt fla g set set to se t susp, what may be useful for test o r deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? sof s: star t of fram e inte rrupt flag set set to se t sof, what may b e useful fo r te st o r deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? eorsts: end of reset interrupt fl ag set set to se t eorst, what may be useful for test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? wakeups: wa ke-up interrupt flag set set to se t wakeup, what may b e useful fo r test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? eorsms: end of resu me interrupt fl ag set set to se t eorsm, what may be useful for test or debu g purposes. 31 30 29 28 27 26 25 24 dm a 7int s dm a 5int s dma4 i n t s dma3 int s dma2 in t s dma1 i n t s ? w w w w w w 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? uprsms eorsms wakeups eorsts sofs ? susps w w w w w w 0 0 0 0 0 0 32058k avr32-01/12 562 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? u prsms: upst ream res ume interrupt fla g set set to se t uprsm, what may be useful for test o r deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? d maxints, x in [1 ..6]: dma ch ann e l x in te r rupt fla g set set to se t dmaxint, what may be useful for test o r deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 563 at32uc3a 30.8.2 .5 usb device global interrupt enab le registe r (udinte) offset: 0x0010 regis te r nam e: udinte acces s type: read-only reset value: 0x00000000 ? susp e: su s pe nd inte rrupt enable set by software (b y setting t he suspes bit) to enab le th e suspe nd interrupt (susp). clear by s oftware (b y setting t he suspec bit) to disable t he suspend interrup t (susp). ? sof e: star t of fra me inte rrupt enable set by software (by setting the sofes bi t) to enable the start of frame interrupt (sof). clear by s oftwar e (b y setting t he sofe c bi t) t o disable t he star t of frame interrup t (sof). ? eorste: end of reset interrupt ena ble set by softwar e (b y setting t he eorstes bit) t o enable the en d of rese t interrupt (eorst). clear by s oftware (b y setting t he eorstec bit) to disabl e th e end of reset interrupt (eorst). ? wakeupe: wa ke-up interrupt enable set by software (by setting the wake u pes bit) to enable the wake-up interrupt (wake up). clear by software (by setting the wake u pec bit) to disable the wake -up interrupt (wakeup). ? eorsme: end of resu me interrupt ena ble set by softwar e (b y setting t he eorsmes bit) t o enable the en d of resu me interrupt (eorsm). clear by s oftwa re (b y setting t he eorsmec bit) t o disa bl e th e end of resum e in ter rup t (eorsm). ? u prsme: upst ream res ume interrupt enable set by sof twar e (b y sett ing t he uprsme s bi t) t o ena b le t h e upstre am resu me interrupt (uprsm). clear by s oftware (b y setting t he uprsme c bit) to disable t he upstre am resume interrupt (uprsm). 31 30 29 28 27 26 25 24 dm a 6int e dm a 5int e dma4 i n t e dma3 int e dma2 in t e dma1 i n t e ? r r r r r r 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ep6inte ep5inte ep4inte r r r 0 0 0 15 14 13 12 11 10 9 8 ep3inte ep2inte ep1inte ep0inte ? ? ? ? r r r r 0 0 0 0 7 6 5 4 3 2 1 0 ? uprsme eorsme wakeupe eorste sofe ? suspe r r r r r r 0 0 0 0 0 0 32058k avr32-01/12 564 at32uc3a ? epxinte, x in [0..6]: e n dpoint x interrupt enable set by software (by setting t he epxintes bit) to enable the e ndpoint x interrupt (epxint). clear by software (by setting the epxi nt ec bit) to disable the endpoint x interrupt (epxint). ? d maxinte, x in [1..6]: dma channel x interrupt enable set by software (b y setting t he dmaxi ntes bit) to enab le th e dm a channe l x interrup t (dmaxint). clear by s oftwar e (b y setting t he dmaxint ec bit) t o disable t he dma chann el x interrupt (dmaxint). 32058k avr32-01/12 565 at32uc3a 30.8.2 .6 usb device global interrupt enab le clear regist er (udinteclr) offset: 0x0014 regis te r nam e: udint e clr acces s type: write-only rea d value: 0x00000000 ? suspec: suspen d interrupt enable clear set to clear susp e. clea rin g has n o e ffect. alway s r e ad as 0. ? sofec : star t of frame inte rrupt enable clear set to clear sofe . clea rin g has n o e ffect. alway s r e ad as 0. ? e orstec: end of reset interrupt enab le clear set to clear eo rste. clea rin g has n o e ffect. alway s r e ad as 0. ? wakeupec: wake-u p interrupt enab le clear set to clear wake upe. clea rin g has n o e ffect. alway s r e ad as 0. ? e orsmec: end of resume interru pt enable clear set to clear eo rsme. 31 30 29 28 27 26 25 24 ? dma6intec dma5intec dma4intec dma3intec dma2intec dma1intec ? w w w w w w 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? ? ep6intec ep5intec ep4intec w w w 0 0 0 15 14 13 12 11 10 9 8 ep3intec ep2intec ep1intec ep0intec ? ? ? ? w w w w 0 0 0 0 7 6 5 4 3 2 1 0 ? uprsmec eorsmec wakeupec eorstec sofec ? suspec w w w w w w 0 0 0 0 0 0 32058k avr32-01/12 566 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? u prsmec: upstre am resume interrupt enable clear set to c lear uprsme . clea rin g has n o e ffect. alway s r e ad as 0. ? epxintec, x in [0..6]: endpo i nt x interrupt enab le clear set to clear epxi nte. clea rin g has n o e ffect. alway s r e ad as 0. ? dmax i ntec, x in [1..6]: dma c ha nnel x interr upt enable clear set to clear dmaxi nte. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 567 at32uc3a 30.8.2.7 usb d e vice global interrup t enab le set register (udinteset) offset: 0x0018 regis te r nam e: udinteset acces s type: write-only rea d value: 0x00000000 ? susp es: suspend interrupt enab le set set to set su spe. clea rin g has n o e ffect. alway s r e ad as 0. ? sof e s : s tart o f fr am e interru p t e nabl e s et set to se t sofe. clea rin g has n o e ffect. alway s r e ad as 0. ? eorstes: end of reset inte rrupt enab le set set to se t eorste. clea rin g has n o e ffect. alway s r e ad as 0. ? wakeupes: wa ke-up interrupt enable set set to set wak eupe. clea rin g has n o e ffect. alway s r e ad as 0. ? eorsmes: end of resume interrupt enable set set to se t eorsme. 31 30 29 28 27 26 25 24 ? dma6intes dma5intes dma4intes dma3intes dma2intes dma1intes ? w w w w w w 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? ? ep6inte s ep5intes ep4intes w w w 0 0 0 15 14 13 12 11 10 9 8 ep3intes ep2intes ep1intes ep0intes ? ? ? ? w w w w 0 0 0 0 7 6 5 4 3 2 1 0 ? uprsmes eorsmes wakeupes eorstes sofes ? suspes w w w w w w 0 0 0 0 0 0 32058k avr32-01/12 568 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? u prsmes: upstr eam resu me interrupt enab le set set to se t uprsme. clea rin g has n o e ffect. alway s r e ad as 0. ? epxintes, x in [0..6]: endpo i nt x interrupt ena b le set set to set epxinte . clea rin g has n o e ffect. alway s r e ad as 0. ? dm a xintes, x in [1. . 6]: dm a channe l x interrupt enable set set to set dmaxinte . clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 569 at32uc3a 30.8.2.8 u sb de vice fr ame nu mber re g iste r (ud f nu m) offset: 0x0020 regis te r nam e: udfnum acces s type: read-only reset value: 0x00000000 ? fnum : fr ame number set by hardware. thes e bi ts are t he 11-bit fram e number information. t hey ar e provided in th e last received so f packet. cleared by hardware upo n receiving a usb reset. not e tha t fnum is u pdate d ev en i f a corr upted so f is received. ? fncerr : frame number crc error set by h ardware when a co rrupted fram e number is received. this bi t and the so f interrup t flag are updated at th e same time. cleared by hardware upo n receiving a usb reset. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 fncerr ? fnum ru ru 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 fnum ? ? ? ru 0 0 0 0 0 32058k avr32-01/12 570 at32uc3a 30.8.2.9 usb e ndpoin t enable/reset re giste r (uerst) offset: 0x001c regis te r nam e: uerst acces s type: read/write reset value: 0x00000000 ? epen x, x in [0..6]: endpoint x enable set t o enab le th e endp oint x. clea r to disable the en dpoint x, wh at forces the endpo int x st ate to inactive (n o answer to usb requests) and resets the endpoi n t x registe rs ( u ecf gx, ues t ax, ueconx) but not the endpoint conf iguration (alloc, epb k, epsize , epdir, eptype). ? eprst x, x in [0..6] : en dpoint x reset set by so ft ware to reset the endpoint x fi fo prior t o any other oper ation, upon hardware rese t or when a usb bus reset ha s been received. this resets t he endpoint x registers (uecfgx, uestax, ueconx) but no t the endpoint configuration (alloc, epb k, epsize, epdir, eptype). all the endpoin t mechanism (f if o cou nter, reception, transmission, etc.) is rese t apar t from the data toggle sequence fiel d (d tseq) which ca n be cleared by setting t he rstdt bit (b y setting th e rstdts bit). the endpoint configu r ation remains active and t h e endpoint is still enabled. t hen, clea r by so ftware to c omplete th e reset operatio n an d to start usin g th e f ifo. cleared by hardware upo n receiving a usb reset. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? eprst6 eprst5 eprst4 eprst3 eprst2 eprst1 eprst0 rwu rwu rwu rwu rwu rwu rwu 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? epen6 epen5 epen4 epen3 epen2 epen1 epen0 rw rw rw rw rw rw rw 0 0 0 0 0 0 0 32058k avr32-01/12 571 at32uc3a 30.8.2.10 u sb endpoint x co nfiguratio n registe r (uecfgx) offset: 0x0100 + x . 0x04 regis te r nam e: uecfgx , x in [0..6] acces s type: read/write reset value: 0x00000000 ? a lloc: e ndpoint memory allocate set to allocate th e endpoint memory. clear to free th e endpoint memory. cleared by hardware upo n receiving a usb reset (excep t for th e endpoint 0). note that after setti ng this bit , the user should ch eck th e cf g o k b i t to know w heth er the allo c a tio n of thi s endpoi nt is correct. ? epbk: e n dpoint banks set to select th e number of banks for th e endpoint: fo r contro l endpoints, a single-b ank endpoint (00b) shoul d be selected. cleared by hardware upo n receiving a usb reset (excep t for th e endpoint 0). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? eptype ? autosw epdir rwu rwu rwu 0 0 0 0 7 6 5 4 3 2 1 0 ? epsize epbk alloc ? rwu rwu rwu 0 0 0 0 0 0 epbk endpo int banks 0 0 1 (single-b ank endpoint) 0 1 2 (d ou ble -bank endpo int) 1 0 3 (triple-bank endpoint) 1 1 reserved 32058k avr32-01/12 572 at32uc3a ? epsize : endpo int size set to select the size o f ea ch endpoint bank: cleared by hardware upo n receiving a usb reset (excep t for th e endpoint 0). ? epdir: endpoint direction set to select th e endpoint direction: cleared by hardware upo n receiving a usb reset. ? autosw: automati c switch set t o au toma tica lly switch ba nk when it is ready . clear to disable th e automatic b ank switching. cleared by hardware upo n receiving a usb reset. ? eptype: endpoint type set to select th e endpoint type: cleared by hardware upo n receiving a usb reset. epsize endpoint si ze 0 0 0 8 bytes 0 0 1 16 bytes 0 1 0 32 bytes 0 1 1 64 bytes 1 0 0 1 28 b y tes 1 0 1 2 56 b y tes 1 1 0 5 12 b y tes 1 1 1 1024 bytes epdir endpoi nt direction 0 out 1 i n (not fo r control endpoints) eptype endpoint type 0 0 control 0 1 isochronous 1 0 bulk 1 1 interrupt 32058k avr32-01/12 573 at32uc3a 30.8.2.1 1 u sb endpoint x stat us register (uestax) offset: 0x0130 + x . 0x04 regis te r nam e: uestax, x in [0..6] acces s type: read-only reset value: 0x00000100 ? t xini : t rans mi tte d in d ata inte rru pt fl ag fo r contro l endpoints: set by har dwar e wh en th e current b ank is ready to accept a new in packet. this triggers an epxint inter r upt if txine = 1. shall b e cleare d by software ( by settin g th e txinic bit) t o acknowledge t he interrupt an d to send t he packet. fo r isochronous, bulk and interrupt in endpoints: set by hardware at the same t i me as fifocon when the cu rrent bank is free. this triggers an epxint interrupt if txine = 1. shall b e clear ed by softwar e (b y settin g th e txinic bit) t o acknowledge the interrupt, what has n o effect on the end- po int fifo. t h e softwar e t he n writes into the fifo an d c le ar s th e f ifoc on b i t t o a llo w t h e u sb con tro lle r t o sen d th e data . if the in endpoint is c ompos ed of multip le banks , this al so switch es t o th e next ban k. t h e txini an d fifoco n bi ts are update d by hardwar e in accordan ce with the stat us o f th e next bank. txin i shall alwa ys be cleare d befor e clearing fifocon. t hi s bi t is in activ e (cl eared ) f or isochronous, bu lk and interrupt out endpoints. ? rxo ut i : re ceiv e d ou t d ata int e rru pt fl ag fo r contro l endpoints: set by hardware when the c u rrent bank contains a bulk ou t packet (data or status st age). this triggers an epxint interrupt if rxoute = 1. 31 30 29 28 27 26 25 24 ? byct ru 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 byct ? cfgok ctrldir rwall ru ru ru ru 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 currbk nbusybk ? ? dtseq ru ru ru 0 0 0 0 0 1 7 6 5 4 3 2 1 0 short packet st alledi/ crc err i overfi nakini nakouti rxstpi/ under fi rxouti txini ru ru ru ru ru ru ru ru 0 0 0 0 0 0 0 0 32058k avr32-01/12 574 at32uc3a shall be cleare d by softwar e (b y settin g th e rxouti c bit) to acknowledge the interrupt and to free th e bank. fo r isochronous, bulk and interrup t out endpoints: set by ha r dware at the same ti me as fifocon when the curr ent bank is full. t his triggers an epxi nt interrupt if rxoute = 1. sha ll be cleared by so ftware (b y setting th e rxouti c bit) to acknowledge th e interrupt, what ha s no effect on the endpoint fifo. the sof tware t hen reads from t he fifo a nd clears t he fifo con bit t o fre e the bank. if the out end p oint is com- posed of multi p le ba nks, this also switches to the next b ank. the rxouti and fifo con bits are updated by hardware in accord ance wit h th e status of t he next bank. rxouti shall always be cleared befor e cleari ng fifocon. thi s bi t is in acti v e (cl eared ) f or is ochronous, bu lk and interrupt in endpoints. ? r xstpi: re ceived setup interrupt fl ag fo r contro l endpoints, set by hardware to signal that the current ban k contains a ne w va lid setup packet. this trigge rs an epxint interrupt if rxstpe = 1. shall be cleare d by softwar e (b y settin g th e rxstpic bit) to acknowledge the interrupt an d to free th e bank. this bi t is inactive (cleared ) fo r bu lk and interrup t in/o ut endpoints a nd it means underfi f o r isoch ronous in/out endpoints. ? underfi: und erflo w inte rrupt flag for isochronous in/o ut endpoints, se t by har dware when an u nderfl ow error oc curs. this trigge rs an epxint interrup t if underfe = 1. an un derflow can occur d uring in stage i f t he host attempts t o read from an empty bank. a z ero-lengt h packet is then auto- matica lly sent by th e usb controller. an unde rf low can a ls o oc cu r during out sta ge if th e host sends a packet while the b ank is already full. typically, the cpu is no t fa st enough. the packe t is lost. shall be cleare d by softwar e (b y settin g th e underfic bit) to acknowledge th e interrupt. th is bi t is inactiv e (cleared) fo r bulk a nd interrupt in/o ut endpoints a nd it mean s rxstp i for control endpoints. ? nakouti : nake d out interrupt flag set by hardware whe n a nak h andshak e has b een sent in resp onse to an out req uest fr om the host. this triggers an epxint interrupt if nakoute = 1. sh all be cleared by softwar e (by setting the nakoutic bit) t o acknowledg e th e interrupt. ? nakini: na ke d in inter rupt flag set by hardware when a nak h andsh ake has bee n sent in response to an in reques t from the host . this triggers an epx- int interrupt if naki ne = 1. shall be cleare d by softwar e (b y settin g th e naki nic bit) to acknowledge the interrupt. ? overfi : overflow inte rrupt flag set by hardware when an overflow error occurs. this tr iggers an e p x in t int er r up t i f ove rf e = 1. for all endpoint types, an overflow c an occur during out stage if the host attempts to write int o a bank that is too small for t he packet . th e packet is ack nowledge d and the received out data interrupt (rxouti) is ra ised as if no overfl ow had occurred. the bank i s filled with all the first b ytes of the pa ck et that fit in. 32058k avr32-01/12 575 at32uc3a shall be cleare d by softwar e (b y settin g th e overfi c bit) to acknowledge th e interrupt. ? sta lledi: stalle d interrupt flag set by hard war e t o sign a l th a t a s t al l ha nd shak e ha s b ee n sen t. t o do that, the software ha s to set the stallr q bit (by setting the stallrqs bit). this trigger s an epxint interru p t if stal lede = 1. shall be cleare d by softwar e (b y settin g th e stalledic bit) t o acknowledge t he interrupt. ? crcerri: c rc erro r interrupt flag se t by hardware to sign al tha t a cr c error has been detected in an isochr ono us out en dpo int. th e out packet is s tor ed in the bank as if no crc error had occurred. this tr iggers an epxi nt inte rrupt if crcerre = 1. shall be clea r e d by softwar e (b y s ett in g t h e crcerric bit) t o acknowledge t he interrupt. ? shortpacket: short pack et interru pt flag fo r non-control out endpoints, se t by hardwar e when a s hor t packet has bee n received. fo r non-control in endpoints, set by hardware wh en a short packet is transmitt ed up on endin g a dma transfer, th us signal- ing an end of isochronous frame or a bu lk or interrupt end of transfer, th is only i f the end of dma bu ffer output enab le bit (dmaend_en ) and the automatic switch bit (autosw) are set. this triggers an epxint int e rrupt if shortpac kete = 1. shall be cleare d by softwar e (b y settin g th e shortp acketc bit) to acknowledge the interrupt. ? d tseq: data togg le sequence set by hardware to indicate the pid o f the current bank: for in tran sf ers, it indicates the data toggle se quence that w ill be us ed for the next packet to be sent. this is not relative to th e current bank. fo r out transfers , th is value indicate s th e last data togg le sequenc e receive d on t he current bank. not e tha t by d ef ault dt seq = 01b, a s i f th e la st dat a tog g l e seq uenc e wa s da ta1, so th e next sen t o r expecte d dat a t o ggle sequence shoul d be data0. ? n busyb k: number of busy banks set by hardware to indicate th e numbe r of bu sy banks: for in endpoints, it ind i cates the number of banks filled by the user and ready for i n transf er. when all banks are free, thi s triggers an epxint int e rrupt if nbu sybke = 1. dtseq data togg le sequence 0 0 data0 0 1 data1 1 x reserved nbusybk n umber of busy banks 0 0 0 (a ll ban k s f r ee) 0 1 1 1 0 2 1 1 3 32058k avr32-01/12 576 at32uc3a for out en d p o ints, i t indicate s th e number of b anks fil led b y o ut t ransact i on s f r om the host. wh en all bank s are busy, this triggers an epxi nt interrupt if nbusy b ke = 1. note that when th e fifocon bi t is cleare d (b y setting t he fifoconc bit) to validate a n ew bank, this fiel d is updated 2 o r 3 clock cycles la te r to ca lculate the address of the nex t bank. an e px int interr up t is triggered if : - for in endpoint, nb usybke=1 and all the b a nks are free. - for out endpoint, nb u sybke=1 a nd a l l th e ban ks are busy. ? currbk: cu rrent bank fo r non-control endpoints, se t by hardware t o indicate th e curren t bank: note that this field may be update d 1 cloc k cycle after the rwal l bit changes, so the user should not poll this field as a n inte rr upt flag. ? rw a ll: re ad/writ e allo wed for in endpoint s, set by hardware when the current ban k is not full, i.e. th e software can write further dat a into the fifo. for ou t endpoint s, set by hardware when th e current bank is no t empty, i.e. the software ca n read further data f rom the fifo. never se t if stallrq = 1 or in case of error . cleare d by hardware otherwise. th is bi t shall not be used for control endpoints. ? c trldir: co nt ro l direc t ion set by hardwar e afte r a setup packe t to indicate the directio n of the following packet: ca n no t be se t or cleared by software. ? c fgok: config uratio n ok status th is bi t is updat ed when th e alloc bi t is set. set by h ardware if the endp oint x num ber of banks (epbk) a nd size (epsize) a re correct co mpared to the maximal all owed numbe r of ba nks an d size for this endpoint and to the maximal fifo size (i .e. the dp r am size). if this bit is cleared by hard wa re, th e user should reprogram the uecfgx regist er wit h c orre ct e pbk and e psize v alu es. ? byct : by t e cou nt set by th e hardware t o indicate th e byte count o f th e fifo. currbk curr ent bank 0 0 bank0 0 1 bank1 1 0 bank2 1 1 reserved ctrldir contr ol direction 0 out 1 in 32058k avr32-01/12 577 at32uc3a for in endpoints, incremented afte r each byte written by t he soft ware into t he endpoint and decremented af ter each byte sent to th e host. for out endpoints , incremented after each byte received from the host and decremented after each byte read by the soft- ware from th e endpoint. note that this field may be update d 1 cloc k cycle after the rwal l bit changes, so the user should not poll this field as a n inte rr upt flag. 32058k avr32-01/12 578 at32uc3a 30.8.2.12 us b endpoint x status clear regis te r ( uest axclr) offset: 0x0160 + x . 0x04 regis te r nam e: uestaxclr , x in [0..6] acces s type: write-only rea d value: 0x00000000 ? txinic: tr ansmitted in d ata inte rrupt flag clear set to clea r txini. clea rin g has n o e ffect. alway s r e ad as 0. ? rxoutic: re c e iv ed out data in ter rupt flag clear set to clear rxouti. clea rin g has n o e ffect. alway s r e ad as 0. ? r xstpic: received setu p int e rru pt fl a g clear set to clear rxstpi . clea rin g has n o e ffect. alway s r e ad as 0. ? underfic: u nderflo w interrupt flag clear set to clear un derfi. clea rin g has n o e ffect. alway s r e ad as 0. ? na kou tic: nak ed out i nte rrup t f la g clear set to clear nakouti. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 short packetc stalledic/ crcerric o verfic n ak ini c n a k outi c rxstpic/ u nderf ic rxoutic txinic w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 579 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? nak inic: nak ed in interrupt flag clear set to clear nakini . clea rin g has n o e ffect. alway s r e ad as 0. ? overf ic: over flow in ter rup t flag clear set to clea r overfi. clea rin g has n o e ffect. alway s r e ad as 0. ? sta lledic: stal led interru pt flag clear set to clear stalledi . clea rin g has n o e ffect. alway s r e ad as 0. ? crc erric: crc erro r interrupt flag clear set to c lear crcerri. clea rin g has n o e ffect. alway s r e ad as 0. ? sho rtpa cketc: sho rt pa ck et interr u pt fl a g clear set to clear shortpack et. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 580 at32uc3a 30.8.2.13 us b endpoint x sta t us set regis ter (uest axset) offset: 0x0190 + x . 0x04 regis te r nam e: uestaxse t, x in [0..6] acces s type: write-only rea d value: 0x00000000 ? t xini s: trans mit te d i n data in terrupt flag set set to se t txini, what may b e useful for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? r xoutis: received ou t data inte rrupt flag set set to se t rxouti , what may b e usef ul for t est or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? r xstpis: re ceived setu p interrupt flag set set to se t rxstpi, what may be useful for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? underfis: unde rflo w inter rupt flag set set to se t underfi, what ma y b e usef ul for t est or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? nakou tis: nak ed out interrupt flag set set to se t nakouti, what may b e useful fo r te st or debug purposes. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? nbusybks ? ? ? w 0 7 6 5 4 3 2 1 0 short packets stalled i s/ crcerr is o verfis n akinis nako utis rxstpis/ underfis rxo utis t xin is w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 581 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? nakinis: naked in interrupt flag set set to se t nakini , what may b e useful for t est or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? over fis: overflow inte rrupt flag set set to se t overfi , what ma y be usef ul for test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? sta lledis: st alle d inter r upt fl a g set set to se t stalledi, wha t may b e useful fo r test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? crc erris: crc erro r interrupt flag set set to se t crcerri, what may b e useful for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? shortpa ckets: short pack et interr upt flag set set to se t shortpacket, what may be useful for test or deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? n busyb ks: number of busy banks interr u pt fl a g set set to force the number o f busy banks interrupt flag ( n busybk), what may be useful for test or debug pu r poses. set again to unforce the number o f busy banks interrupt flag ( nbusybk). clearin g ha s n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 582 at32uc3a 30.8.2.14 u sb en dpoin t x co ntro l registe r (ueconx) offset: 0x01c0 + x . 0x04 regis te r nam e: ueconx , x in [0..6] acces s type: read-only reset value: 0x00000000 ? txine: transmitte d in data interrupt enable set by softwar e (by setting the txines bi t) to enable the transmitte d in da ta interrupt (txini). clea r by softwar e (by setting the txinec bi t) t o disable the transmitte d in data interrupt (txini). ? r xoute: received out da ta interrupt enable set by softwar e (by setting the rxoutes bit) t o enabl e th e received out data interrup t (rxout). clea r by softwar e (by setting the rxou tec bit) to disabl e the received ou t data interrupt (rxout). ? rx stpe: receiv e d setu p i nte rru pt ena ble set by softwar e (by setting the rxstpes bit) to e nable the received setup i nterrup t (rxstpi). clea r by softwar e (by setting the rxstpec bi t) to disable th e received setu p interrupt (rxstpi). ? und erfe: underflow interrupt enable set by softwar e (by settin g th e und e rf es b it ) t o e nab l e th e und erflo w i n terrupt (underfi ). cl ear by softwa r e (by sett ing t he underfe c bit) to disable th e underf low interrupt (underfi). ? nak oute : nake d out inte rrupt enable set by softwar e (by setting the nako utes bit) to enable th e nake d ou t interrupt (nakouti). clea r by softwar e (by setting the nako utec bit) to disabl e th e nake d out interrupt (nakouti). ? nakine: naked i n interrupt enable set by softwar e (by settin g th e na kines bit ) to enabl e th e naked in interrupt (na kini). clear by software (by setting the naki nec bit) to disabl e the naked in interrup t (nakini). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? stallrq rstdt ? epdishdma ru ru r 0 0 0 15 14 13 12 11 10 9 8 ? fifocon killbk nbusybke ? ? ? ? ru ru r 0 0 0 7 6 5 4 3 2 1 0 short packete stallede/ crc err e overfe nakine nakoute rxstpe/ under fe rxoute txine r r r r r r r r 0 0 0 0 0 0 0 0 32058k avr32-01/12 583 at32uc3a ? overfe: overflow interrupt enable set by softwar e (by setting the overfes bit) t o enabl e the overflow interrupt (overfi). clear by s oftwar e (b y setting th e ove rf e c bit) to disabl e the overflo w interrup t (ov erfi). ? sta llede: st alle d i nte r rupt e na ble set by softwar e (by settin g th e stall ed es b it ) to e nabl e th e sta lle d interr up t (stalle di). clear by s oftware (b y setting t he stal ledec bit) to disable t he stalled interrup t (stalledi). ? crcerre: crc erro r interrupt enable set by so ftware (by setting the cr cerres bit) to enable the c r c erro r interrupt ( crcerri). clear by s oftware (b y setting t he crcerrec bit) to disable t he crc error interrupt (crcerri). ? shortpa ckete: short pack et interr upt enable set by softwar e (by setting the shortpacketes bi t) t o enable the shor t packet interrupt (shortpacket). clear by s oftwa re (b y setting t he shortpacke te c bi t) to disable t he short packet interrupt (shortpacket). ? n busyb ke: number of busy banks interrup t enable set by software (by setting the nbu sybkes bit) to enable the number of busy banks interrupt ( nbusybk). clear by software (by setting the n bus ybkec bit) to disable the number of busy banks i n terrupt (nb usybk). ? killb k: kill in bank set by software (by set t ing the killbks bit) to k ill the last written bank. cl eare d by h ar d ware w hen the bank is killed. caut ion: the bank is really cleared when t he ?kill packet? procedure is accepted b y the usb macro core. th is bit is auto- matica lly cleare d afte r th e en d of th e procedure: ? t he bank is really cleare d or the bank is se nt (in tr ansf er): nb usybk is decremented. ? t he bank is not cleared bu t sent (in transf er): nbu sybk is decremented. ? the ba nk is not cleare d because it wa s empty. the so ftware shall wait for this bit to be cleared before tr ying to kill anot her packet. note that this kill request is r efuse d if at the same time an in token i s comi ng and the last bank is t h e current one being sent on the usb line. if at lea s t 2 banks are ready to be sent, there is no p r oblem to kill a pack et even if an in token is coming . indeed, in this case , the curr ent bank is se nt (in transfer) wh ile the last bank is killed. ? f ifocon: fifo control fo r contro l endpoints: the f ifocon and rwall bits a re irrelevant. th e software shal l the refore never use the m on these endpoints. whe n rea d, th eir v alue is alw a ys 0. for in endpoints: set by hardwar e when th e current bank is free, at the same time as txini. clea r by softwar e (b y setting t he fifoco nc bit) t o send th e fi fo dat a and t o switch t o th e next bank. fo r out endpoints: set by hardwar e when th e current ba nk is fu ll, at th e same tim e as rxouti. 32058k avr32-01/12 584 at32uc3a clear by s oftwar e (b y setting t he fifoco nc bi t) to fre e th e curren t ba nk and to switch to t he ne xt bank. ? epdishdma: endp o int inte rrupts disabl e hdma reque st enable set by software (b y setting th e epdishdmas bit) to pause t he on-going dma cha nne l x transfer on any e ndpoint x i nter- rupt (epxi nt), wh atever the stat e of th e e ndpo i nt x interrupt enable bit (epxinte). th e software the n has to acknowledg e or to disabl e th e interrupt source (e.g. rxouti ) or to clear t he epdishdma bit (by setting the epdishdm ac bit) i n order to complete th e dm a transfer. i n pi ng-p o ng mod e, if th e in ter rup t is ass o ciat ed to a ne w system-b ank packet (e.g. ban k 1) an d th e curr en t dma t ransfer is running on th e previo us packe t (bank0 ), then the previous-packet dm a trans fer complete s norm ally, bu t th e new-packet dma tran sfer w ill not st art (not reques ted). if th e interrup t is not associated to a ne w system-ban k packet (nakini, nakouti, etc.), th en the request cancellation may occu r at an y time and ma y immediatel y paus e th e current dm a transfer. this may be u sed fo r exampl e to identify erroneou s packet s, t o preven t them from bein g transferre d into a buffer , to com- plet e a dma transfe r by software after recept ion of a short packet , etc. ? r stdt : rese t data toggle set by softwar e (by setting the rstdts bit ) to clea r the data toggle sequence , i.e. to se t t o data 0 the data toggle sequence of t he n ext sent (in endpoints ) or rec e ived (o ut en dpo in ts) packe t. cleared by hardware instantaneously. th e s oftwar e does not have to wai t fo r t his bit t o be clear ed. ? sta llrq: st all r e que st set by softwar e (b y setting t he stallr qs bit) t o request to se nd a stal l handshake to th e host. cleare d by hardware when a n ew setu p pack et is received. ca n also be cleared by softwar e by setting the stallrqc bit. 32058k avr32-01/12 585 at32uc3a 30.8.2.15 u sb endpoint x co ntro l clear register (ueconxclr) offset: 0x0220 + x . 0x04 regis te r nam e: ueconxclr, x in [0..6] acces s type: write-only rea d value: 0x00000000 ? txinec: transmit ted in da ta interrupt enab le clear set to clea r txine. clea rin g has n o e ffect. alway s r e ad as 0. ? r xoutec: received ou t dat a interrupt enab le clear set to clear rxoute. clea rin g has n o e ffect. alway s r e ad as 0. ? r xstpec: re ceived setu p interrupt enab le clear set to clear rxstpe . clea rin g has n o e ffect. alway s r e ad as 0. ? underfec: unde rflo w inte rrupt enab le clear set to clear un derfe. clea rin g has n o e ffect. alway s r e ad as 0. ? nakoutec: nak ed out interrupt enab le clear set to clear nakoute. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? stallrqc ? ? epdishdmac w w 0 0 15 14 13 12 11 10 9 8 ? fifoconc ? nbusybkec ? ? ? ? w w 0 0 7 6 5 4 3 2 1 0 short packetec stalledec/ crcerrec overfec nakinec nakoutec rxstpec/ underfec rxoutec txinec w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 586 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? na ki nec: n ak e d in inte rru pt e na bl e cl ear set to clear nakine . clea rin g has n o e ffect. alway s r e ad as 0. ? overfe c: overflow interrupt ena ble clear set to clea r overfe. clea rin g has n o e ffect. alway s r e ad as 0. ? sta lledec: stalled interr upt enable clear set to clear stalled e. clea rin g has n o e ffect. alway s r e ad as 0. ? crcerrec: crc er ro r interrupt enab le clear set to c lear crcerre. clea rin g has n o e ffect. alway s r e ad as 0. ? shortpa cketec: short pack et interrupt enab le clear set to clear shortpack ete. clea rin g has n o e ffect. alway s r e ad as 0. ? nb u sy b kec: num b er o f bu sy b a nks interrupt enab le clear set to clear nbu sybke. clea rin g has n o e ffect. alway s r e ad as 0. ? fifocon c: fifo contro l clear set t o clear fifocon. clea rin g has n o e ffect. alway s r e ad as 0. ? epd ishdm a c : endpoi nt i nte rrupt s di sab l e hd m a r e que st enable c lear set to clear epdishdma . clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 587 at32uc3a ? stallrqc : stal l request clear set to clear stallrq . clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 588 at32uc3a 30.8.2.16 usb endpoint x contr o l set register (ueconxset) offset: 0x 01 f 0 + x . 0x04 regis te r nam e: ueconx set, x in [0..6] acces s type: write-only rea d value: 0x00000000 ? txines: transmit ted in da ta interrupt enab le set set to set txine. clea rin g has n o e ffect. alway s r e ad as 0. ? r xoutes: received o u t da ta interrupt enab le set set to se t rxoute. clea rin g has n o e ffect. alway s r e ad as 0. ? r xstpes: re ceived setup interrupt enable set set to se t rxstpe. clea rin g has n o e ffect. alway s r e ad as 0. ? underfes: underflow interrupt enab le set set to se t underfe. clea rin g has n o e ffect. alway s r e ad as 0. ? nakoute s: nake d out inter rupt enab le set set to se t nakoute. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? stallrqs rstdts ? epdishdmas w w 0 0 15 14 13 12 11 10 9 8 ? ? killbks nbusybkes ? ? ? ? w w 0 0 7 6 5 4 3 2 1 0 short packetes stalledes/ crcerres o ver f e s n a kines na k oute s rxstpes/ underfes rxo u tes txin es w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 589 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? nakines: naked in inte rrupt enab le set set to se t nakine. clea rin g has n o e ffect. alway s r e ad as 0. ? overfe s: overflow interrupt ena b le set set to se t overfe. clea rin g has n o e ffect. alway s r e ad as 0. ? stal ledes : stalle d int e r rupt enabl e s et set to set stalle de. clea rin g has n o e ffect. alway s r e ad as 0. ? cr cerres: c rc erro r interrupt enable set se t t o se t c r cerre. clea rin g has n o e ffect. alway s r e ad as 0. ? shortpa cketes: short pack et interrupt enab le set set to set shortpa ckete. clea rin g has n o e ffect. alway s r e ad as 0. ? n busyb kes: number of busy banks interrup t ena b le set set to set nb usybke. clea rin g has n o e ffect. alway s r e ad as 0. ? killb ks: kill in bank set set to set killbk . clea rin g has n o e ffect. alway s r e ad as 0. ? epdishdmas: endpoint i nter rupts disabl e hdma reque st enable set set to set ep dishdma. clea rin g has n o e ffect. 32058k avr32-01/12 590 at32uc3a alway s r e ad as 0. ? r stdts: reset data toggl e set set to se t rstdt. clea rin g has n o e ffect. alway s r e ad as 0. ? sta llrqs: stal l request set set to set stall rq. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 591 at32uc3a 30.8.2.17 usb d e vice dma channel x next descr iptor address regist er (uddmax_nextdesc) offset: 0x0310 + (x - 1 ) . 0x10 regis te r nam e: uddmax_nextdesc , x in [1..6] acces s type: read/write reset value: 0x00000000 ? n xt_desc_ad dr: ne xt descriptor address this field contai ns th e bits 31:4 of th e 16-byte aligne d addres s o f the next channe l descriptor to b e processed. note th a t t his fi e ld is writt en e i the r b y softwa r e or b y descriptor loadin g. 31 30 29 28 27 26 25 24 nxt_desc_addr rwu 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 nxt_desc_addr rwu 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 nxt_desc_addr rwu 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 nxt_desc_addr ? ? ? ? rwu 0 0 0 0 32058k avr32-01/12 592 at32uc3a 30.8.2.18 u sb device dm a channel x hsb ad dress regist er (uddmax_addr) offset: 0x0314 + (x - 1 ) . 0x10 regis te r nam e: uddmax_addr, x i n [1..6] acces s type: read/write reset value: 0x00000000 ? h sb_ad dr: hsb address this fiel d determines the hsb bu s current addr ess of a channel transfer. the add ress set on t he hsb addr ess bu s is hsb_addr rounde d down to t he nearest word-align ed addres s, i.e. hsb_addr[1:0] is considered as 00 b sinc e on ly wor d ac cesses ar e performed. channe l hs b sta rt an d en d a ddre ss e s m a y b e align e d o n an y byt e bounda ry. t he s oft war e ma y w ri te this fi el d o nl y w he n the c hanne l en able d bit (ch_e n) of th e uddma x _s tatu s register i s clea r. this field is u pdate d at t he en d of th e addre ss pha se of th e current a ccess to th e hsb bu s. it is incremente d o f the hsb access b yte-width. the hsb access wi dth is 4 by te s, or less at packet start or end if th e start o r end ad dress is not aligned on a w ord boundary. the packet start addr es s is either the channel start a ddres s or t he nex t c hann e l add re s s to b e a c cess ed i n t he channel buffer. th e packe t en d add re ss is either th e ch ann e l en d a ddr es s o r t h e la te st chan nel add r ess acce ssed in th e chan nel buffe r. th e chan nel st art addr ess is w ritte n by s oftwa re or lo ad ed from th e desc ripto r , wh ere as the ch ann el e n d ad dre ss is either determine d by the end of buff er or the end of usb tr ansf er i f t he bu ff er close i nput enab le bit (buff_close_in_en) is set. 31 30 29 28 27 26 25 24 hsb_addr rwu 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 hsb_addr rwu 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 hsb_addr rwu 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 hsb_addr rwu 0 0 0 0 0 0 0 0 32058k avr32-01/12 593 at32uc3a 30.8.2.19 u sb device dm a channel x control regi st er (uddmax_control) offset: 0x0318 + (x - 1 ) . 0x10 regis te r nam e: uddmax_control , x in [1..6] acces s type: read/write reset value: 0x00000000 ? ch_en: ch annel ena ble set this bit t o enable t his channel dat a transfer. clear th is bi t to disab l e the cha n ne l da t a transfe r. th is may b e used t o start or resum e a ny requested transfer. th is bi t is cleare d by hardwar e when th e hsb sour ce chann el is disable d at en d of dm a buffer. ? ld_nxt_ ch_desc_en: loa d next channe l desc riptor enable set this bit to allo w automati c next descripto r loadin g at th e end of t he channel transfer. clear th is bit t o disable th is feature. if set, the dma channel controller l oads th e ne x t descripto r when the uddmax_status.c h_en bit is reset due to soft- war e of hardwar e event (fo r example at t he en d of th e current transfer). ? b uff_close_in_en: buff er close input enable set th is bit t o automatically closed the current dm a transfe r at th e end of the us b out data transfer (received shor t packet). clear th is bit t o disable th is feature. ? dmae nd_e n: end of dma buffer output enable set t his bi t to prop e rly co mplete th e usb tran sfe r at t h e e n d o f t h e dm a t r ans fer. for in end p oint, it means th at a sh ort packet (or a zero length packet ) will be se nt to th e usb line to prop erly closed the usb transfe r at the e nd of th e dma transfer. f or ou t end po int, it m eans th at all t he bank s wil l be p r op e rly released. (nbusybk= 0) at the end of the dma transfer. 31 30 29 28 27 26 25 24 ch_byte_length rwu 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ch_byte_length rwu 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 burst_lock _en desc_ld_ irq_en eobuff_ irq_en eot_irq_en dmaend_en buff_close _in_en ld_nxt_ch_ desc_en ch_en rwu rwu rwu rwu rwu rwu rwu rwu 0 0 0 0 0 0 0 0 32058k avr32-01/12 594 at32uc3a ? eot_i rq_e n: end of usb t rans fer inter r upt en ab le set th is bit t o enabl e the end of us b ou t data transfer interrupt. th is interrupt is generate d on ly i f the buff_close_ in_en bit is se t. clear this bit to disabl e this interrupt. ? eobuff_irq_e n: end of buffer inte rrupt enable set th is bit t o enabl e the end of buffer interrupt. th is interrupt is generate d when the chann el byt e count reache s zero. clear this bit to disabl e this interrupt. ? d esc_l d_irq_en: desc riptor loade d interrupt enable set this bit t o enable the descripor loaded interrupt. th is interrupt is generate d whe n a descriptor has been loaded from th e syst em bus. clear this bit to disabl e this interrupt. ? burst_lock_en: burs t loc k enable se t th is bit to loc k th e hsb data bur st for maximum optimizatio n of h sb busses bandwidth usage and maximization o f fly- by d uration. if clear, the dm a never locks h sb access. ? ch_byte_length: channel byte length this fiel d determines th e total numbe r of byte s t o be transferred for this buffer. th e maximu m channel transfer siz e 64 kb is r eached when this fiel d is 0 (default value). if th e transfe r size is u nknown, the transfe r end is c ontroll ed by t h e periphera l an d this fiel d shoul d b e se t t o 0. this field can be written by software or des c riptor loading onl y after the uddmax_status.c h_en bit has been cleared, otherwise this field i s ignored. 32058k avr32-01/12 595 at32uc3a 30.8.2.20 u sb de vice dma chann el x stat us registe r (uddmax_status) offset: 0x0 31c + (x - 1 ) . 0x10 regis te r nam e: uddmax_status , x in [1..6] acces s type: read/write reset value: 0x00000000 ? ch_en: ch annel enabled if se t, the dma cha nne l is curren tly enabled. if cleared , the dma cha nnel d oes no longer transfer data. ? ch_ac tive: channel active if se t, the dma cha nne l is curren tly trying to sour ce usb data. if cleared , the dma cha nne l is no longer trying to sour ce usb data. whe n a usb data transfe r is completed, th is bit is a utomatically reset. ? eot_sta: end of usb transfer status set by har dware when the completion of the usb da ta tran sfer has closed the d m a tran sfer. it is valid only if buff_close_en=1. th is bi t is automatica lly cleared when rea d by software. ? eoch_buff_sta: end of channe l buff er status set by hardwar e when th e channel byte count downcounts to zero. th is bi t is automatica lly cleared when rea d by software. ? d esc_ld_st a: desc riptor loa ded status set by hardwar e whe n a descriptor has bee n loaded from th e hsb bus. th is bi t is automatica lly cleared when rea d by software. 31 30 29 28 27 26 25 24 ch_byte_cnt ru 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ch_byte_cnt ru 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? desc_ld_ sta eoch_buff_ sta eot_sta ? ? ch_active ch_en ru ru ru rwu rwu 0 0 0 0 0 32058k avr32-01/12 596 at32uc3a ? ch_byte_cnt : channe l byte count this field gi ves the current number of b ytes still to be transfe r red for this buffer. this field is dec remente d at each dm a access. this field is reliable (stable) onl y if the c h_en flag is 0. 32058k avr32-01/12 597 at32uc3a 30.8.3 usb hos t registers 30.8.3 .1 usb ho st general control regi st er (uhcon) offset: 0x0400 regis te r nam e: uhcon acces s type: read/write reset value: 0x00000000 ? sof e: star t of fra me genera tion enable set t his bi t t o genera t e sof o n the u sb b u s i n ful l sp ee d mod e and k eep a liv e in lo w sp ee d mod e. clear this bit to disabl e th e sof generation and to leave t he usb bu s in id le state. t hi s bi t is set by ha rdware w he n a u sb rese t i s req ueste d or an upstrea m resume interrupt is detect ed (uhint.txrsmi). ? r eset: se nd usb reset set this bit to generat e a usb reset on the usb bus. cleare d by hardware when th e usb rese t ha s been sent. it may be useful to clea r t h is bit b y so ftware when a device disconnecti on is detect ed (uhi nt.ddisc i is se t ) whereas a usb reset is being sent. ? r esume : send usb resume set this bit to generat e a usb resume on the usb bus. clea red by hardwar e when t he usb resume ha s been sent or when a usb reset is requested . clearing by so ftwa re has no effec t. th is bit shou ld be set on ly when the start o f fram e generation is enable. (sof e bit set). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? resume reset sofe rwu rwu rwu 0 0 0 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? 32058k avr32-01/12 598 at32uc3a 30.8.3 .2 usb ho st glob al interrupt re giste r (uhint) offset: 0x0404 regis te r nam e: uhint acces s type: read-only reset value: 0x00000000 ? dconn i: de vice connec tion interrupt flag set by hardwar e whe n a new device h as been connecte d to th e usb bus. sh all be cleared by softwar e (by setting the dconnic bit). ? ddisci: d evice discon nection inte rrupt flag set by hardwar e when th e device ha s bee n removed from th e usb bus. shall be cleare d by softwar e (b y settin g th e ddis cic bit). ? r sti: usb res e t sent inter rupt flag set by hardwar e whe n a usb r eset has been sent to th e device. shall be cleare d by softwar e (b y settin g th e rsti c bit). ? r smedi : dow n str eam res u me sen t in ter rup t fl ag set by hardwar e whe n a downstream resu me ha s been sent to t he device. sh all be cleared by softwar e (by setting the rsme dic bit). ? r xrsmi: upstr eam resume receive d interrupt flag set by hardwar e whe n an upstream resume has been received from the device. sh all be cleare d b y softwar e (by settin g th e rxrsmi c bit ). ? h sofi: ho st star t of fr ame int e rru pt fl ag set by har dw are when a s o f is issue d by the ho st controller . this triggers a usb int errup t wh en hsofe is set. when usin g th e ho st controller in lo w spe ed mode , this bi t is also set when a kee p-alive is sent. shal l b e c leare d b y soft ware (b y s ett in g th e hsofi c bit ). 31 30 29 28 27 26 25 24 ? dma6int dma5int dma4int dma3int dma2int dma1int ? r r r r r r 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? p6int p5int p4int p3int p2int p1int p0int r r r r r r r 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 ? hwupi hsofi rxrsmi rsmedi rsti ddisci dconni r r r r r r r 0 0 0 0 0 0 0 32058k avr32-01/12 599 at32uc3a ? h wupi: host wake-up interr upt flag asynchrono us interrupt. set by ha rdwar e in the following cases : ? th e host controlle r is in th e suspen d mod e (sofe=0) an d an upstre am resume from the p eri phera l is detecte d. ? th e host controller is in t he suspen d mode (sofe=0) and a peripheral disconnection is detected. ? the host controlle r is in t he id le stat e (vbusrq=0, no vbu s is generated), and an otg srp even t initiated by the periphera l is detected. note that th is interrup t is generate d even if t he clock is froze n by the frzclk bit. ? p xi nt, x in [0 .. 6] : p ip e x in terru pt fl ag set by har dwar e whe n a n inter rupt is trigg ered by the endpoin t x (upstax). this trigge r s a usb interr upt if th e corre- sponding pipe interrupt enab le bit is set (uhint e re gister) . clea re d by ha r dwa r e whe n th e in terr up t sour ce is s e rved . ? dmax in t, x in [1. .6] : dm a channel x interrup t flag set by ha rdware wh en an interrup t is triggere d by th e dma chan nel x. th is trig gers a usb interrup t if the corresponding dmaxinte is set (uhinte register). cleared by hardware when t he uhd max_stat us i n terr upt source is cleared. 32058k avr32-01/12 600 at32uc3a 30.8.3 .3 usb ho st global interrupt clea r registe r (uhintclr) offset: 0x0408 regis te r nam e: uhintclr acces s type: write-only rea d value: 0x00000000 ? dcon n ic: de vice c on n ecti on inter rupt flag clear set to c lear dconni. clea rin g has n o e ffect. alway s r e ad as 0. ? ddiscic: d evice disconnectio n interrupt flag clear set to clea r ddisci. clea rin g has n o e ffect. alway s r e ad as 0. ? r stic: usb r e set sent interr upt flag clear set to clea r rsti. clea rin g has n o e ffect. alway s r e ad as 0. ? r smedic: d ownstream resume se nt interr u pt fla g cl ear set to c lear rsmedi. clea rin g has n o e ffect. alway s r e ad as 0. ? r xrsmic: upstre am resume receive d interrupt flag clear set to c lear rxrsmi. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? hwu pi c h s o fic rx r smic rs med ic r st ic dd isc ic dconnic w w w w w w w 0 0 0 0 0 0 0 32058k avr32-01/12 601 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? h sofic: hos t start of fram e interrupt flag clear set to clea r hs ofi. clea rin g has n o e ffect. alway s r e ad as 0. ? h wupic: host wake -up interru pt flag clear set to clea r hw upi. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 602 at32uc3a 30.8.3 .4 usb ho st global interrupt se t register (uhintset) offset: 0x040c regis te r nam e: uhintset acces s type: write-only rea d value: 0x00000000 ? dconnis: d evice conn ection inte rrupt flag set set to se t dconni, what may b e useful for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? ddiscis: d evice disconn ection inte rrupt flag set set to se t ddisci, what may be useful for test o r deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? r stis: usb re set sent interrupt fl ag set set to se t rsti , what may b e useful fo r te st or deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? r smedis: downstr eam resu me sent interru pt flag set set t o se t rsmedi, wha t ma y be useful fo r t e st or debu g purpos es. clea rin g has n o e ffect. alway s r e ad as 0. ? r xrsm is : up stre am resum e re ceive d inte rrup t fl a g s et set t o se t rxrsmi, wha t ma y be useful fo r t e st or debu g purpos es. 31 30 29 28 27 26 25 24 ? dma6ints dma5ints dma4ints d ma3ints d ma2int s d ma1int s ? w w w w w w 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? hwupis hsofis rxrsmis rsmedis rstis ddiscis dconnis w w w w w w w 0 0 0 0 0 0 0 32058k avr32-01/12 603 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? h sofis: host sta r t of fra me inte rrupt flag set set to se t hsofi, what may b e useful for test o r debug purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? hw upis: h ost wa ke -u p in terru pt fl ag set set to se t hwupi, what ma y b e usef ul for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? d maxints, x in [1 ..6]: dma ch ann e l x in te r rupt fla g set set to se t dmaxint, what may be useful for test o r deb ug purposes. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 604 at32uc3a 30.8.3.5 us b host globa l i nterru pt enab l e regi ster (uhint e) offset: 0x0410 regis te r nam e: uhinte acces s type: read-only reset value: 0x00000000 ? dconnie: d evice conn ection inte rrupt enable set by software (b y setting t he dconni es bit) to enable the device con necti on interrupt (dconni). clea r by softwar e (by setting the dconn iec bit) to disable th e device connection interrupt (dconni). ? ddiscie: d evice disconn ection inte rrupt enable set by softwar e (by setting the ddiscies bi t) to enab le th e device disconnecti on interrupt (ddisci). clear by s oftware (b y setting t he ddiscie c bit) to disable t he device disconnection interrup t (ddisci). ? r stie: usb re set sent interrupt enable set by softwar e (by setting the rsties bi t) to enable the usb rese t sent interrup t (rsti). clear by s oftware (b y setting t he rsti ec bit) to disable t he usb rese t sent interrupt (rsti). ? r smedie: downs tr eam resu me se n t in terr u pt ena ble set by software (by setting the rsmedies bit) t o enabl e the downstream resume interrupt (rsmedi). clea r by softwar e (by setting the rsmediec bit) t o disabl e th e downstre am re su me inte rr upt (rsmedi). ? r xrsm ie : up stre am resum e re ceive d inte rrup t enab le set by softwar e (by setting the rxrsmies bit) t o enable the upstream resume received i nterrupt (rxrsmi). clear by s oftwar e (b y se tting th e r xrsmie c bit) t o disa bl e th e downst rea m resum e interrupt (rxrs mi). ? h sofie: host sta r t of fra me inte rrupt enable set by softwar e (by settin g th e hs ofies bit ) to enabl e th e host s tart of f rame inter rupt (hsof i). clea r b y so f tware (by setti ng t he hs ofiec bit) to dis ab le the ho st star t o f f r a me interr upt (hsofi ). 31 30 29 28 27 26 25 24 ? dma6inte dma5inte dma4inte d ma3inte d ma2int e d ma1int e ? r r r r r r 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? p6inte p5inte p4inte p3inte p2inte p1inte p0inte r r r r r r r 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 ? hwupie hsofie rxrsmie rsmedie rstie ddiscie dconnie r r r r r r r 0 0 0 0 0 0 0 32058k avr32-01/12 605 at32uc3a ? hw upie: host wake-u p interrupt enable set by softwar e (by setting t he hwupies bit) t o enable t he host wake-up interrup t (hwupi). clea r by softwa r e ( by setti ng t he hwup iec bit) t o disabl e th e host wake-u p int errupt (hwupi ). ? pxinte, x in [0..6]: pipe x interrupt enable set by softwar e (b y setting t he pxint es bi t) t o enab le th e pipe x interrupt (pxint). clear by software (by setting the pxintec bi t) t o disable the pipe x i nterrup t (pxint). ? d maxinte, x in [1..6]: dma channel x interrupt enable set by softwar e (by setting the dmaxintes bi t) t o enable the dm a channe l x interrupt (dmaxint). clear by s oftwar e (b y setting th e dm axint e c bit ) to d isabl e th e dm a channe l x interru pt (dm a xint). 32058k avr32-01/12 606 at32uc3a 30.8.3 .6 usb ho st global interrupt enable clear register (uhinteclr) offset: 0x0414 regis te r nam e: uhint e clr acces s type: write-only rea d value: 0x00000000 ? dconniec: d e vice connectio n inter rupt enable clear set to c lear dconnie. clea rin g has n o e ffect. alway s r e ad as 0. ? ddisciec: d evice disconnectio n inter r upt en ab le clear set to clea r ddisciec. clea rin g has n o e ffect. alway s r e ad as 0. ? r stiec: usb reset se nt interrupt enab le clear set to clear rstie c. clea rin g has n o e ffect. alway s r e ad as 0. ? r smediec: downstream re sume sent interrupt enab le clear set to c lear rsmediec. clea rin g has n o e ffect. alway s r e ad as 0. ? r xrsm iec: upstre am re sume received interrupt enable clear set to clear rstie c. 31 30 29 28 27 26 25 24 ? dma6intec dma5intec dma4intec dma3intec dma2intec dma1intec ? w w w w w w 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? p6intec p5intec p4intec p3intec p2intec p1intec p0intec w w w w w w w 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 ? hwupiec hsofiec rxrsmiec rsmediec rstiec ddisciec dconniec w w w w w w w 0 0 0 0 0 0 0 32058k avr32-01/12 607 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? hs ofiec: host sta r t of fram e interrupt enable clear set to clea r hsofiec. clea rin g has n o e ffect. alway s r e ad as 0. ? h wupiec: host wake -up interrupt enab le clear set to clea r hwupiec. clea rin g has n o e ffect. alway s r e ad as 0. ? pxi nte c, x in [0.. 6]: pip e x in terr upt enable clear set to clear pxi ntec. clea rin g has n o e ffect. alway s r e ad as 0. ? dmax i ntec, x in [1..6]: dma c ha nnel x interr upt enable clear set to clear dmaxi ntec. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 608 at32uc3a 30.8.3 .7 usb ho st global interrupt enable set register (uhinteset) offset: 0x0418 regis te r nam e: uhinteset acces s type: write-only rea d value: 0x00000000 ? dconn ies: de vice connect ion inte rrupt enab le set se t t o set dconnie. clea rin g has n o e ffect. alway s r e ad as 0. ? dd iscies: de v ice disc onnectio n in terrupt e nabl e set set to set ddiscie. clea rin g has n o e ffect. alway s r e ad as 0. ? r sties: usb re set sent interrupt enable set se t to se t r s t ie. clea rin g has n o e ffect. alway s r e ad as 0. ? r smedies: d o wnstream resume sent interrupt enable set set to se t rsmedie. clea rin g has n o e ffect. alway s r e ad as 0. ? r xr smies: upstream re sume received in terrupt enable set set to se t rxrsmie. 31 30 29 28 27 26 25 24 ? dma6intes dma5intes dma4intes dma3intes dma2intes dma1intes ? w w w w w w 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? p6intes p5intes p4intes p3intes p2intes p1intes p0intes w w w w w w w 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 ? h wupies hsofie s r xrsmies r smedie s r sti es ddiscie s dconnies w w w w w w w 0 0 0 0 0 0 0 32058k avr32-01/12 609 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? h sofies: hos t start of fram e interrupt enab le set set to se t hsofie. clea rin g has n o e ffect. alway s r e ad as 0. ? hw u pies: host wa ke-up interrupt enab le set se t t o set hwu pie . clea rin g has n o e ffect. alway s r e ad as 0. ? pxinte s, x in [0..6]: pipe x interrupt enab le set set to set pxinte . clea rin g has n o e ffect. alway s r e ad as 0. ? dm a xintes, x in [1. . 6]: dm a channe l x interrupt enable set set to set dmaxinte . clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 610 at32uc3a 30.8.3 .8 usb host frame nu mber register (uhfnum) offset: 0x0420 regis te r nam e: uhfnum acces s type: read/write reset value: 0x00000000 ? fnum : fr ame number th e valu e co nt ain ed in this re gister is th e cu rr ent sof number . th is valu e ca n b e modifie d by software. ? fle nhigh: fram e length this register gives the 8 high-order bits o f the 14-b its internal fram e counter (fra me counte r at 12 mhz, co unte r lengt h is 1200 0 t o ensur e a sof generatio n every 1 ms). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 flenhigh ru 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? ? fnum rwu 0 0 0 0 0 0 7 6 5 4 3 2 1 0 fnum ? ? ? rwu 0 0 0 0 0 32058k avr32-01/12 611 at32uc3a 30.8.3 .9 usb host frame nu mber register (uhaddr1) offset: 0x0424 regis te r nam e: uhaddr1 acces s type: read/write reset value: 0x00000000 ? uhaddr _p0 : usb host address th ese bits should contain t he address of t he pipe 0 of th e usb device. cleare d by hardware when a usb reset is r equested. ? uhaddr _p1 : usb host address th ese bits should contain t he address of t he pipe 1 of th e usb device. cleare d by hardware when a usb reset is r equested. ? uhaddr _p2 : usb host address th ese bits should contain t he address of t he pipe 2 of th e usb device. cleare d by hardware when a usb reset is r equested. ? uhaddr _p3 : usb host address th ese bits should contain t he address of t he pipe 3 of th e usb device. cleare d by hardware when a usb reset is r equested. 31 30 29 28 27 26 25 24 ? uhaddr_p3 rwu ? 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? uhaddr_p2 rwu ? 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? uhaddr_p1 rwu ? 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 ? uhaddr_p0 rwu ? 0 0 0 0 32058k avr32-01/12 612 at32uc3a 30.8.3.10 u sb host frame nu mber register (uhaddr2) offset: 0x0428 regis te r nam e: uhaddr2 acces s type: read/write reset value: 0x00000000 ? uhaddr _p4 : usb host address th ese bits should contain t he address of t he pipe 4 of th e usb device. cleare d by hardware when a usb reset is r equested. ? uhaddr _p5 : usb host address th ese bits should contain t he address of t he pipe 5 of th e usb device. cleare d by hardware when a usb reset is r equested. ? uhaddr _p6 : usb host address th ese bits should contain t he address of t he pipe 6 of th e usb device. cleare d by hardware when a usb reset is r equested. ? uhaddr _p7 : usb host address th ese bits should contain t he address of t he pipe 7 of th e usb device. cleare d by hardware when a usb reset is r equested. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? rwu ? 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? uhaddr_p6 rwu ? 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? uhaddr_p5 rwu ? 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 ? uhaddr_p4 rwu ? 0 0 0 0 32058k avr32-01/12 613 at32uc3a 30.8.3.11 u sb pipe enable/reset register (uprst) offset: 0x0041c regis te r nam e: uprst acces s type: read/write reset value: 0x00000000 ? penx, x in [0..6]: pipe x enable set to enable the pipe x. clear to di sable the pipe x, wh at forces the pipe x state to inactive and resets the pi pe x regis t ers (upcfgx, ups tax, upconx) bu t no t t he pip e configurati on (all oc, pbk, psize). ? p rstx, x in [0..6]: pipe x re set set by software to rese t the pipe x fif o. this resets the endpoin t x r egisters (upcfg x, upstax, upconx) but no t t he endpoint configuration (alloc, pbk, psize, pto k en, ptype, p epnum, intfrq). all t he e ndpoi nt mecha nism (fif o co unte r, reception , t ra n smissio n, etc. ) is reset ap art from th e dat a t o ggle management . the endpoint configu r ation remains active and t h e endpoint is still enabled. t hen, clea r by so ftware to c omplete th e reset operatio n an d to start usin g th e f if o. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? prst6 prst5 prst4 prst3 prst2 prst1 prst0 rwu rwu rwu rwu rwu rwu rwu 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? pen6 pen5 pen4 pen3 pen2 pen1 pen0 rw rw rw rw rw rw rw 0 0 0 0 0 0 0 32058k avr32-01/12 614 at32uc3a 30.8.3.12 u sb pipe x co nfiguratio n registe r (upcf gx) offset: 0x0500 + x . 0x04 regis te r nam e: upcfgx , x in [0..6] acces s type: read/write reset value: 0x00000000 ? a lloc: pip e memory allocate set t o configur e the pi pe memory with t h e characteristics. clear to up d ate the memory allocation. th is bi t is cleare d by hardwar e whe n a usb r eset is r equested. refe r to th e dpra m management chapte r for mor e details. ? p bk: pip e ba nks set t o se lect th e n u mbe r o f ba nks for t h e pipe: fo r contro l endpoints, a single-b ank pipe (00b) shoul d be selected. cleared by hardware upo n sendin g a usb res et. 31 30 29 28 27 26 25 24 intfrq rwu 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ? ? ? ? pepnum rwu 0 0 0 0 15 14 13 12 11 10 9 8 ? ? ptype ? autosw ptoken rwu rwu rwu 0 0 0 0 0 7 6 5 4 3 2 1 0 ? psize pbk alloc ? rwu rwu rwu 0 0 0 0 0 0 pbk endpo int banks 0 0 1 (si n gle-b ank pip e) 0 1 2 (double-bank pipe) 1 0 3 (triple-bank pipe) 1 1 reserved 32058k avr32-01/12 615 at32uc3a ? psize: pipe si ze set t o s ele ct th e siz e of eac h pi pe ba nk: cleared by hardware upo n sendin g a usb res et. ? pto ken: pipe token set to select th e endpoint token: ? autosw: automati c switch set t o au toma tica lly switch ba nk when it is ready . clear to disable th e automatic b ank switching. cleared by hardware upo n sendin g a usb res et. ? ptype: pipe ty pe set t o s ele ct th e p i pe typ e: cleared by hardware upo n sendin g a usb res et. ? pepnum: pipe en dpoint number set this field accordin g to the pipe configuration. set th e numbe r o f th e endpoint targete d by th e pipe. th is valu e is from 0 t o 15. cleared by hardware upo n sendin g a usb res et. psize endpoin t size 0 0 0 8 bytes 0 0 1 16 bytes 0 1 0 32 bytes 0 1 1 64 bytes 1 0 0 1 28 by tes 1 0 1 2 56 by tes 1 1 0 5 12 by tes 1 1 1 1024 bytes ptoken endpoint direction 00 setup 01 in 10 out 11 reserved ptype pipe ty pe 0 0 control 0 1 isochronous 1 0 bulk 1 1 interrupt 32058k avr32-01/12 616 at32uc3a ? i ntfrq: pipe interru pt requ est frequency these bi ts are the max imum va lue in millisec ond of the pollin g period for an interrupt pipe. th is valu e has n o ef fect fo r a non-interr upt pipe. cleared by hardware upo n sendin g a usb res et. 32058k avr32-01/12 617 at32uc3a 30.8.3.13 usb pipe x status re gister (upstax) offset: 0x0530 + x . 0x04 regis te r nam e: upstax, x in [0..6] acces s type: read-only reset value: 0x00000000 ? r xini: received in data interrup t flag set by hardware whe n a ne w usb messag e is stored in the curr ent ban k of the pipe . th is trigger s an interrup t if the rxine bit is set. s h all be cleare d by software (b y setting the rxi n ic bit). ? txouti: transmit ted ou t data interrupt flag set by hardware when the cu r re n t out b an k is fr e e an d c an b e filled . this trigg ers an in ter r upt i f the txoute bit is set. shall be cleare d by software (b y settin g the txouti c bit). ? t x stpi: t ransmitted se tu p i n terru pt fl ag for control en dpoint s. set by ha rdware when the current setup bank is free and can be filled. this trigger s an interrupt i f the txstpe bit is set. s h all be cleare d by soft ware (by setti ng the txstpic bit). ? underfi: und erflo w inte rrupt flag set by ha rdwar e when a t ransaction underflow occurs in the current isochronous or interrupt pipe . (the p ipe can?t sen d the out dat a packet in time because the cu r rent bank is not ready). a zer o-length-packet (z lp) will be se nd instead of. this triggers an interrupt i f t he un d erf le bi t is se t . sh al l be c le a red by so ft ware (by setting the unde rfic bit). ? perri : pipe erro r interrupt flag se t by hardwar e wh en an err or o c cur s on t he c u r r en t b a nk of th e p ipe . this tri g ge rs an inte rrupt if the per re bi t is set. refers to the uperrx registe r to determin e th e source of th e error. automaticall y cleare d by hardware when the error source bit i s cleared. ? nakedi: na ke d inte rrupt flag set by hardware when a n a k has been receiv ed on the current bank of the pipe. t h is triggers an interrupt if the nakede bit is set. shall be cle a red by soft ware (by setting the nakedic bit). 31 30 29 28 27 26 25 24 ? pbyct r 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 pbyct ? cfgok ? rwall r r r 0 0 0 0 0 0 15 14 13 12 11 10 9 8 currbk nbusybk ? ? dtseq r r r 0 0 0 0 0 0 7 6 5 4 3 2 1 0 short packeti rxs tall di/ crc err i overfi na k edi perr i txstpi/ under f i txouti rxini r r r r r r r r 0 0 0 0 0 0 0 0 32058k avr32-01/12 618 at32uc3a ? overfi : overflow inte rrupt flag set by ha rdwar e when th e curren t pipe has re ceived more data th an the ma ximum length of the cu rren t pi pe. an interrupt is triggered if the ove r fie bit is set. sh a ll be clea re d by so ftwa re (b y setting the overfic bit). ? r xst alldi: receive d stalled interr upt flag for al l endpoints bu t isochronous. se t by hardware when a stal l handshak e ha s bee n receive d on th e current bank of the pipe. the pipe is automatica l ly fr ozen. this triggers an inte rrupt if the rxst alle bit is set. shall be cleared to hand- s hake th e int er rupt (b y se tting the rxst alldi c bit). ? crcerri: c rc erro r interrupt flag for isochronou s endp oint, set by hardware when a crc error occur s on t h e current bank of the pip e . t hi s t r igge r s a n in ter- rupt if the t xstpe bit i s set. shall be cleared to handshake the interrupt ( b y setting the crcerric bit). ? sho rtpa cketi: sho rt pa ck et interru pt fl ag set by hardware when a s hort packe t is received by th e ho st controller (packe t length inferior to t h e psize programmed field). sh all be cleare d to handshake the interrupt (b y setting the shortpacketic bit). ? d tseq: data togg le sequence set by ha rdwa re to indicat e th e da ta pi d of th e curren t b ank. for out pipe, thi s field indic a tes the data toggle of the next pack et that w ill be sent. for in pipe, this fiel d indicates th e da ta toggle of the received packet stored in the curren t bank. ? n busyb k: number of busy banks set by ha rdwar e to indicate th e number of bu sy bank. fo r out pipe , it i ndicates the number of b usy bank(s), filled by the user , read y for out t ransfer. when all ba nks are busy, this triggers an pxint int e rrupt if upconx.nbusybk e = 1. for in pi pe , it indicates the numbe r o f busy bank(s ) filled by in transaction from the device . whe n a ll banks are free , this triggers an pxint interrupt if up conx.nbu sybke = 1.. dtseq data to gg le sequence 0 0 data0 0 1 data1 1 0 reserved 1 1 reserved nbusybk num ber of bu sy bank 0 0 al l banks are free. 0 1 1 bu sy bank 1 0 2 bu sy banks 1 1 reserved 32058k avr32-01/12 619 at32uc3a ? currbk: cu rrent bank fo r non-control pipe , set by hardware to indicate t he number of t he current bank. note that this field may be update d 1 cloc k cycle after the rwal l bit changes, so the user should not poll this field as a n inte rr upt flag. ? rw a ll: re ad/writ e allo wed f o r out pi pe, se t by har dware w he n t he c urren t ban k i s no t f ull, i.e . th e software ca n write fur th e r d ata into th e fifo. for in pipe, se t by hardwa re whe n th e current b ank is not empt y, i.e. th e softwar e can read further data fro m th e fifo. cleare d by hardware otherwise. th is bi t is also clear ed by hardwar e when th e rxstal l or th e perr bit is set. ? c fgok: config uratio n ok status th is bi t is updat ed when th e alloc bi t is set. set by hardwar e if th e pi pe x n u mbe r o f ban ks (pbk ) an d size (p size) ar e corre ct compare d t o th e maxima l allow e d n u m- be r of ba nks an d size for this pi pe and to th e maximal fifo s ize (i.e. the dpram size). if this bit is cleared by hard wa re, th e user should reprogram th e upcfgx register with cor rect pbk a nd p si ze valu es. ? pbyct : pipe byte count set by th e hardware t o indicate th e byte count o f th e fifo. for ou t pipe, inc r emented aft er each byt e writt en by the soft ware int o the pipe and decrement ed after ea ch byt e sent to th e peripheral. fo r i n pipe , incremente d afte r each byte receive d from the peripheral an d decremented afte r each by te read by t h e soft- ware from th e pipe. note that this field may be update d 1 cloc k cycle after the rwal l bit changes, so the user should not poll this field as a n inte rr upt flag. currbk curr ent bank 0 0 bank0 0 1 bank1 1 0 bank2 1 1 reserved 32058k avr32-01/12 620 at32uc3a 30.8.3.14 usb pipe x status clea r registe r (upstaxclr) offset: 0x0560 + x . 0x04 regis te r nam e: upstaxclr , x in [0..6] acces s type: write-only rea d value: 0x00000000 ? rx inic : rece iv ed in data int e rrupt fla g cl ear set t o clea r rxini . clea rin g has n o e ffect. alway s r e ad as 0. ? txoutic: transmitted ou t data inte rrupt flag clear set t o clea r tx out i. clea rin g has n o e ffect. alway s r e ad as 0. ? txstpic: transm itted setup inte rrupt flag clear set to clear txstpi . clea rin g has n o e ffect. alway s r e ad as 0. ? underfic: u nderflo w interrupt flag clear set to clear un derfi. clea rin g has n o e ffect. alway s r e ad as 0. ? nakedic: na ke d interrupt flag clear set to clear nake di. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 short packetic rxstalldic/ crcerric overfic nakedic ? txstpic/ u nderf ic txoutic rxinic w w w w w w w 0 0 0 0 0 0 0 32058k avr32-01/12 621 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? overf ic: over flow in ter rup t flag clear set to clea r overfi. clea rin g has n o e ffect. alway s r e ad as 0. ? r xst alldic: received stal led interru pt flag clear set to clear rxstall di. clea rin g has n o e ffect. alway s r e ad as 0. ? crc erric: crc erro r interrupt flag clear set to c lear crcerri. clea rin g has n o e ffect. alway s r e ad as 0. ? shortpa cketic: short packet interrupt flag clear set to clear shortpack eti. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 622 at32uc3a 30.8.3.15 u sb pipe x status set register (upstaxset) offset: 0x0590 + x . 0x04 regis te r nam e: upstaxse t, x in [0..6] acces s type: write-only rea d value: 0x00000000 ? r xinis: receiv ed in data interrupt flag set set to se t rxini, what ma y b e usef ul for t est or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? txoutis: tran smitted out data inte rrupt flag set set to se t txouti, what may be useful for test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? txstpis: tr ansmitted setu p interrupt flag set set to se t txstpi , what ma y b e usef ul for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? underfis: unde rflo w inter rupt flag set set to se t underfi, what ma y b e usef ul for t est or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? perri s: pipe er ro r in ter rup t f la g set set to se t perri, what may b e useful for test o r debug purposes. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? nbusybks ? ? ? ? w 0 7 6 5 4 3 2 1 0 short packetis rxstalldis/ crcerr is overfis nakedis perris txstpis/ underfis txoutis rxinis w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 623 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? nakedis: na ke d inter rupt flag set set to se t nakedi , what ma y be usef ul for test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? over fis: overflow inte rrupt flag set set to se t overfi , what ma y be usef ul for test or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? rxst alldis: receive d stalled interru pt flag set set to se t rxstalldi, what ma y b e usef ul for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? crc erris: crc erro r interrupt flag set set to se t crcerri, what may b e useful for test o r debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? shortpa cketis: short pa cket interrupt flag set set t o se t shortpac keti, w ha t m ay b e usefu l for te st or debu g purposes. clea rin g has n o e ffect. alway s r e ad as 0. ? n busyb ks: number of busy banks interr u pt fl a g set set to set nb u sybki, what may be us eful for test or debug purposes. clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 624 at32uc3a 30.8.3.16 u sb pipe x c ontr o l r e gister (u pc on x) offset: 0x05c0 + x . 0x04 regis te r nam e: upconx , x in [0..6] acces s type: read-only reset value: 0x00000000 ? rx i ne: received in data interr u pt enable set by software (by setting the rxines bit) t o enabl e th e received in data interrup t (rxine). clear by software (by setting the rxinec bit) to disabl e th e received in data inter rup t (rxine). ? txoute: transmit ted ou t d ata inte rru pt e nable set by softwar e (by setting the txoutes bi t) t o enable the transmitted ou t data interrupt (txoute). clear by software (by setting the txoutecbit) to disabl e th e transmitted out data interrup t (txoute). ? t xstpe: tr ansmitted setup interrupt ena b le set by software (by setting the txstpes bit) to enable the transm itted setup interrupt (t xstpe). clear by s oftware (b y setting t he txstpec bit) to disabl e th e transmitt ed setup interrupt (txstpe). ? underfie: unde rflo w inter rupt enable set by softwar e (by setting the und erfies bit) t o ena ble t he un der flow i nt err upt ( underfi e) . cl ear by softwa r e (by sett ing t he underfie c bit) to disa ble the underflow interrupt (underfie). ? perr e: pipe erro r interrupt enable set by software (b y setting t he perres bit) to enable th e pipe error interrupt (perre). clear by s oftware (b y setting t he perrec bit) to disabl e th e pipe erro r interrupt (perre). ? nak ede: nake d interrupt enable set by software (by setting the nak e des bit) to enable the n aked interrupt (nakede). clear by software (by setting the nake d ec bit) to disable the n aked interrupt (nakede). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? rstdt pfreeze pdishdma ru ru ru 0 0 0 15 14 13 12 11 10 9 8 ? fif ocon ? nbu sybke ? ? ? ? ru ru 0 0 7 6 5 4 3 2 1 0 short packetie rxstallde/ crc err e overfie nakede perre txstpe/ underfie txoute rxine ru ru ru ru ru ru ru ru 0 0 0 0 0 0 0 0 32058k avr32-01/12 625 at32uc3a ? over fie: overflow interrupt enable set by softwar e (by setting the o verfies bit) to enable th e overflow interrup t (overfie). clear by software (by setting the ov erfiec bit) to disabl e th e overflow interrupt (overfie). ? r xst allde: receiv ed stalle d inter rupt enable set by software (b y setting t he rxstalldes bit) to enable the received stall ed interrupt (rxstallde). clear by s oftware (b y setting t he rxstalld ec bit) to disabl e th e re ceived stalled interrupt (rxstallde). ? crcerre: crc erro r interrupt enable set by so ftware (by setting the cr cerres bit) to enable the c r c erro r interrupt ( crcerre). clear by so ftware (by setting the cr cerrec bit) to disable t he crc error interrupt (crcerre). ? shortpacketie: short packet interrupt enable set by softwar e (by setting the shortpacketes bi t) t o enable the shor t packet interrupt (shortpacketie). clear by s oftwa re (b y setting t he shortpacke te c bi t) to disable t he short packet interrupt (shortpackete). ? n busyb ke: number of busy banks interrup t enable set by software (by setting the nbu sybkes bit) to enable the number of busy banks interrupt ( nbusybke). clear by software (by setting the n bus ybkec bit) to disable the number of busy banks i n terrupt (nb usybke). ? f ifocon: fifo control f o r out an d s etup pipe : set by hardwar e when th e curren t ba nk is free , at the same t im e th an txout i or txstpi. clea r by softwar e (b y setting t he fifoco nc bit) t o sen d th e fi fo dat a and t o switch t he bank. for in pipe: set by hardwar e whe n a new in messa ge is st ored in t he current bank, a t the same time than rxini. clear by s oftwar e (b y setting t he fifoco nc bi t) to fre e th e curren t ba nk and to switch to t he ne xt bank. ? pdishdma: pipe interrupts disabl e hdma request enable see epdis h dma (ueconx register). ? p freeze: pi p e f ree ze set by soft ware (by setting the pf reezes bit) to fr eeze the pipe requests generation. clear by soft ware (by setting the pf reezec bit) to enable the pipe reque st generation. t hi s bi t is set by ha r dware w he n : - th e pipe is no t configured - a stal l handsha ke has been received on th is pipe - an e rro r occu rs on the pipe (per r = 1) - ( inr q+1 ) i n r equ ests h av e b een proce ss ed th is bi t is set at 1 by hardwar e after a pipe rese t or a pi pe enable. ? r stdt : rese t data toggle set by soft ware (by setting the rstdts bit) to re se t the data toggle to it s initial value for the current pipe. cleare d by hardware when proceed. 32058k avr32-01/12 626 at32uc3a 30.8.3.17 u sb pipe x c ontrol clear registe r (upconxclr) offset: 0x0620 + x . 0x04 regis te r nam e: upconxclr, x in [0..6] acces s type: write-only rea d value: 0x00000000 ? r xinec: received in dat a interrupt enab le clear set to clea r rxine. clea rin g has n o e ffect. alway s r e ad as 0. ? txoutec: tran smitted out data inte rrupt enab le clear set to clea r txoute. clea rin g has n o e ffect. alway s r e ad as 0. ? txstpec: tr ansmitted setu p interrupt enab le clear set to clear txstpe . clea rin g has n o e ffect. alway s r e ad as 0. ? underfiec: u nderflo w interr upt enable clear set to clear un derfie. clea rin g has n o e ffect. alway s r e ad as 0. ? perr ec: pipe erro r interrupt enable clear set to clear per re. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? pfreezec pdishdmac w w 0 0 15 14 13 12 11 10 9 8 ? fifoconc ? nbusybkec ? ? ? ? w w 0 0 7 6 5 4 3 2 1 0 short packetiec rxstalldec/ crcerrec o verfie c na kedec perrec txstpec / underfiec txoutec rxinec w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 627 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? nakedec: na ke d inte rrupt enab le clear set to clear nake de. clea rin g has n o e ffect. alway s r e ad as 0. ? over fiec: overflow interrupt enable clear set to clea r overfie. clea rin g has n o e ffect. alway s r e ad as 0. ? r xst alldec: receive d stalled interr upt enable clear set to clear rxstall de. clea rin g has n o e ffect. alway s r e ad as 0. ? crcerrec: crc er ro r interrupt enab le clear set to c lear crcerre. clea rin g has n o e ffect. alway s r e ad as 0. ? shortpa cketiec: short packet inte rrupt enab le clear set to clear shortpack etie. clea rin g has n o e ffect. alway s r e ad as 0. ? nb u sy b kec: num b er o f bu sy b a nks interrupt enab le clear set to clear nbu sybke. clea rin g has n o e ffect. alway s r e ad as 0. ? fifocon c: fifo contro l clear set t o clear fifocon. clea rin g has n o e ffect. alway s r e ad as 0. ? pdishdmac : pipe interrupts disa ble hdma request enab le clear set to clear pdi shdma. clea rin g has n o e ffect. alway s r e ad as 0. ? pfreezec: pipe free ze clear set to clear pfreeze. 32058k avr32-01/12 628 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 629 at32uc3a 30.8.3.18 usb pipe x contr o l set re gister (upconxset) offset: 0x 05 f 0 + x . 0x04 regis te r nam e: upconx set, x in [0..6] acces s type: write-only rea d value: 0x00000000 ? rx ines: rece i ve d i n data interrupt enable set set t o se t rxine. clea rin g has n o e ffect. alway s r e ad as 0. ? t xoute: transmitted o u t da ta interrupt enab le set set t o se t rxine. clea rin g has n o e ffect. alway s r e ad as 0. ? t x stpes: t ransm i tted set up interrupt enable set set to set txstpe . clea rin g has n o e ffect. alway s r e ad as 0. ? underfies: unde rflo w inter rupt enab le set se t t o se t u n derfie. clea rin g has n o e ffect. alway s r e ad as 0. ? perr es: pipe er ro r in ter rup t ena bl e set set to set pe rre. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? rstdts pfreezes pdishdmas w w w 0 0 0 15 14 13 12 11 10 9 8 ? ? ? nbusybkes ? ? ? ? w 0 7 6 5 4 3 2 1 0 short packeties rxstalldes/ crcerres overfies nakedes perres txstpes/ underfies txoutes rxines w w w w w w w w 0 0 0 0 0 0 0 0 32058k avr32-01/12 630 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. ? nak edes: nake d interrupt enab le set set to se t nakede. clea rin g has n o e ffect. alway s r e ad as 0. ? over fies: overflow in terrupt ena b le set set to set overfie . clea rin g has n o e ffect. alway s r e ad as 0. ? r xst alldes: receiv ed stalle d interr upt enable set set to set rx stallde. clea rin g has n o e ffect. alway s r e ad as 0. ? cr cerres: c rc erro r interrupt enable set se t t o se t c r cerre. clea rin g has n o e ffect. alway s r e ad as 0. ? shortpacketies: short packet interrupt enab le set set to set shortpa cketie. clea rin g has n o e ffect. alway s r e ad as 0. ? n busyb kes: number of busy banks interrup t ena b le set set to set nb usybke. clea rin g has n o e ffect. alway s r e ad as 0. ? pdishdmas: pipe interrupts dis abl e hdma request enable set set to se t pdishdma. clea rin g has n o e ffect. alway s r e ad as 0. ? p freezes: pi p e f reeze set set to set pfreeze . clea rin g has n o e ffect. alway s r e ad as 0. ? r stdts: reset data toggl e set set to se t rstdt. 32058k avr32-01/12 631 at32uc3a clea rin g has n o e ffect. alway s r e ad as 0. 32058k avr32-01/12 632 at32uc3a 30.8.3.19 u sb pipe x in r equest register (upinrqx) offset: 0x0650 + x . 0x04 regis te r nam e: upinrqx, x in [0..6] acces s type: read/write reset value: 0x00000000 ? inr q: in request number be fo re freeze enter the number of i n transactions bef ore the usb controller freezes the pipe. the u sb controller will perform (inrq+1) in requests before to freeze t he pipe . th is counter is au tomatically decrease d by 1 ea ch time a in r equ est has been suc- cessfu lly performed. t hi s reg ister h as n o effec t when the in mode bit is se t (infinite in requests generation till the pipe i s not frozen). ? inmode: in request mode set t his bit t o a llow t he u sb con troller t o perfor m infinit e i n r eque sts w he n t h e p ip e is no t f rozen . clear th is bi t to perfo r m a pr e- define d numb er of in r equ ests. th is number is t h e inrq field. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? inmode rw 0 7 6 5 4 3 2 1 0 inrq rwu 0 0 0 0 0 0 0 0 32058k avr32-01/12 633 at32uc3a 30.8.3.2 0 u sb pipe x error re gister (uperrx) offset: 0x0680 + x . 0x04 regis te r nam e: uper rx, x in [0..6] acces s type: read/write reset value: 0x00000000 ? datatgl: data toggle error set by ha rdwar e whe n a data toggl e erro r ha s bee n detected. sh al l be cl ea re d by sof twa re. settin g b y sof twa r e h a s n o effect . ? datapid: da ta pid error set by ha rdwar e whe n a data pid erro r ha s bee n detected. sh al l be cl ea re d by sof twa re. settin g b y sof twa r e h a s n o effect . ? pid : pid error set by ha rdwar e whe n a pid er ror has be e n detected. sh al l be cl ea re d by sof twa re. settin g b y sof twa r e h a s n o effect . ? timeout : time-out error set by ha rdwar e whe n a time out erro r has be en detected. sh al l be cl ea re d by sof twa re. settin g b y sof twa r e h a s n o effect . ? cr c 16: crc 16 error se t by ha rdwar e w hen a crc 16 e rro r has b een de tec ted. sh al l be cl ea re d by sof twa re. settin g b y sof twa r e h a s n o effect . ? c ounter: erro r counter se t by ha rdwar e w hen a crc 16 e rro r has b een de tec ted. sh al l be cl ea re d by sof twa re. settin g b y sof twa r e h a s n o effect . 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? counter crc16 timeout pid datapid datatgl rwu rwu rwu rwu rwu rwu 0 0 0 0 0 0 0 32058k avr32-01/12 634 at32uc3a 30.8.3.21 us b hos t dma channel x nex t descri p tor add re ss r eg ister (uhd m ax_n extd es c) offset: 0x0710 + (x - 1 ) . 0x10 regis te r nam e: uhdmax_nextdesc , x in [1..6] acces s type: read/write reset value: 0x00000000 same as ?usb device dma channel x next de sc riptor addres s registe r (uddmax_nextdesc )? on pag e 591. 31 30 29 28 27 26 25 24 nxt_desc_addr rwu 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 nxt_desc_addr rwu 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 nxt_desc_addr rwu 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 nxt_desc_addr ? ? ? ? rwu 0 0 0 0 32058k avr32-01/12 635 at32uc3a 30.8.3.22 u sb host dma channel x hsb address register (u hdmax_addr) offset: 0x0714 + (x - 1 ) . 0x10 regis te r nam e: uhdmax_addr, x i n [1..6] acces s type: read/write reset value: 0x00000000 same as ?usb device dma channel x hsb addre s s register (uddmax_addr)? on p ag e 592. 31 30 29 28 27 26 25 24 hsb_addr rwu 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 hsb_addr rwu 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 hsb_addr rwu 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 hsb_addr rwu 0 0 0 0 0 0 0 0 32058k avr32-01/12 636 at32uc3a 30.8.3.2 3 u sb h ost dma ch ann e l x control re gister (uhdmax_control) offset: 0x0718 + (x - 1 ) . 0x10 regis te r nam e: uhdmax_control , x in [1..6] acces s type: read/write reset value: 0x00000000 same as ?usb device dma channel x control regi st er (uddmax_control) ? o n pag e 593. (just replac e th e in endpoint term by out e ndpoint, a nd vice-versa) 31 30 29 28 27 26 25 24 ch_byte_length rwu 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ch_byte_length rwu 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 burst_lock _en desc_ld_ irq_en eobuff_ irq_en eot_irq_en dmaend_en buff_close _in_en ld_nxt_ch_ desc_en ch_en rwu rwu rwu rwu rwu rwu rwu rwu 0 0 0 0 0 0 0 0 32058k avr32-01/12 637 at32uc3a 30.8.3.24 u sb host dma channel x status register (uhdmax_status) offset: 0x0 71c + (x - 1 ) . 0x10 regis te r nam e: uhdmax_status , x in [1..6] acces s type: read/write reset value: 0x00000000 same as ?u sb device dma channe l x stat us registe r (uddmax_status)? o n page 595. 31 30 29 28 27 26 25 24 ch_byte_cnt ru 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ch_byte_cnt ru 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? desc_ld_ sta eoch_buff_ sta eot_sta ? ? ch_active ch_en ru ru ru rwu rwu 0 0 0 0 0 32058k avr32-01/12 638 at32uc3a 30.8.4 us b pipe/endpoint x f ifo data register (usb_fifox_data) note that this regis t er can be access e d even if usbe = 0 or frzclk = 1 . disabling the u s b controller (b y clearing the usbe bit ) does not reset th e dpram. 32058k avr32-01/12 639 at32uc3a 31. t imer/counter (tc) re v: 2.2.2.1 31.1 features ? thre e 16-bit timer counter channels ? a w ide ra ng e o f fu nc ti on s including: ? frequency measurement ? e vent counting ? i nte rva l measurement ? p ul se generation ? delay timing ? p ulse widt h modulation ? up/down capabilities ? each ch an nel is us er -con fi g urab l e an d contain s: ? three ex ternal clock inputs ? five inte rnal cloc k inputs ? two multi-purp ose input/outp ut signals ? intern al int errup t signal ? tw o g l ob a l registe r s tha t ac t on all th ree tc cha nnels 31.2 description th e time r counte r (tc) includes three ident ical 16-b it time r counter channels. each ch anne l ca n be independently programmed to perform a wid e rang e of function s including frequency measurement , event counting, interval measurement, pulse generation, delay timin g an d pulse widt h modulation. each channel has three external cl oc k inputs, fi ve internal clock inputs and two m ulti-p urpose input/outpu t signa ls which can b e configure d by t he user . each chann el drives an internal inter- rupt sign al which ca n b e programme d t o genera te processor interrupts. t he ti me r count e r b loc k h as tw o g loba l register s whic h act upon al l thre e t c channe ls. th e block contro l register allows t he three channels to be start ed simultane ously with th e same instruction. the block mode registe r define s th e extern al clo ck inpu ts fo r each channel , allowin g them t o be cha ined. 32058k avr32-01/12 640 at32uc3a 31.3 block diagram figur e 31-1. timer counte r block diagram tabl e 31-1. sign al na me description block/channel sign al name description chann el signal xc 0, xc1, xc2 exter nal clock inputs tioa ca pture m o de: timer coun ter inpu t waveform mode: tim e r co unter outp ut tiob ca pture m o de: timer coun ter inpu t waveform mode: tim e r co unter inpu t/output int interrupt sign al output sync synchronizatio n in put signal timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1 32058k avr32-01/12 641 at32uc3a 31.4 pin name list 31.5 p roduct dependencies 31.5.1 i/ o lines t h e pi ns used fo r int erfacin g th e comp liant external devices ma y be multip lexed wit h pio lines. th e programmer must first program t he pi o controllers to assign the tc pi ns to their peripheral functions. 31.5.2 deb ug operation the timer co unter clocks are frozen du ring debug operation, unless t he ocd system keeps peripher als running in d ebu g operation. 31.5. 3 po wer mana gement th e time r counte r clock is generated by t he po wer manager. before usin g th e tc , th e program- me r must ensure that t he tc cloc k is enabled in th e power manager. 31.5.4 in terrupt the tc has an i nterr upt line connected t o the interrupt controller . handling t he tc interrupt require s progr amming th e interrupt contro lle r befor e confi gurin g th e tc. 31.6 functional description 31.6.1 tc description the three channe ls o f the timer counter ar e independent a nd identica l i n operation. th e regis- ters for channe l programming ar e list ed in table 31-4 on p ag e 654. 31.6.1.1 16-bit counter each c hanne l is organ ized arou nd a 1 6-bit counter. t he value of the count e r is increme nted at each positive edg e of th e select ed clock. when th e counte r has reached the valu e 0xfff f and passes t o 0x0000, an overfl ow occu rs an d the covfs bi t in sr (status register) is set. the curren t value o f the count e r is accessible in r eal tim e by reading t he counter value r egis- ter, cv. t he counter ca n be reset by a trigger . in t his case , th e counte r valu e passes to 0x0000 on th e next va lid edg e of th e select ed clock. 31.6.1 .2 cloc k selection at bl ock level, input clock sign als of ea ch chan nel can either be connected to t he external inputs tclk0, tclk1 or tclk2 , or be con nected t o the configurable i /o sign als tioa0, ti oa1 or tioa2 for chaining by p rogramming the bmr (bl o ck mode). see figur e 31-2. tabl e 31-2. tc pin list pin name descr iption type tclk0-tclk2 externa l clock input input ti o a0-ti o a2 i /o l i n e a i/o ti ob0-tiob2 i /o line b i/o 32058k avr32-01/12 642 at32uc3a each ch anne l can independent ly select an intern al o r external clock s ource for its c ounter: ? inter nal cloc k signals: timer_clock1, timer_clock2, timer_clock3, timer_clock4 , timer_clock5 . the peripher als chapter details t he connectio n of these cloc k source s. ? externa l cloc k sign als: xc0, xc1 o r xc2. the peripher als chapter details t he connectio n of these cloc k sources. t his selection is m ade by t h e tcc lk s bi ts in th e tc chann e l mod e r egiste r . th e select ed clock ca n be invert ed wit h th e clki bi t in cmr. this a llows counti ng on th e oppo- s it e edge s of t he c lock. th e burst function allows the clock to be validated when an extern al sign al is high. t he burst parameter in t h e mod e registe r defines th is signal (none, xc0, xc1, xc2). note: in a ll cases, if an externa l cloc k is us ed, th e duration of e a ch of its lev els mus t be l o ng e r t ha n th e master c lock period . the externa l cloc k frequenc y m u st be a t least 2 . 5 t ime s low e r tha n t h e m a s- ter clo ck figur e 31-2. clock selection 31.6.1 .3 clock control th e cloc k of ea ch cou nt er ca n b e co ntroll ed in tw o di ffere nt ways: i t ca n be enabled/d isabled and st arte d/ stopped . see figur e 31-3. ? the clock c an be enable d o r disabled by th e user wit h th e cl ken and the clkdis commands in the contro l register. in captur e mode it can b e disabled by an rb l oad event if ldbdis is set to 1 in cm r. in waveform mode , it can be disabled by an rc co mpare event if cpcdis is se t t o 1 in cmr. wh en disabled , the start or the stop actions have no effect: only a clken command in th e contro l register can re-enable th e clock. when th e cloc k is enabled, the clksta bi t is se t in the status register. ? the cloc k ca n also be starte d or stopped: a trigge r (software, synchro, extern al or compare) alwa ys starts t he clock. th e cloc k ca n be stopped by an rb lo ad even t in captur e mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki burst 1 selected clock 32058k avr32-01/12 643 at32uc3a (ldb st op = 1 in cmr ) o r a rc compare e v ent in waveform mode (cpcstop = 1 in cmr). th e start and th e stop comman ds hav e effe ct on ly i f th e cloc k is enabled. figur e 31-3. clock control 31.6.1.4 tc operatin g modes each ch a nne l can independent ly ope rat e in tw o differen t m odes: ? captu re mode provides measuremen t on signals. ? wavefor m mod e provides wav e generation. the tc operating mode is pro g rammed wi th the wave bit in th e tc channel mode register. i n captur e mode, ti oa an d tiob are configure d as inputs. i n w avefor m mode , tioa is a lways c on figured to be a n outpu t an d tio b is a n out pu t if i t i s no t selected t o be th e external trigger. 31.6.1.5 trigger a trigge r resets th e counte r and starts th e counter clock. three type s o f trigge rs ar e common to bot h mo de s, an d a fourt h ext ern al t r igge r is avail a ble to eac h m od e. th e following trigge rs ar e commo n t o bot h modes: ? software trigger : each channe l has a software trigger, available by settin g swtrg in ccr. ? sync: each chan nel has a synchronization signal sync. whe n asserted , th is signal ha s the sam e effect as a software trigger. th e sync signals of all ch anne ls ar e asserted simultaneously by wr iting bc r (block control) with sy n c set. ? compar e rc trigger: rc is impl emente d in each chann el an d ca n provid e a trigge r when the counter valu e matches the rc val ue if cpctrg is set in cmr. th e cha n nel can also be con figured t o h ave a n external trigg e r. in captur e mod e, the external trigge r sig nal ca n b e sele c ted be tween tioa and t iob. in wave form mo de , an ex te rnal event can be prog ram med on one of the f ollowing signals: tiob, xc0, xc1 or xc2. this external even t ca n the n be programmed t o perform a trigger by setting enetr g in cmr. q s r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger 32058k avr32-01/12 644 at32uc3a if a n external trigger is used , th e duration o f th e pu lses must be longer than the master clock perio d in orde r to be detected. regardless of the t rigger used, it will be t aken into ac count at the f ollowin g a ct i ve edg e o f t he selected cl o ck. th is mean s th at th e co unter value can be rea d differe ntly from zero just after a trigge r, espe cially whe n a low freq u ency sign al is sel ecte d as th e clo ck. 31.6.2 capture operating mode this mode is entered b y clearing the w ave parameter in cm r (channel mode register). captur e mod e allo ws th e tc channe l to perform measuremen ts such as p u lse timing , fre- quency, per io d, duty cycle and phase on t i oa and tio b sig nals which are considered as inputs. figure 31-4 shows t h e configuratio n o f th e tc channe l when programme d in captur e mode. 31.6.2 .1 captur e register s a and b register s a an d b (ra and rb) a r e use d as captur e register s. th is mean s th at th ey can be loaded with the counter va lue when a p rogr ammable event occurs on the sig nal tioa. th e ldra parameter in cmr d efines the tioa edge for th e load ing of register a, and t he ldrb parameter defin es th e ti oa edge for the loading o f register b. ra is lo aded on ly if it ha s no t bee n load ed since the las t trigger or if rb has been loade d since the la st loading of ra. rb is loaded only if ra has been loaded sin ce th e last trigge r or the last loading of rb . load ing ra or rb be for e th e re ad of th e last value loade d se ts th e overru n erro r fla g (lovrs) in sr (st atu s register). in th is ca se, t he o ld value is ov erwritte n. 31.6.2 .2 trig ge r conditions in addition to th e sync signal , t he sof twar e trigg e r an d the rc c o mpare trig ger , an ex ter nal tr ig- ge r can be define d. th e abetrg bi t in cm r selects tioa o r tiob in put sig nal as an exter nal trig ger. the etrgedg parameter defines the e d ge (rising, falling or both) detec ted to generate an external trigger . if etrgedg = 0 ( none), th e external trigger is dis abled. 32058k avr32-01/12 645 at32uc3a figur e 31-4. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clkstaclkenclkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel 32058k avr32-01/12 646 at32uc3a 31.6.3 waveform operat ing mode waveform operating mode is entered by setting the wave p a rameter in cmr (c hannel mode register). i n wave form operatin g mod e th e tc c han nel ge nerate s 1 o r 2 p wm sig n al s with th e s am e f re- quency and in dependently programmable duty cycles , or generates differe nt types of one-shot or repetitiv e pulses. in t his mode , tioa is configur ed as an output and ti ob is de f ined as a n output if it is no t used as an external event ( eevt parameter in cmr). figur e 31-5 shows the configuratio n of t he tc chann el whe n programmed in wave form operat- ing mode. 31.6.3.1 waveform selection depending on the w avsel parameter in cmr (channel mode reg i ster), the behavi or of cv varies. with any s election, ra, rb an d rc ca n all be use d as compar e registers. ra c ompare is used t o contro l the tioa output, rb com par e is used to control t he tiob output (i f correctl y configured ) and rc c ompare is use d to contro l ti oa and/or tiob outputs. 32058k avr32-01/12 647 at32uc3a figur e 31-5. wavefor m mode tcclks clki qs r s r q clkstaclkenclkdis cpcdis burst tiob register aregister bregister c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel 32058k avr32-01/12 648 at32uc3a 31.6.3.2 wavs el = 00 when wavsel = 00, the value of cv is incre m ented from 0 to 0xffff . once 0xfff f has been reached, th e valu e of cv is res e t. incrementation of cv sta r ts aga in an d the cy cle continues. see figur e 31-6. an external event trig ge r or a software trigge r can rese t the value of cv. it is imp ortant to note that the trigger may occu r at any time. see figure 31-7. rc com pare cannot be programmed to generat e a trig ger in this configur ation. at the same time, rc c ompare ca n st op th e counter clock (cpcstop = 1 in cmr ) and/or disable t he coun- ter clock (cp c dis = 1 in cmr). figur e 31-6. wavsel= 00 withou t trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples 32058k avr32-01/12 649 at32uc3a figur e 31-7. wavsel= 00 with trigger 31.6.3.3 wavs el = 10 whe n wavsel = 10 , t he va lue of cv is i ncremented from 0 to the value of rc , the n automati- cally rese t on a rc c o mpa re . onc e the value of cv h as bee n reset, it is the n incr emente d an d so on . see figur e 31-8. it is im portant to note that cv can be reset at any time by an external event or a so ftware trigger if both ar e programmed correctly. see figur e 31-9. in addition, rc c ompar e can stop th e counter cloc k (cpcst op = 1 in cmr ) and/o r disable the counter clock (cp c dis = 1 in cmr). figur e 31-8. wavsel = 1 0 withou t trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples 32058k avr32-01/12 650 at32uc3a figur e 31-9. wav se l = 10 wit h tri gger 31.6.3.4 wavs el = 01 when wavsel = 0 1, the valu e of cv is incre m ented from 0 to 0xff ff. once 0xfff f is reache d, th e valu e o f cv is decremen ted t o 0 , the n re-incremen ted t o 0xffff an d so on . see fig ur e 31-10. a t rigger su ch as an external event or a so ft ware trigger can modify cv a t an y time. if a trigge r occurs while cv is incrementing , cv then decrements . if a trig ger is received while c v is decre- menting, cv then increments. see figur e 31-11. rc co mpar e cannot b e programmed t o generat e a trigge r in t his configuration. at the sa me time , rc compar e can s top the coun ter clock (cpcstop = 1) and/or disable the counter clock (cp c dis = 1). time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger 32058k avr32-01/12 651 at32uc3a figur e 31-10. wavs el = 01 without trigger figur e 31-11. w avs el = 01 wit h tr i gger 31.6.3.5 wavs el = 11 whe n wavsel = 1 1 , th e valu e o f cv is i n cremente d from 0 to rc. o n ce rc is re ached , the valu e of cv is d e crem ente d t o 0, the n re -incr emente d t o rc a nd so on. se e figure 31-12. a t rigger su ch as an external event or a so ft ware trigger can modify cv a t an y time. if a trigge r occurs while cv is incrementing , cv then decrements . if a trig ger is received while c v is decre- menting, cv then increments. see figur e 31-13. rc c omp are can stop th e coun ter cloc k (cpcstop = 1) an d /or disable the coun ter clock (c pcdis = 1). time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a 32058k avr32-01/12 652 at32uc3a figur e 31-12. wavs el = 11 without trigger figur e 31-13. w avs el = 11 wit h tr i gger 31 .6.3. 6 exte rnal event/trigg e r con d iti ons an extern al event can b e programmed to be detected o n one of t h e clo ck sources (x c0, xc1, xc2 ) or tiob. t he external event selected can the n be use d as a trigger. the ee v t parameter in cmr sele cts the external trigger. th e eevtedg parameter defines th e trig ger ed ge for each of the possible extern al trigge rs (rising, falling or bo th ). if ee vtedg is cleare d (none), no exter nal event is de fined. time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a 32058k avr32-01/12 653 at32uc3a if ti ob is define d as an exter nal event signa l (eev t = 0), tio b is no l onge r use d as a n ou tput and the comp a re re gister b is not used to ge nerate waveforms and subsequ ently no ir qs. in th is case the tc ch anne l ca n only generat e a waveform on tioa. when an ex ternal event is d efined, it ca n be use d as a trigge r by setting bit enetrg in cmr . as i n captur e mode , the sync si g nal and t he software trigge r ar e also availabl e as triggers. rc compare can also be used a s a tri gge r depe n ding on t he p aramet er w avsel . 31.6.3 .7 out put c ontr oller the outpu t controller define s the outp ut leve l change s on tioa and t iob following an event. t io b contr o l i s used o nly i f tio b is de fined as ou tp ut ( not as an externa l even t). the following events control tioa an d tiob: softwa re trigger, external event a nd rc compare. ra com par e cont rols ti oa and rb comp a re contr ols tiob. each of these event s can be p ro- grammed to set, clea r or toggle the outpu t as defined in the corresponding parameter in cmr. 32058k avr32-01/12 654 at32uc3a 31.7 t imer counter (tc) user interface bcr (b lock con trol re gister) an d bmr (b lock mo de registe r) contro l the whole tc block. t c chann els ar e controlled by th e regist ers listed in table 31-4 . th e o ffse t of each of th e channel regist ers in tabl e 31-4 is in relation to the of fs et of t he corresponding channel as ment io ned in tabl e 31-4 . notes: 1. read-on ly if wa ve = 0 tabl e 31-3. tc glo b al memory map offset channel/register name access reset value 0x00 tc ch annel 0 see tab le 31-4 0x40 tc ch annel 1 see tab le 31-4 0x80 tc ch annel 2 see tab le 31-4 0xc0 tc blo c k control register bcr write-only ? 0xc4 tc blo c k mo de register bmr read/write 0 tabl e 31-4. tc c hann el memory map offset register name access reset value 0x00 channel c ontrol register ccr write-only ? 0x04 channe l mo de register cmr read/write 0 0x08 reserved ? 0x0c reserved ? 0x10 counter value cv read-only 0 0x14 re gi ster a ra read/ wr ite (1) 0 0x18 re gi ster b rb read/ wr ite (1) 0 0x1c regi ster c rc read/write 0 0x20 status register sr read-only 0 0x24 interr upt enab le register ier write-only ? 0x28 interr upt disab le register idr write-only ? 0x2c interr upt mask register imr read-only 0 32058k avr32-01/12 655 at32uc3a 31.7.1 tc blo c k contro l register regis te r nam e: bcr acces s type: write-only ? sync: s ynchr o command 0 = n o e ffect. 1 = asse rts t he sync signa l whic h generates a softwar e trigge r simultaneously for each o f t he channels. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? sync 32058k avr32-01/12 656 at32uc3a 31.7.2 tc blo c k mo de register regis te r nam e: bmr acces s type: read/write ? tc0 xc0s: ex te rnal cloc k sign a l 0 s elec tion ? tc1 xc1s: ex te rnal cloc k sign a l 1 s elec tion ? tc2 xc2s: ex te rnal cloc k sign a l 2 s elec tion 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? tc2xc2s tc1xc1s tc0xc0s tc 0xc0s sig nal conn ecte d t o xc0 0 0 tclk0 0 1 none 1 0 tioa1 1 1 tioa2 tc1xc1s sig nal connected to xc1 0 0 tclk1 0 1 none 1 0 tioa0 1 1 tioa2 tc2xc2s sig nal connected to xc2 0 0 tclk2 0 1 none 1 0 tioa0 1 1 tioa1 32058k avr32-01/12 657 at32uc3a 31.7.3 tc c hanne l contro l register regis te r nam e: ccr acces s type: write-only ? cl ken : counte r cloc k enabl e command 0 = n o e ffect. 1 = e nables the cloc k if clkdis is no t 1. ? c lkdis: cou nte r cloc k disabl e command 0 = n o e ffect. 1 = disa bl e s th e cl oc k. ? swtrg : software trigger command 0 = n o e ffect. 1 = a so ft war e tr igge r is perfo rmed: t h e co unte r is rese t an d th e cloc k is s tarted. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? s wtrg clkdis clken 32058k avr32-01/12 658 at32uc3a 31.7.4 tc c hanne l mo de register: ca pture mode regis te r nam e: cmr acces s type: read/write ? t cclks: cloc k selection ? cl ki : cloc k inv er t 0 = counter is incremente d o n rising edg e o f the clock. 1 = co unter is incr emented o n falling edge of the clo ck. ? burst: burs t signa l selection ? ldbsto p: counter cloc k stopp ed with rb loading 0 = cou nter cl ock is not stopped w he n r b loadin g o ccurs. 1 = c ounter cloc k is stopped when rb l oading occurs. ? ldbd is: counter cloc k disabl e with rb loading 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wa ve = 0 cpctrg ? ? ? abetrg etrgedg 7 6 5 4 3 2 1 0 l dbdis l dbstop burst cl ki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 1 0 1 xc0 1 1 0 xc1 1 1 1 xc2 burst 0 0 the clo c k is not gated by an externa l signal. 0 1 xc0 is ande d with the selected clo ck. 1 0 xc1 is ande d with the selected clo ck. 1 1 xc2 is ande d with the selected clo ck. 32058k avr32-01/12 659 at32uc3a 0 = cou nter cl ock is not d isabled whe n rb loa din g occ urs. 1 = c ounter cloc k is disable d when rb loa din g occurs. ? etrg e dg: e xterna l tr igge r e dg e se l ection ? abetr g: tioa or tiob extern al trigger selection 0 = ti ob is use d a s an extern al trigger. 1 = ti oa is use d a s an extern al trigger. ? c pctr g: rc compare trigge r enable 0 = rc c o mp ar e h a s no eff ect o n th e cou nt e r and it s clock. 1 = rc c ompare resets th e counte r an d starts t he counter clock. ? wa ve 0 = c aptur e mo de is ena ble d. 1 = c aptur e mo de is disabled (wave for m mo de is enabled ). ? l dra: ra loa ding selection ? l drb: rb loa ding selection etrgedg edge 0 0 none 0 1 risi ng edge 1 0 falli n g edge 1 1 ea ch edge ldra edge 0 0 none 0 1 rising ed ge of tioa 1 0 falli ng edg e of tioa 1 1 ea ch edg e of tioa ldrb edge 0 0 none 0 1 risi ng edg e of tioa 1 0 fallin g edge of ti oa 1 1 eac h edge of ti oa 32058k avr32-01/12 660 at32uc3a 31.7.5 tc c hanne l mo de register: wavefo rm mode regis te r nam e: cmr acces s type: read/write ? t cc lks: clo c k select i on ? cl ki : cloc k inv er t 0 = counter is incremente d o n rising edg e o f the clock. 1 = co unter is incr emented o n falling edge of the clo ck. ? burst: burs t signa l selection ? c pcst op: co unter clock stoppe d with rc comp are 0 = c ounter cloc k is not stopped wh en counte r reache s rc. 1 = c ounter cloc k is stopped when counter reache s rc. ? c pcdis: counter clock disable with rc comp are 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave = 1 wavsel enetrg eevt eevtedg 7 6 5 4 3 2 1 0 cpcdis cpcstop burst clki tcclks tcclks cloc k selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 1 0 1 xc0 1 1 0 xc1 1 1 1 xc2 burst 0 0 the clo c k is not gated by an externa l signal. 0 1 xc0 is ande d with the selected clo ck. 1 0 xc1 is ande d with the selected clo ck. 1 1 xc2 is ande d with the selected clo ck. 32058k avr32-01/12 661 at32uc3a 0 = cou nter cl ock is not d isabled when counter reaches rc. 1 = counter clock is di sabled when counte r reaches rc. ? eevtedg: external ev ent edge selection ? eevt : external event selection note: 1. if tiob is chos en as the external even t sig nal, it is config ured as an i nput a nd no lo nge r generates waveforms a nd subse- quently no irqs. ? e netrg: extern al event trigge r enable 0 = th e external even t has no effect on the counter an d it s clock. in this case, the selected external event only controls the ti oa output. 1 = th e extern al event resets the counte r and star ts th e counter clock. ? wa vsel: wa vefo rm selection ? wa ve = 1 0 = w avefor m mode is disa bled (captur e mod e is enabled). 1 = w avefor m mode is e nabled. eevtedg e d ge 0 0 none 0 1 r i s i n g ed ge 1 0 f all i ng edge 1 1 eac h edge eevt signal selected as exter na l e vent tio b d ir ec tion 0 0 tiob input (1) 0 1 xc0 output 1 0 xc1 output 1 1 xc2 output wavsel effect 0 0 up mode wi thout automatic trigge r on rc compare 1 0 up m ode with automa tic trig ger on rc compare 0 1 u pdo wn mode w it ho ut a ut o m a t ic tri gg e r on rc c ompare 1 1 updo wn mode with automati c trig ger on rc compare 32058k avr32-01/12 662 at32uc3a ? acpa: ra compare effe ct on tioa ? a cpc: r c compa r e ef f ect o n t ioa ? ae evt : e x ternal event e ff ect o n t i oa ? as wtr g: software trigge r effe ct on tioa ? bcp b: rb co mpare effe ct on tiob acpa effect 0 0 none 0 1 set 1 0 clear 1 1 toggle acpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aeevt ef fect 0 0 none 0 1 set 1 0 clear 1 1 toggle aswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpb effect 0 0 none 32058k avr32-01/12 663 at32uc3a ? bcp c: rc co mpare effe ct on tiob ? beevt: ex ternal event eff ect on tiob ? bswtr g: software trigge r effe ct on tiob 0 1 set 1 0 clear 1 1 toggle bcpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle beevt ef fect 0 0 none 0 1 set 1 0 clear 1 1 toggle bswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpb effect 32058k avr32-01/12 664 at32uc3a 31.7.6 tc counter va lue register regis te r nam e: cv acces s type: read-only ? c v: counter value cv co nt ains th e counte r valu e in re al time. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 cv 7 6 5 4 3 2 1 0 cv 32058k avr32-01/12 665 at32uc3a 31.7.7 tc r egist er a regis te r nam e: ra acces s type: read-only if wave = 0, read/write if wave = 1 ? ra: r egist er a ra co nt ains th e register a valu e in re al time. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ra 7 6 5 4 3 2 1 0 ra 32058k avr32-01/12 666 at32uc3a 31.7.8 tc r egist er b regis te r nam e: rb acces s type: read-only if wave = 0, read/write if wave = 1 ? rb: r egist er b rb co nt ains th e register b valu e in re al time. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rb 7 6 5 4 3 2 1 0 rb 32058k avr32-01/12 667 at32uc3a 31.7.9 tc r egist er c regis te r nam e: rc acces s type: read/write ? rc: r egist er c rc contains the re gister c va lue in real time. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rc 7 6 5 4 3 2 1 0 rc 32058k avr32-01/12 668 at32uc3a 31.7.10 t c st atus register regis te r nam e: sr acces s type: read-only note: re ading the status re gister will also cl ear th e interrupt flag for the correspondi ng interrupts. ? c ovfs : count er overflow status 0 = n o counte r over flo w has occurre d since th e last rea d of th e status register. 1 = a co unte r overfl ow ha s occurred since th e last read o f the stat us register. ? lov rs: loa d ove rrun status 0 = loa d overru n ha s no t occ urre d s ince the last rea d o f th e status registe r o r wa ve = 1 . 1 = ra o r rb h a ve bee n l oade d a t leas t t wi ce without any rea d o f th e cor re spondin g register since th e last read of th e sta- tus registe r, if wa ve = 0. ? c pa s: ra compare status 0 = ra com par e has no t occurred since th e last rea d o f the stat us registe r or wave = 0. 1 = r a compare has occurred since the last read of the status re gister, if wave = 1. ? cpbs: rb co mpare status 0 = rb com par e has no t occurred since th e last rea d o f the stat us registe r or wave = 0. 1 = r b compare has occurred since the last read of the status re gister, if wave = 1. ? cpcs: rc co mpare status 0 = rc c ompar e ha s not occurred since the la st rea d of the stat us register. 1 = rc c ompar e ha s occurred since the last read of t he stat us register. ? l dras: ra loading status 0 = ra loa d ha s n ot occ urred s ince the last read o f the status register or wave = 1. 1 = r a load has occurred since the last re ad of the status register, if w ave = 0. ? l drbs: rb loading status 0 = rb loa d ha s n ot occ urred s ince the last read o f the status register or wave = 1. 1 = r b load has occurred since the last re ad of the status register, if w ave = 0. ? etrgs: external trigg e r status 0 = ex ternal trigge r ha s not occurre d since th e las t rea d o f th e status register. 1 = ex ternal trigge r ha s occurred since th e last read o f the stat us register. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? mtiob mtioa clksta 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs 32058k avr32-01/12 669 at32uc3a ? c lkst a: clock enab ling status 0 = cl oc k is disabled. 1 = clo ck is e nab le d. ? mtioa: tioa mirror 0 = tioa is low. if wave = 0, this mea n s that tioa pin is low. if wave = 1, t hi s m ean s t ha t ti oa i s d riv en l o w. 1 = tioa is high. if wave = 0, this mea n s that tioa pin is high. if wave = 1, this means that t i oa is driven high. ? mtiob : ti ob mirror 0 = tiob is low. if wave = 0, this mea n s that tiob pin is low. if wave = 1, t hi s m ean s t ha t ti ob i s d riv en l o w. 1 = tiob is high. if wave = 0, this mea n s that tiob pin is high. if wave = 1, this means that t i ob is driven high. 32058k avr32-01/12 670 at32uc3a 31.7.11 tc interrupt enable register regis te r nam e: ier acces s type: write-only note: re ading the status re gister will also cl ear th e interrupt flag for the correspondi ng interrupts. ? co vfs : c o unt er overflo w 0 = n o e ffect. 1 = e nables the counter overflow interrupt. ? l o vrs : l o a d o ve rrun 0 = n o e ffect. 1 = e nables the loa d overru n interrupt. ? cpa s: ra comp a re 0 = n o e ffect. 1 = e nables the ra com pare interrupt. ? cpbs : rb compa r e 0 = n o e ffect. 1 = e nables the rb com pare interrupt. ? cpcs : rc compa r e 0 = n o e ffect. 1 = enable s the rc compar e interrupt. ? l dras: ra loading 0 = n o e ffect. 1 = e nab les the ra l o ad inte rru pt. ? l drbs: rb loading 0 = n o e ffect. 1 = e nab les the rb l o ad inte rru pt. ? etrgs: external trigger 0 = n o e ffect. 1 = enable s the extern al trigge r interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs 32058k avr32-01/12 671 at32uc3a 31.7.12 tc interrupt disabl e register regis te r nam e: idr acces s type: write-only note: re ading the status re gister will also cl ear th e interrupt flag for the correspondi ng interrupts. ? co vfs : c o unt er overflo w 0 = n o e ffect. 1 = disa bl es th e counte r overflow interrupt. ? l o vrs : l o a d o ve rrun 0 = n o e ffect. 1 = di sables the load overru n interrupt (if wave = 0). ? cpa s: ra comp a re 0 = n o e ffect. 1 = disa bl es th e ra compa r e i nter rup t (i f wave = 1). ? cpbs : rb compa r e 0 = n o e ffect. 1 = disa bl es th e rb compa r e i nter rup t (i f wave = 1). ? cpcs : rc compa r e 0 = n o e ffect. 1 = disa bl es th e rc compar e interrupt. ? l dras: ra loading 0 = n o e ffect. 1 = di sables the r a load interrupt (if w ave = 0). ? l drbs: rb loading 0 = n o e ffect. 1 = di sables the r b load interrupt (if w ave = 0). ? etrgs: external trigger 0 = n o e ffect. 1 = disa bl es th e exte rna l trigger int err upt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs 32058k avr32-01/12 672 at32uc3a 31.7.13 tc inte rrupt mask register regis te r nam e: imr acces s type: read-only note: re ading the status re gister will also cl ear th e interrupt flag for the correspondi ng interrupts. ? co vfs : c o unt er overflo w 0 = th e counte r overflow interrup t is disabled. 1 = th e counte r overflow interrup t is enabled. ? l o vrs : l o a d o ve rrun 0 = th e l oad overrun interrupt is disabled. 1 = th e l oa d over ru n int err upt is ena ble d. ? cpa s: ra comp a re 0 = th e ra compar e interrupt is disabled. 1 = th e ra c o mpar e inte rru pt is e nab led. ? cpbs : rb compa r e 0 = th e rb compar e interrupt is disabled. 1 = th e rb c o mpar e inte rru pt is e nab led. ? cpcs : rc compa r e 0 = th e rc co mpare interrupt is disa bled. 1 = th e rc co mpare interrupt is e nabled. ? l dras: ra loading 0 = th e l oad ra i nterrup t is disabled. 1 = th e l oa d ra i nt e rrup t i s enabl ed. ? l drbs: rb loading 0 = th e l oad rb i nterrup t is disabled. 1 = th e l oa d rb i nt e rrup t i s enabl ed. ? etrgs: external trigger 0 = th e extern al trigger interrupt is disa bled. 1 = th e extern al trigger interrupt is e nabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs 32058k avr32-01/12 673 at32uc3a 32. pulse width modula t ion control ler (pwm) re v: 1.3.0.1 32.1 features ? 7 channels ? on e 20-bit counter pe r channel ? common clo ck generator p rovidin g thir teen diff erent clocks ? a modul o n coun ter providin g eleven clocks ? two independent linear dividers workin g on modulo n c oun ter outputs ? independen t channels ? i ndependent enab le disable command fo r each channel ? i ndependent cloc k selection fo r each channel ? independent period an d du ty cycle fo r each channel ? doubl e buffering of period or d u ty cycle for each channel ? p rogrammabl e selection of the output wa vefo r m p o larity for ea c h c h ann el ? programmabl e center o r left aligne d output waveform fo r each channel 32.2 description the pwm macrocell c o ntrols several cha nnels independent ly. each channe l co ntrols one square output waveform . characterist ics o f the output wavefo rm such as pe riod, duty-cycle and polarity ar e configurable throu gh the user interface. each channe l selects and uses one o f the clocks pr ovided by the clock gene rator. th e cloc k genera tor provides sever al clocks resulting from th e division of th e pwm macroce ll mast er clock. all pw m macrocell ac cesses ar e made throug h register s mappe d on th e peripher al bus. channe ls can be synchronized , t o generat e n on overlapped waveforms. all ch anne ls integrate a double buf fer in g syste m in orde r t o prevent an unexpecte d output wavefo rm while modifying the period or the duty-cycle. 32058k avr32-01/12 674 at32uc3a 32.3 block diagram figur e 32-1. pulse wid t h modulatio n controller bl ock diagram 32.4 i /o lines description each ch anne l outp ut s on e wavefo r m on on e extern al i/ o lin e. pwm controller peripheral bus pwmx pwmx pwmx channel update duty cycle counter pwm0 channel pio interrupt controller power manager mck clock generator pb interface interrupt generator clock selector period comparator update duty cycle counter clock selector period comparator pwm0 pwm0 tabl e 32-1. i/ o line description name description type pwmx pwm waveform output fo r channe l x output 32058k avr32-01/12 675 at32uc3a 32.5 p roduct dependencies 32.5.1 i / o lines the pi ns used for interfacing t he pwm may be multiplexe d wit h pi o lines. the programm er must first program t he pio controller to assign t he desire d p wm p ins to the ir periphera l fu ncti on. if i/o line s of th e p wm a re not us e d b y the app l icati on, the y can be used for o t her p u r pose s b y t he pio co ntroller. not all pw m o utpu ts may b e enable d. if an applica tion requ ires on ly four chan nels, then only four pio lines w ill be assi gned to pwm outputs. 32.5.2 deb ug operation th e pwm clock is r unn ing during debu g operation. 32.5. 3 po wer mana gement the pwm clock is gen erat ed by the power manager. befor e usin g the pwm, t he programmer must ensure tha t t h e pw m cloc k i s en abled in the po w er m a n ager . ho wev er , i f t he ap p lication do es no t requ ire pw m operations , the pwm clo ck ca n be stoppe d when not neede d an d be restarted later. in thi s ca se, the pw m will resu me its operations where it left off. in t he pwm d escription, master clock (mck) is t he clock of the perip heral bus to which the pwm is con nected. 32.5.4 interrupt sources t h e pw m interrupt line is c o nnecte d to the interrupt controller . usin g th e pwm interrup t requires t he interrupt controller t o b e programmed first. 32058k avr32-01/12 676 at32uc3a 32.6 functional description th e pwm macroce ll is primar ily compose d of a clock ge nerator modu le and 7 c hannels. ? clocked by th e syst em clock, mck, th e clock generator modu le prov ides 13 clocks. ? e ach channe l can independent ly choo se one o f the cloc k generato r outputs. ? each ch anne l gene rate s a n ou tpu t wavefor m wit h attribu te s th at can b e defin ed ind epen de ntly fo r eac h channe l thr o ug h th e u se r interface register s. 32.6.1 pwm clock generator figur e 32-2. function al view of the clock generator blo ck diagram caution : be fore usin g th e pwm macroce ll, th e programmer must ensure that th e pwm cloc k in t he powe r manage r is enabled. th e pwm macr ocell master clock, mck, is divid e d in th e cloc k ge ner ato r mo dul e to provide dif- fere nt clocks avai lable for all channe ls. each chan nel can independe ntly select one o f the divid ed clocks. modulo n counter mck mck/2 mck/4 mck/16 mck/32 mck/64 mck/8 divider a clka diva pwm_mr mck mck/128 mck/256 mck/512 mck/1024 prea divider b clkb divb pwm_mr preb 32058k avr32-01/12 677 at32uc3a th e clo c k ge nera to r is divid ed in three blocks: ? a modulo n counter whi ch p rovid es 1 1 clocks : f mck , f mck /2, f mck /4, f mck /8, f mck /16, f mck /32, f mck /64, f mck /12 8, f mck /256, f mck /512, f mck /10 2 4 ? two linear dividers (1, 1/2, 1/3 , ... 1/255) that provide two separat e clocks: clka and c lkb each linear divider ca n independentl y divide one o f the clocks o f the modulo n counter. the select ion o f t he clock to be divided is made a c cording t o th e prea (preb) fi eld o f t he pwm mo de registe r (mr). t he result ing clock clka (clk b) is t he clock selecte d divided by d iva (divb) field valu e in t he pwm mode register (mr). afte r a reset o f t he pwm controller, di va (divb) an d prea (preb) in th e pwm mode register ar e se t to 0. this implie s that after res et clka (clkb ) are turned off. at reset, a ll clocks provided by th e modu lo n counte r ar e turn ed off except clock ?clk?. th is situa- tion is also tr u e when t he pwm mast er cl ock is t u rned of f through t he power management controller. 32.6.2 pwm channel 32.6.2 .1 bloc k diagram figur e 32-3. functional view of th e channe l bloc k diagram each o f t he 7 channe ls is composed o f three blocks: ? a cloc k sele ctor which sele cts on e o f th e cloc ks pro vid e d b y th e clo c k g en erato r d esc ribed in section 32.6. 1 ?pwm clock g enerator ? o n pa ge 676. ? a n interna l c o unte r cl ock ed b y th e outpu t o f t h e cloc k se lector . this inter na l counter is incremente d o r decrem en te d accordin g t o th e channe l con figuratio n and com parat or s e ven ts. the si ze o f th e inte rn a l coun te r is 2 0 bits. ? a comparator used to generate event s according to t he intern al counter value . it also computes t he pwmx output waveform according to t he configuration. 32.6 .2.2 wave for m properties th e different properties o f output waveform s are: ? the internal clock selection. th e internal channel counte r is clocked by on e of the clocks provided by th e clock generator described in t h e previous section. this chan nel parameter is define d in the c pre fiel d o f th e cm rx register . t h is fiel d is r e se t at 0. ? the wavefo rm period. th is channe l parameter is define d in th e cprd fiel d of th e cprdx reg ister. comparator pwmx output waveform internal counter clock selector inputs from clock generator inputs from peripheral bus channel 32058k avr32-01/12 678 at32uc3a - if t he wavefor m is left aligned , the n th e output wavefor m perio d depend s on the counter sour ce clock a nd ca n be calculated: b y usin g th e master clo ck (m ck ) d ivided by a n x giv e n prescaler v alue (w ith x being 1, 2, 4, 8, 16, 32 , 64, 128, 256, 512, or 1024), the resulting pe riod form ula will be: by usin g a master cloc k d ivid ed by o ne of bot h diva or d i vb divide r, th e fo rm ula become s, respective ly: or if the waveform is ce nter aligne d then th e output waveform perio d depends o n th e counter sour ce clock a nd ca n be calculated: b y usin g th e master clo ck (m ck ) d ivided by a n x giv e n prescaler v alue (w ith x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 102 4 ). the resulting pe riod form ula will be: by usin g a ma ster cloc k divided by o ne of bot h diva or d i vb divide r, th e fo rm ula become s, respect ive ly: or ? the wavefo rm duty cycle. th is channe l parameter is defined in th e cdty field of t he cdtyx re g is te r. if the waveform is le ft aligne d then: if the waveform is c ente r aligned , then: ? the wavef o rm po larity . a t th e beginning of th e period, th e signa l ca n be at high or lo w level. t his property i s de fined in th e cpo l fie l d o f t he cmrx register. by defaul t th e sig nal starts by a l o w level. ? the waveform alignment . th e output waveform ca n be left or center aligned. center aligned wavefor ms ca n be used to generat e non overlapped waveforms. this property is define d in the calg fiel d of t he cmrx register. th e default mode is l eft aligned. x cprd ( ) mck ------------------------------- crpd diva ( ) mck ------------------------------------------ crpd divab ( ) mck ---------------------------------------------- 2 x cprd ( ) mck --------------------------------- --------- 2 cprd diva ( ) mck -------------------------------------------------- --- 2 cprd divb ( ) mck ------------------------------------------------- ---- duty cycl e period 1 fchannel_x_clock cdty ? ( ) period ---------------------------------------------------------------------------------------------------- ----- = duty cycle period 2 ? ( ) 1 fchannel_x_clock cdty ? ( ) ) period 2 ? ( ) 32058k avr32-01/12 679 at32uc3a figur e 32-4. non overlappe d center aligne d waveforms note: 1 . see fi gure 32 -5 on pag e 680 fo r a detai led descriptio n of center al igned waveforms. when center aligned, the internal channel coun t er increa ses up to cprd and.decreases down t o 0. this ends th e period. when le ft aligned, t he internal chann el counter increases up t o cprd and is reset. this ends t he period. thus, for t he sa me cprd value , the period f or a center aligne d chan nel is twice t he period for a left aligned channel. waveform s ar e fixe d at 0 when: ? cdt y = cprd and cpol = 0 ? cdty = 0 and cpol = 1 waveform s ar e fixe d at 1 (onc e th e channel is enabled) when: ? cdty = 0 and cpol = 0 ? cdt y = cprd and cpol = 1 th e waveform polari ty must be se t before enabling the channel. this imme diat ely affects the channel output level. chan ges on channel polari ty are not take n into account while t he channel is e nabled. pwm0 pwm1 period no overlap 32058k avr32-01/12 680 at32uc3a figur e 32-5. waveform properties pwm_mckx chidx(pwm_sr) center aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) left aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) calg(pwm_cmrx) = 0 calg(pwm_cmrx) = 1 period period chidx(pwm_ena) chidx(pwm_dis) 32058k avr32-01/12 681 at32uc3a 32.6.3 pwm controller operations 32.6.3.1 initialization befo re en abling th e output channel, t his chann el must have be e n configur ed by the software application: ? conf igurat io n o f th e cl oc k gen erato r if di va a nd divb ar e r equ ired ? selection o f the clock fo r ea ch channel (c pre fiel d in t he cmrx register) ? conf igurat io n o f th e wavefor m align men t fo r each chann el (cal g fie l d in t h e cmrx register) ? configuratio n o f the period fo r ea ch chann el (cprd in the cprdx r egister). writing in cprdx register is p ossib le while t he chann el is disabled. after validation o f the channel , the user must use cupdx r egister to update cprdx as explained below. ? c onfigu rat ion o f the d u ty cy c l e fo r each channel (cdty in the cdty x registe r). w r itin g in cdtyx register is po ssib le while the channel is disabled . after validatio n of th e channe l, the user mu st use cupdx r egister to update cdtyx as explaine d below. ? configuratio n o f th e output waveform polarity fo r ea ch channel (cpo l in t he cmrx register) ? enabl e interrupts (writing chidx in the ier register) ? enable th e pwm channel (writi ng chid x in the ena r egister) it is possible to synch r onize diff erent channels b y enab l ing the m a t t he sam e tim e b y mean s of writing simultaneously seve ral chidx bits in th e ena register. in such a situatio n, al l ch a nnels may h ave th e sam e clock se lecto r configur ation an d the sam e period specified. 32.6.3.2 s ou rce clo ck se lection c ri t eria t he larg e number of sour ce clocks ca n make selection difficult. th e relationsh ip betwee n the valu e in th e period register (cprdx) an d th e duty cycle r egister (cdtyx) can help the user in choosing . the event number writte n in the period register give s the pw m accuracy . th e duty cycle qua ntu m cannot be lowe r than 1/cprdx value. t he high er the value of cprdx, the greater th e pw m accuracy. for example, i f t he user sets 15 (i n decimal) in cprdx, t he user is a b le to set a value between 1 up to 14 in cdtyx r egister . th e resultin g duty cycle qu antum cannot be lower than 1/ 15 o f the pwm pe riod. 32.6.3.3 changing the duty cycl e or the period it is possible to modulate th e output waveform du ty cycle or period. to preven t unexpe cte d output wavefo rm , t he user must use the updat e register (pwm_cupdx) to change waveform pa ramet ers while the channel is st ill enabled. the user can writ e a new peri od valu e or duty cycle value in the update r egi ster (cupdx). this regist er holds the new valu e until the end of the current cycle and u p dates the value for t he next cyc le. depending on t he cpd fiel d in t he cmrx register, cupdx ei th er updat es cprdx or cdtyx. note that even if the update register is used , the perio d must not be smaller than th e duty cycle. 32058k avr32-01/12 682 at32uc3a figur e 32-6. synchronized period or duty cycle update to preven t overwriting t he cupdx by software, t he user can use status events in order to syn- chronize his so ftware. two method s are possible. in both, the user must enable the dedicated interrupt in ier at p wm controller level. the first method (polling method) consists of reading the r elevant stat us bit in isr registe r accordin g to th e enabled channel(s). see figure 32-7. th e second metho d uses a n interrup t service rout ine associated with t he pwm channel. note: reading the isr r egister automati cal ly clears ch idx fl ag s. figur e 32-7. polling method note: polarit y and alignmen t ca n be modifie d on ly when the channe l is disabled. pwm_cupdx value pwm_cprdx pwm_cdtyx end of cycle pwm_cmrx. cpd user's writing 1 0 writing in pwm_cupdx the last write has been taken into account chidx = 1 writing in cpd field update of the period or duty cycle pwm_isr read acknowledgement and clear previous register state yes 32058k avr32-01/12 683 at32uc3a 32.6.3.4 interrupts d ep endi ng o n the inte rr up t ma sk in th e im r register, a n interrup t is ge nerate d at th e en d o f th e corresponding channel period. th e interrupt rema ins active unt il a read operation in the isr r eg- ist e r occur s. a ch a nnel interrupt is e n abled by settin g the corresponding bit in th e ie r register. a chan nel interrupt is disable d by setting the corresponding bit in the idr register. 32058k avr32-01/12 684 at32uc3a 32.7 pulse width modulation (pwm ) contro ller user interface 32.7.1 register mapping tabl e 32-2. pwm co ntroller regist ers offset register name access peripheral reset value 0x00 pw m mode register mr read/write 0 0x04 pw m enable register ena write-only - 0x08 pw m disabl e register dis write-only - 0x0c pw m status register sr read-only 0 0x10 pw m interrup t enable register ier write-only - 0x14 pw m interrup t disab le register idr write-only - 0x18 pw m interrup t mask register imr read-only 0 0x1c pw m interrup t status register isr read-only 0 0x4c - 0xf 8 reserved ? ? ? 0x4c - 0xfc reserved ? ? ? 0x10 0 - 0x1fc reserved 0x200 chan nel 0 mode register cmr0 read/write 0x0 0x204 chan nel 0 duty cycle register cdty0 read/write 0x0 0x208 chan nel 0 period register cprd0 read/write 0x0 0x20c chan nel 0 counter register ccnt0 read-only 0x0 0x210 chan nel 0 upda te register cupd0 write-only - ... reserved 0x220 chan nel 1 mode register cmr1 read/write 0x0 0x224 chan nel 1 duty cycle register cdty1 read/write 0x0 0x228 chan nel 1 period register cprd1 read/write 0x0 0x22c chan nel 1 counter register ccnt1 read-only 0x0 0x230 chan nel 1 upda te register cupd1 write-only - ... ... ... ... ... 32058k avr32-01/12 685 at32uc3a 32.7.2 pwm mode reg ister regis te r nam e: mr acces s type: read/write ? diva , divb: cl ka, clkb divide factor ? prea, preb 31 30 29 28 27 26 25 24 ? ? ? ? preb 23 22 21 20 19 18 17 16 divb 15 14 13 12 11 10 9 8 ? ? ? ? prea 7 6 5 4 3 2 1 0 diva diva , divb clka, clkb 0 c lka, clkb cloc k is tur ned off 1 c lka, clkb cloc k is clock selected b y prea, preb 2-255 c lka, clkb cloc k is clock selected b y prea, pr eb divided b y div a, divb fa ctor. prea, preb divider input clo ck 0 0 0 0 mck. 0 0 0 1 mck/2 0 0 1 0 mck/4 0 0 1 1 mck/8 0 1 0 0 mck/16 0 1 0 1 mck/32 0 1 1 0 mck/64 0 1 1 1 mck/128 1 0 0 0 mck/256 1 0 0 1 mck/512 1 0 1 0 mck/1024 other reserved 32058k avr32-01/12 686 at32uc3a 32.7.3 pwm ena b le register regis te r nam e: ena acces s type: write-only ? chidx: channel id 0 = n o e ffect. 1 = e nab le pw m output fo r channe l x. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? chid6 chid5 chid4 chid3 chid2 chid1 chid0 32058k avr32-01/12 687 at32uc3a 32.7.4 pwm disabl e register regis te r nam e: dis acces s type: write-only ? chidx: channel id 0 = n o e ffect. 1 = disable pwm output fo r channel x. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? chid6 chid5 chid4 chid3 chid2 chid1 chid0 32058k avr32-01/12 688 at32uc3a 32.7.5 pwm s t atus register regis te r nam e: sr acces s type: read-only ? chidx: channel id 0 = pwm output fo r channe l x is disabled. 1 = pwm output fo r channe l x is enabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? chid6 chid5 chid4 chid3 chid2 chid1 chid0 32058k avr32-01/12 689 at32uc3a 32.7.6 pwm i nterrupt enab le register regis te r nam e: ier acces s type: write-only ? chidx: channel i d. 0 = n o e ffect. 1 = enable interrup t fo r pw m ch ann el x. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? chid6 chid5 chid4 chid3 chid2 chid1 chid0 32058k avr32-01/12 690 at32uc3a 32.7.7 pwm interrupt disabl e register regis te r nam e: idr acces s type: write-only ? chidx: channel i d. 0 = n o e ffect. 1 = disa bl e int e rrup t fo r p w m c hanne l x. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? chid6 chid5 chid4 chid3 chid2 chid1 chid0 32058k avr32-01/12 691 at32uc3a 32.7.8 pwm i nterrup t mask register regis te r nam e: imr acces s type: read-only ? chidx: channel i d. 0 = inte rrupt fo r p w m channel x i s d isab l e d. 1 = inte rrupt fo r p wm c hannel x i s ena ble d. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? chid6 chid5 chid4 chid3 chid2 chid1 chid0 32058k avr32-01/12 692 at32uc3a 32.7.9 pwm i nter rupt status register regis te r nam e: isr acces s type: read-only ? chidx: channel id 0 = n o n ew c hann el perio d since th e last read o f the isr register. 1 = a t least one new c han nel period since t h e last read o f th e isr register. note: reading isr automatically clears chi dx flags. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? chid6 chid5 chid4 chid3 chid2 chid1 chid0 32058k avr32-01/12 693 at32uc3a 32.7.10 p wm channe l mo de register regis te r nam e: cmrx acces s type: read/write ? cpre: ch an nel pre-scaler ? ca l g: channe l al ignment 0 = th e p eri od is left aligned. 1 = th e p eri od is center aligned. ? cpol: ch annel polarity 0 = th e o utput waveform starts at a low level. 1 = th e o utput waveform starts at a high level. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? cpd cpol calg 7 6 5 4 3 2 1 0 ? ? ? ? cpre cpre channe l pre-scaler 0 0 0 0 mck 0 0 0 1 mck/2 0 0 1 0 mck/4 0 0 1 1 mck/8 0 1 0 0 mck/16 0 1 0 1 mck/32 0 1 1 0 mck/64 0 1 1 1 mck/128 1 0 0 0 mck/256 1 0 0 1 mck/512 1 0 1 0 mck/1024 1 0 1 1 clka 1 1 0 0 clkb oth er r ese rved 32058k avr32-01/12 694 at32uc3a ? cpd: ch an nel update pe riod 0 = writin g to t h e c u pd x wi ll m odi fy the du t y cy cle at the next period st art event. 1 = wr iting to the cu pdx will modif y the period at the ne xt period start event. 32058k avr32-01/12 695 at32uc3a 32.7.11 pwm channel duty cycl e regis ter regis te r nam e: cdty x acces s type: read/write on ly th e first 20 bits (internal chan nel counte r size ) ar e significant. ? cdty: chan nel duty cycl e defines the waveform du ty cycle. this valu e mu st b e define d between 0 a n d cprd (cprx). 31 30 29 28 27 26 25 24 cdty 23 22 21 20 19 18 17 16 cdty 15 14 13 12 11 10 9 8 cdty 7 6 5 4 3 2 1 0 cdty 32058k avr32-01/12 696 at32uc3a 32.7.12 pwm channel peri od register regis te r nam e: cprdx acces s type: read/write on ly th e first 20 bits (internal chan nel counte r size ) ar e significant. ? cprd: ch annel period if the wav eform is left- align ed, then th e outpu t waveform perio d depends on the counter source clock a nd ca n be calculated: ? b y using the master cloc k (mck) divided by an x gi ven prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the re sultin g period form ula will be: ? by usin g a master cloc k divided by o ne of both diva or di vb divider, the formula becomes, respectively: or i f t he w a vef orm is c e nter- align ed , the n t h e ou tp ut w a vef orm p erio d dep ends o n th e c o unte r sou rc e cl o c k an d c an be calculated: ? b y using the master cloc k (mck) divided by an x gi ven prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the re sultin g period form ula will be: ? by usin g a master cloc k divided by o ne of both diva or di vb divider, the formula becomes, respectively: or 31 30 29 28 27 26 25 24 cprd 23 22 21 20 19 18 17 16 cprd 15 14 13 12 11 10 9 8 cprd 7 6 5 4 3 2 1 0 cprd x cprd ( ) mck ------------------------------- crpd diva ( ) mck ------------------------------------------ crpd divab ( ) mck ---------------------------------------------- 2 x cprd ( ) mck --------------------------------- --------- 2 cprd diva ( ) mck -------------------------------------------------- --- 2 cprd divb ( ) mck ------------------------------------------------- ---- 32058k avr32-01/12 697 at32uc3a 32.7.13 p wm channe l counter register regis te r nam e: ccntx acces s type: read-only ? cnt : channe l counte r register inter n al c oun te r value . t his r eg i ste r i s r eset when: ? t he channe l is enable d (writing chid x in t he ena register). ? the counte r reache s cprd valu e define d in th e cp rdx register if the waveform is left aligned. 31 30 29 28 27 26 25 24 cnt 23 22 21 20 19 18 17 16 cnt 15 14 13 12 11 10 9 8 cnt 7 6 5 4 3 2 1 0 cnt 32058k avr32-01/12 698 at32uc3a 32.7.14 p wm channe l update register regis te r nam e: cupdx acces s type: write-only th is registe r acts as a double buff er fo r the peri od or the duty cycle. th is prevents an unexpected wavefo rm when modify- ing the wa veform period or duty-cycle. on ly th e first 20 bits (internal chan nel counte r size) ar e significant. 31 30 29 28 27 26 25 24 cupd 23 22 21 20 19 18 17 16 cupd 15 14 13 12 11 10 9 8 cupd 7 6 5 4 3 2 1 0 cupd cpd (cmrx register) 0 the duty-cycle (cdty in the cdtyx regi st er) is updated with the cupd value at the beginning of th e ne xt period. 1 the period (cprd in the cpr d x re gister) is update d with the cupd value at the b eginning of th e ne xt period. 32058k avr32-01/12 699 at32uc3a 33. a nalog-to-digital converter (adc) re v: 1.0.0.3 33.1 features ? integrated multiplexe r offering up to eight independen t analog inputs ? ind iv idual en ab l e an d di sa bl e of e ac h cha nn el ? hard ware or software trigger ? external trigge r pin ?time r counter output s (corresponding tioa trigger) ? pdc s upport ? poss ibility of adc ti mings configuration ? sleep mode and c onve r si on se que ncer ? automatic wake up on trigge r and back to s lee p mode after conver sions of all enabled channels 33.2 overvi ew th e adc is base d on a su ccessive approximatio n register (sar) 10-b it a nalog-to-di git al con- vert er (adc). it also in t egrates an adc_nb_channels- to-1 analog multiplexer, making possibl e the analog-to -digital conversion s of adc_nb_channel s analog lines. the c on ve r- sion s extend fr om 0v to advref . th e adc supports an 8-bit or 10-bit resolution mode, and conversion result s are reported in a common registe r for all channels, as we ll as in a channel-dedicated registe r. software trigger, ext ernal trigger on rising edg e of the tr i gger pi n or internal triggers f rom timer counter out- put( s) ar e configurable. the adc also integra tes a sleep m ode and a conversion sequencer and conne cts with a pdc channe l. t h ese fea tur es re duce b ot h powe r consumpt ion an d processor intervention. finally, th e user can configure adc timings, suc h as sta rtu p tim e a nd sa mp le & ho ld tim e. 32058k avr32-01/12 700 at32uc3a 33.3 block diagram figur e 33-1. analog-to-digital converte r block diagram 33.4 i/o lines description 33.5 p roduct dependencies 33.5.1 gpio th e pin tri gger may be shared with other periphera l functions through the pio controller. in this case, the pio controller should be s et acco rdingly to assign the pin tri gger to the adc function. tabl e 33-1. adc pins description pin name description vddana analog p owe r supply advref reference voltage ad0 - ad [ adc_nb_channels-1] a n alog i np ut ch an nels trigger external trigger dedicated analog inputs analog inputs multiplexed with i/o lines gnd ad- ad- ad- ad- ad- ad- a dv ref vddana trigger trigger selection adc control logic adc interrupt intc hsb pdc peripheral bridge pb user interface successive approximation register analog-to-digital converter p io timer counter channels 32058k avr32-01/12 701 at32uc3a 33.5. 2 analog inpu ts the analog inpu t pins can be multiplexed with pi o lin es. in th is case , the assignment of th e adc inpu t is autom atically do ne as soo n as th e correspondin g chann el is enable d by writing the cher r egister . by default, after reset, the pi o lin e is configured as input with it s pull-u p enabled and th e ad c i npu t i s conn e cted to the gnd. 33.5.3 po wer manager th e adc is automatica lly clocked after the first conversion in norm al mode. in slee p mode , the adc cl oc k is automatica lly stopped afte r ea ch conversion. as t h e lo gic is sma ll and the adc c ell can b e put int o slee p mode , the po wer manager(pm) has n o e ffect on t he adc behavior. 3 3.5. 4 i nterr up t cont roll er t he adc interrup t line is co nnec ted on on e o f the internal source s of the interrup t controller. using t he adc interrupt requir es the intc t o be programme d first. 33.5.5 timer triggers time r counters ma y or may no t be use d as hardware triggers dependin g o n user requirements. t hu s, s om e o r all of t he timer counter s ma y b e n on-co nnecte d. 33.5.6 conversion performances fo r performanc e an d electr ical characterist ics of t he adc, see t he dc characteri stics section. 32058k avr32-01/12 702 at32uc3a 33.6 functional description 33.6.1 analog-to-digita l conversion th e adc uses th e adc clock to perfor m conversions. converting a s ingl e anal og value t o a 10- bit digi tal data re quires sam ple and hold clock cycles as defi ned in the field shtim of the mr register and 10 adc clock cycl es. th e adc clock freq uency is select ed in the prescal field of th e mr register. t he adc clo ck rang e is betwee n clk_adc/2, if prescal is 0 , and clk_adc/128 , if pres- cal is se t t o 63 (0x3f). prescal must be programme d in order to provide an adc cloc k frequency accordin g to th e parameter s given in t h e product definition section. 33.6.2 co nversion reference th e conver sion is perf orm e d o n a fu ll rang e b e twee n 0v and th e reference voltag e pin advref. analog inpu ts between these voltages conver t to values base d o n a linea r conversion. 33.6.3 co nversion resolution t he ad c s upp o rt s 8-bi t or 10-b it res olut ions. t he 8 - bit select ion is perform e d by setting the bi t lowr es in th e adc mode register (mr) . by default, after a reset, the resolution is the highest an d the data field in th e d a ta re gisters is fully us ed. by setting th e bit l owres, the adc sw itche s i n the lowest resolution an d th e conversion resu lts ca n b e read in th e e igh t lo west sig- nifican t b its o f t h e dat a re giste r s . th e tw o hig hest b it s o f t h e d ata fie l d i n th e cor resp ond ing cdr r egiste r a nd of th e ldata fiel d in the lcdr register re ad 0. moreover , when a pdc ch anne l is connected to the adc, 10-bit resoluti on sets the transfer requ est sizes to 16-bit . setting the bi t lo wres automat ically switches to 8-bit data transfers. in this case, th e destinatio n buffers ar e optimized. 32058k avr32-01/12 703 at32uc3a 33.6.4 co nversion results when a c onversion is co mpleted , th e resultin g 10-bit digita l valu e is stor ed in the channe l data regis t er (cdr ) of the current ch annel and in the adc las t converted data regi st er (lcdr). the channel eo c bit in t he status regi ster (sr) is set and the drdy is set. in the case of a connect ed pdc channel, drdy risin g triggers a data transf er request . i n an y case, either eoc and d rdy ca n trigger an interrupt. r eading one of the cd r re g ister s cle a rs the corresponding eoc bi t. reading lcdr clea rs the drdy bi t and the eoc bi t corresponding to t he last converte d channel. figur e 33-2. eo cx an d drdy flag behavior read lcdr write cr with start=1 read cdrx write cr with start=1 chx(chsr) eocx ( sr) drdy(sr) conversion time conversion time 32058k avr32-01/12 704 at32uc3a if the cdr is not read be fo re further incoming da ta i s c onv e rt ed , t h e corres pondi n g ov e rru n error (ovre ) flag is se t in the status registe r (sr). in th e sam e way , ne w data conve rt ed w he n drdy is hi gh sets th e bi t govre (gener al overr un error) in sr. th e ovre and govre flag s a r e auto mati cally cle ar ed whe n sr is rea d. figur e 33-3. govr e and ovrex flag behavior warning: if t h e corresponding channel is disabled durin g a conversion or if it is dis able d and t hen ree nabled du ring a conversion, its associat ed dat a and its correspon ding eo c and ovre fl ags in sr ar e unpredictable. read sr dat a c dat a c dat a b dat a b dat a a dat a a undefined data undefined data undefined data lcdr crd0 ch1(chsr) ch0(chsr) trigger crd1 eoc0(sr) eoc1(sr) govre(sr) drdy(asr) ovre0(sr) read cdr0 re ad cdr1 c onve r sion c o nv ers ion conversion 32058k avr32-01/12 705 at32uc3a 33.6.5 co nversion trigge rs conversions o f the activ e analog channels ar e starte d with a software or a hardware trigger. the software trigge r is provid ed by writing the control regist er (cr) with the bit start at 1. th e hardware trigger can be one of the tioa outputs of th e tim er counte r channels, or the exte rnal trigge r inpu t of the adc (trigger). t he hardware trig ger is sele cted with the field trgs el in t he mode regist er (mr). the s elected hardwa re trigg er is enabled wit h the bit trgen in t h e mo de registe r (mr). if a hardware trigger is sel ected, the start of a conversion is de tected at each rising edge of the selecte d si gna l . if one o f th e ti o a output s is selected , th e correspondin g time r coun te r cha nnel must be programme d in wavefor m mode. on ly on e start command is necessary to initiate a co nversion sequence on all th e channels. the ad c har dware logi c aut omaticall y perf or ms t he conver sions on the active channels, then waits fo r a ne w r eq ue st. t h e cha nne l e nable (che r) an d chan ne l disa bl e ( c hdr) reg ister s en abl e the analo g chan nel s t o be enabl ed o r disable d indepen dent ly. if the adc is us e d with a pdc, only t he transfers of co nvert ed data fr om enabled channels ar e performe d an d the r esulti ng dat a b uffer s sho ul d b e interprete d acco rdi ngly. warning: enabling hardware trigger s doe s not disable the software trigger functionality. thus, if a hardware trigger is selec ted, t he star t of a co nversion ca n be initiate d either by th e hardware or the softwar e trigger. 33.6.6 sleep m ode an d conver sion sequencer th e adc sleep mode maximize s power saving by au tomat ically d eactiva ting th e adc whe n it is not b eing used for conversions . sleep mode is s e lected by setting th e bit sl eep in the mode register mr. the s l eep mode is auto matically ma naged by a conversio n sequencer, which can automati- cally pr ocess t he conversions of all cha nne ls at lowest power consumption. when a s t art conve rsion request occurs, th e adc i s auto matical ly a ctivat ed. as the an alog cell requires a s tart-up time, t he lo gic wait s during this ti me an d starts the conversion on th e enabled channels. when all co nversion s ar e complete, th e adc is deactivated until the next trigger. trig- ge rs occurrin g during the sequen ce ar e not ta ken int o account. th e conversion sequencer allo ws automatic processing with minimum processor intervention and optim ized powe r consumption. conversion sequence s ca n b e pe rfo rme d periodicall y u sing a timer/counter output. the period ic acquisition of severa l samp les can be processe d automat- ically without any intervention of th e processor thanks to th e pdc. note: the reference voltag e p ins alwa ys rema in connecte d in nor mal mod e as in sle ep mode. 32058k avr32-01/12 706 at32uc3a 3 3.6. 7 a dc tim ings each adc ha s it s own minima l startup time that is p rogramm ed through the fiel d st artup in t he mode registe r mr. in t h e same way, a mi nima l samp le and ho ld time is n ecessa ry for the adc t o g uaran tee the bes t conver t ed final val ue b etwee n t w o channe ls sele cti o n. th is tim e h as to b e progra mmed through t he bitfield shti m in th e mo de registe r mr. warning: no inp ut buffer amplifier to isola te t he sour ce is includ ed in t he adc. this mu st be take n in to consideration to pr ogram a pr ecise va lue in the shtim field . se e the se ction, adc characteris tics in th e product datasheet. 32058k avr32-01/12 707 at32uc3a 33.7 u ser interface tabl e 33-2. adc register mapping offset register name access reset state 0x00 c ontrol register cr write-only ? 0x04 mod e register mr read/write 0x00000000 0x10 chann el enab le register cher write-only ? 0x14 chann el disab le register chdr write-only ? 0x18 chann el status register chsr read-only 0x00000000 0x1c status reg ister sr read-only 0x000c0000 0x20 la st conver ted data register lcdr read-only 0x00000000 0x24 interrup t enab le register ier write-only ? 0x28 interrup t disable register idr write-only ? 0x2c interrup t mask register imr read-only 0x00000000 0x30 chann el data registe r 0 cdr0 read-only 0x00000000 ... ...(if implemented) ... ... ... 0x4c chann el data register 7(if implem ented) cdr 7 read-only 0x00000000 0xfc versi on register version read-only ? 32058k avr32-01/12 708 at32uc3a 33.7.1 contro l register nam e: cr acces s type: write-only offset: 0x00 reset value: ? ? star t: start con versi on 0 = n o e ffect. 1 = begins ana log- to - digit al c onversion. ? swr st : software re set 0 = n o e ffect. 1 = r esets t he adc simulatin g a hardwar e reset. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? start swrst 32058k avr32-01/12 709 at32uc3a 33.7.2 mo de register nam e: mr acces s type: read/write offset: 0x04 reset value: 0x00000000 ? shtim: sample & hold time sample & ho ld time = (shtim+1) / a dcclock ? star tup: star t up time startup time = (startup +1 ) * 8 / adcclock ? pres cal: prescaler rate selection adc clock = clk_adc / ( (prescal+1) * 2 ) ? s leep: sleep mode ? lowres: resolution ? trgsel: trigge r selection 31 30 29 28 27 26 25 24 ? ? ? ? shtim 23 22 21 20 19 18 17 16 ? ? ? startup 15 14 13 12 11 10 9 8 ? ? prescal 7 6 5 4 3 2 1 0 ? ? sleep lowres trgsel trgen s l eep sel ected mode 0 nor mal mode 1 sle ep mode lowres selected resolution 0 1 0-bit resolution 1 8 -bit resolution trgsel selected trgsel 0 0 0 inte r nal t r ig g er 0, de pen d ing o f c h i p i nteg r a t ion 0 0 1 internal t r ig g er 1, de pen d ing o f c h i p i nteg r a t ion 0 1 0 inte r nal t r ig g er 2, de pen d ing o f c h i p i ntegr a t ion 0 1 1 internal t r ig g er 3, de pen d ing o f c h i p i ntegr a t ion 1 0 0 inte r nal t r ig g er 4, de pen d ing o f c h i p i nteg r a t ion 32058k avr32-01/12 710 at32uc3a ? trgen: trigge r enab le 1 0 1 i n te rn al t r ig g er 5, de pend ing o f c hip i nteg rat ion 1 1 0 extern al trigger 1 1 1 reserved trgen sel ected trgen 0 hardw are triggers ar e disabl ed. starting a conversion is on ly possible by software. 1 hardw are trigge r selected by tr gsel field is e nabled. trgsel selected trgsel 32058k avr32-01/12 711 at32uc3a 33 .7.3 chan nel e nab le r egis ter nam e: cher acces s type: write-only offset: 0x10 reset value: ? ? chx: cha n nel x enable 0 = n o e ffect. 1 = e nab les the co rr espo nding channel(if implem ented). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ch2 ch6 ch5 ch4 ch3 ch2 ch1 ch0 32058k avr32-01/12 712 at32uc3a 33.7.4 channel disabl e register nam e: chdr acces s type: write-only offset: 0x14 reset value: ? ? chx: channel x disable 0 = n o e ffect. 1 = disa bl e s th e corr espond in g cha nnel(if i mplemen ted ). warning: if t he correspon ding chan nel is disabled dur ing a conversion or i f it is disabled then reenabled during a c onver- sion , it s associate d data and its correspond ing eoc an d ovre flag s in sr a r e unpredictable. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 32058k avr32-01/12 713 at32uc3a 33.7.5 channel st atus register nam e: chsr acces s type: read-only offset: 0x18 reset value: 0x00000000 ? chx: channel x status 0 = c orresponding chan nel is disabled(if implemented). 1 = c orresponding chan nel is en abled ( if i mplemen ted ). 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 32058k avr32-01/12 714 at32uc3a 33.7.6 status register name: sr acces s type: read-only offset: 0x1c reset value: 0x000c000 0 ? rx b uff: rx buf fe r f ull 0 = rcr or rncr have a valu e other tha n 0. 1 = b ot h rcr and rncr h av e a va lue of 0. ? end rx: end of rx buffer 0 = th e receive counter register ha s not reach ed 0 since t he last writ e in rcr or rncr. 1 = th e receive counter register has reache d 0 since the last write in r cr or rncr. ? gov re: genera l over run error 0 = n o g ene ra l overru n erro r occurred si nc e th e las t re ad of sr. 1 = a t least one genera l overru n erro r has occurr ed since t he last re ad of sr. ? drdy: data rea dy 0 = no dat a has been converte d sinc e the last read of lcdr. 1 = a t least one dat a has been converte d and is available i n lcdr. ? ovr ex: overrun erro r x 0 = no overru n erro r on the correspondin g channel(if implemented) sinc e th e last read of sr. 1 = th ere has been an overru n erro r on th e corresponding channel (i f implemented) sinc e th e last read of sr. ? e ocx: end of conversi on x 0 = correspondin g an alog cha nne l (if i mplemen ted) is d isa bled, o r th e c onver sio n is not fini shed. 1 = c orresponding analog chann el (if implemented) is e nabled an d conversion is co mplete. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? rxbuff endrx govre drdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 7 6 5 4 3 2 1 0 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0 32058k avr32-01/12 715 at32uc3a 33.7. 7 la st con verte d dat a regis ter nam e: lcdr acces s type: read-only offset: 0x20 reset value: 0x00000000 ? ldata: las t data converted th e analog-to-digital conversion data is p laced into this registe r a t th e e nd of a conversion an d remain s un til a ne w conver- sion is completed. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ldata 7 6 5 4 3 2 1 0 ldata 32058k avr32-01/12 716 at32uc3a 33.7.8 interrupt enab le register nam e: ier acces s type: write-only offset: 0x24 reset value: ? ? rxbuff: receive buf f er full interrupt enable 0 = n o e ffect. 1 = e nables the correspondin g interrupt. endrx: en d of receive buffer interrup t enable ? go v re: ge nera l over run er r or i nte rrupt e n able ? drdy: data rea d y interrupt enable ? ovr ex: overrun error interrupt enabl e x ? eoc x : e nd of conver si on in ter rupt e nab le x 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? rxbuff endrx govre drdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 7 6 5 4 3 2 1 0 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0 32058k avr32-01/12 717 at32uc3a 33.7.9 int e rru p t disabl e re gister nam e: idr acces s type: write-only offset: 0x28 reset value: ? ? rxbuff : rec eiv e buffe r full interrupt disable 0 = n o e ffect. 1 = disa bl es th e co rr espo ndi ng interru pt. ? endrx: en d of receiv e buffer interrupt disable ? govre: g e ner a l o verrun err or in te rrupt dis able ? drdy: data rea d y interrupt disable ? o vrex: overru n error interr upt disab le x ? e ocx: end of conversi on inter rupt disabl e x 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? rxbuff endrx govre drdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 7 6 5 4 3 2 1 0 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0 32058k avr32-01/12 718 at32uc3a 33.7.10 interrupt ma sk register nam e: imr acces s type: read-only offset: 0x2c reset value: 0x00000000 ? rxbuff: receive buf f er full interrupt mask 0 = th e correspondin g interrupt is disabled. 1 = th e corresponding interrup t is enabled. ? end rx: end of receive buff er interrupt mask ? govre: g e ner a l o verrun err or in te rrupt ma sk ? drdy: data rea d y interrupt mask ? ovr ex: overrun error inter r up t mas k x ? e ocx: end of conversi on inter rupt mas k x 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? rxbuff endrx govre drdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 7 6 5 4 3 2 1 0 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0 32058k avr32-01/12 719 at32uc3a 33.7.11 channel data register nam e: cdrx acces s type: read-only offset: 0x2c-0x4c reset value: 0x00000000 ? dat a: converted data th e analog-to-digital conversion data is p laced into this registe r a t th e e nd of a conversion an d remain s un til a ne w conver- sion is co mpleted. the conv ert data register (c dr) is only loaded if th e corr espond ing analog chan nel is enabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? data 7 6 5 4 3 2 1 0 data 32058k avr32-01/12 720 at32uc3a 33.7.12 version register nam e: version acces s type: read-only offset: 0xfc reset value: ? ? variant: va riant number reserved. no functionalit y associated. ? version: vers ion number vers ion number of th e module. no functionalit y associated. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? variant 15 14 13 12 11 10 9 8 ? ? ? ? version[11:8] 7 6 5 4 3 2 1 0 version[7:0] 32058k avr32-01/12 721 at32uc3a 34. audio bitstream dac (abdac) re v: 1.0.1.1 34.1 features ? digital ste reo dac ? over sample d d / a c on v ersi on arch i t e c t ure ? oversampling ra tio fixed 128x ? f ir equalization filter ? dig ital interpolatio n filt er: comb4 ? 3rd order sigm a-delta d/a converters ? digital bi ts tream outputs ? parallel interface ? connected to dma controller fo r backgrou nd transf er without cpu inte rvention 34.2 description the au dio bitstrea m dac converts a 16- bit samp le va lue to a di gital bitstr eam wit h an ave rag e valu e proport ional to th e sample value. two channels are supported, making the audio bit- stream dac p a rticularly suitable for ste r eo au dio. each chann el has a pa ir of complementary digital o u tputs, dacn and dacn_n, which c an be connected to an external high inp ut imped- ance amplifier. th e audio bitstr eam dac is compromise d of two 3rd or der sigm a delta d/a c o nverter with an oversa mpling ratio of 128. t he samples are upsampl ed with a 4th order sinc interpolat ion filter (comb4 ) befor e being input to t he sigm al delta modulator . i n order t o compensate for the pass band fr e q uen cy r e sp o nse o f the in t erpo lat ion f i lter an d f latt en the o v eral l freque n cy r e s pons e, t he input to the interpolat ion filter is firs t filtered with a simple 3-t ap fi r filter.the total frequency respons e of th e equalization fir filter and t he interpolat ion filter is give n in figure 34-2 on page 733. the digital out p ut bitstreams f rom the sigma delt a modulators should be low-pass filtered to re move high frequency no ise inserted by t h e modulation process. th e output dacn an d dacn _n should be as id ea l as possible before filtering , to achieve the best snr qualit y. th e output ca n be connected to a class d amplif ier outpu t stage, o r it ca n be low p ass filtered an d connected to a high inpu t impedanc e amplifier. a sim ple 1st order or higher low p a ss filter that filters all the frequencies a bove 50 khz sh oul d be adequate. 32058k avr32-01/12 722 at32uc3a 34.3 block diagram figur e 34-1. function al block diagram 34.4 p in name list 34.5 p roduct dependencies 34.5.1 i / o lines t he outpu t p in s used for the output bitstr e a m fro m th e audi o bitstr ea m dac m a y be mu ltiplexe d with p io lines. befor e using the au dio bitstrea m dac, th e pio controller must be configured in order fo r the audio bitstre am dac i/ o line s to be in audi o bitstre a m dac pe riphe r al m o de. 34.5. 2 po wer mana gement th e pb-bu s clock to t he audi o bitstream dac is generate d by the power manager. before using the audi o bitstrea m dac , the programmer must ensure that th e audi o bitstream dac clock i s enab led in th e powe r manager. tabl e 34-1. i/o lines descripti on pin name pin description type data0 o utput from au di o bitstrea m da c chan nel 0 outp ut data1 o utput from au di o bitstrea m da c chan nel 1 outp ut datan0 inverte d ou tput from aud io bitstream dac chann el 0 output datan1 inverte d ou tput from aud io bitstream dac chann el 1 output clock gen er at or equalizati on fir comb (int=128) sigma-delta da-mod equalizati on fir comb (int=128) sigma-delta da-mod bit_clk bit_out1 bit_out2 clk sample_clk din1[15:0] din2[15:0] audio bitstr eam dac 32058k avr32-01/12 723 at32uc3a 34.5.3 c loc k management th e audio bitstrea m dac n eeds a sepa rate clock for the d/a c onversion operatio n. th is clock shou ld be se t up in t he generi c clock register in the powe r manager. t he freque ncy o f t his clock must b e 256 times the freque ncy of the desire d samplerate (f s ). for f s =48k hz this mean s that the clock m u st hav e a frequen cy of 12.288mhz. 34.5.4 in terrupts th e audi o bitstream dac i nterface ha s an interrupt line connected to the interrupt controller. in order to handle interrupts, t he interrupt controller must be programmed bef ore conf iguring the audio bitstream da c. all audi o bitstrea m dac interru pts can b e enabled/disabled by writing to th e audio bitstream da c i nt errupt enable/ disab le regi st ers . each pending and unmasked audio bi tstream dac interrupt w ill as sert the interrup t line. the audio bitstream da c int err upt ser vic e r o utin e ca n get th e i nterrupt s ou rc e b y readin g t h e int e rrupt s tatu s registe r. 34.5.5 dma t he audio bitstrea m dac is connec ted to th e dma controller . th e dma contro ller ca n be pro- gram me d to auto m atically transfer samples to the audio bitstr ea m dac samp le data register (sdr) when t he audio bits tream dac is ready for new samples . this enables t he audio bit- stream dac to ope r ate without any cpu interventio n such as polling the interru pt status register (isr) or using interr upts. se e the dma controller docum entation for deta ils on how to setu p dma transfers. 34.6 functional description in ord e r to use the audio bitstre am dac the prod uct dependen cies give n in section 34.5 on page 722 must be resolved . particular attent ion sh ould be given to t he configuration of clocks and i/o lin es in order t o ensure correct operation o f the au dio bitstream dac. the audio bitst rea m dac is enable d b y writing th e enable bi t in the au di o bits tream dac contro l registe r (cr). the two 16-bit sample values fo r channe l 0 and 1 can then be written to th e le as t and mo st signi fi c ant halfwor d of the sa mple data register (sdr), respective ly. the tx_ready bi t in the interrup t stat us register (is r ) wi ll be s et w h enever t he da c is re a dy to receive a n e w samp le. a ne w samp le value shou ld be wr i tten to sdr before 256 dac clock c y cles, o r a n un d errun w ill oc cu r, a s indi c a ted b y t he und erru n s tatus f lags i n isr. is r is cleared when r ead, o r whe n w r iti n g on e to th e correspondin g bits i n th e inte rrupt c lea r r egis ter (icr). for interrupt-base d operatio n, th e relevan t interrupts must be enable d by writin g one to the cor- responding bits in the interrupt enab le registe r (ier). interrupts ca n be disabled by the interrupt disable register (idr), an d active interrupts ar e indicated in t he read-o nly interrup t ma sk regis- te r (im r). th e audio bitstrea m dac can also b e configured fo r peripher al dma access, in which case only th e enabl e bit i n the con tro l registe r nee ds t o b e se t i n th e audio b itstr ea m dac mod ule. 34.6.1 equalizati on filter the equaliza tion filt er is a simple 3-tap fi r filter . the purpose of this filt er is to compensat e for the pa ss ba nd fre qu e ncy response of th e sin c int erpolati on filter. the equalization fil ter makes the pa ss ban d respon se more flat an d moves the -3db corner a li ttl e higher. 32058k avr32-01/12 724 at32uc3a 34.6.2 in terpolation filter th e interpolation filt er interpolates from f s t o 128f s . t his filter is a 4t h orde r cascaded integrator- comb filter , and the basic building blocks o f this filter i s a comb par t and an in te grator part. 34.6.3 sigma delt a modulator this part is a 3rd order sigma delta modulator c o nsisting of thr ee differentiat ors (delta blocks), t hree integrator s (sigm a b locks) a n d a o n e b i t qua ntizer. the p urp o se of th e integra tors is t o sha p e th e noise , s o tha t th e noise is redu ce s in th e ban d o f in ter es t an d inc r ease d a t th e hig her frequencies, where it can be filtered. 34.6.4 data format inpu t data is on two?s complemen t format. 32058k avr32-01/12 725 at32uc3a 34.7 a udio bitstream d a c u ser interface tabl e 34-2. registe r mapping offset register register name access reset 0x0 s am pl e da t a r egi ster sdr read/write 0x0 0x4 reserved - - - 0x8 contro l register cr read/write 0x0 0xc inter rup t mask r egister imr read 0x0 0x10 interrup t enab le register ier write - 0x14 inter rup t dis a b le re gi ster idr write - 0x18 interrup t clear register icr write - 0x1c interrup t status register isr read 0x0 32058k avr32-01/12 726 at32uc3a 34.7.1 a udio bitstream da c sample data register nam e: sdr acces s type: read-write ? ch a nnel0: sample da ta fo r channel 0 signed 16-bit sample data for channe l 0. wh en th e swap bit in t he dac contro l regist er (cr) is set writing to th e sample data register (sd r) w ill caus e the values writ ten t o chann el0 a nd chann el1 to be swapped. ? ch a nnel1: sample da ta fo r channel 1 signed 16-bit sample data for channe l 1. wh en th e swap bit in t he dac contro l regist er (cr) is set writing to th e sample data register (sd r) w ill caus e the values writ ten t o chann el0 a nd chann el1 to be swapped. 31 30 29 28 27 26 25 24 channel1 23 22 21 20 19 18 17 16 channel1 15 14 13 12 11 10 9 8 channel0 7 6 5 4 3 2 1 0 channel0 32058k avr32-01/12 727 at32uc3a 34.7.2 a udio bitstream da c contro l register nam e: cr acces s type: read-write ? swap: sw ap channels 0: the ch a nnel0 and ch ann el1 samples w ill not be sw apped when wr iting the audio bitstream da c sample data regist er (sdr). 1: the c h annel0 and chann el1 samples will be sw apped when writing the audio bit s tream dac sample data regis- te r (sdr). ? e n: enable a udio bitstream dac 0: audio bitstream da c is disabled. 1: audio bi tstream da c is enabled. 31 30 29 28 27 26 25 24 en swap - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 32058k avr32-01/12 728 at32uc3a 34.7.3 a udio bitstream da c interrupt mask register nam e: imr acces s type: read-only ? underru n: underr un inte rrupt mask 0: the audio bitstrea m dac underru n interrupt is disabled. 1: the audio bitstrea m dac underru n interrupt is enabled. ? tx_ready: tx r ead y inte rrupt mask 0: the audio bitstrea m dac tx read y interrupt is disa bled. 1: the audio bitstrea m dac tx read y interrupt is en abled. 31 30 29 28 27 26 25 24 - - tx_ready underrun - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 32058k avr32-01/12 729 at32uc3a 34.7.4 a udio bitstream da c interr upt enable register nam e: ier acces s type: write-only ? underru n: underr un inte rrupt enable 0: no e ffect. 1: en able s th e a udio bitstrea m d a c un de r ru n inte rrupt. ? tx_ready: tx read y inte rrupt enable 0: no e ffect. 1: enab les th e audio bitstrea m dac tx re ady interrupt. 31 30 29 28 27 26 25 24 - - tx_ready underrun - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 32058k avr32-01/12 730 at32uc3a 34.7.5 a udio bitstream da c interr upt disab le register nam e: idr acces s type: write-only ? underru n: underr un inte rrupt disable 0: no e ffect. 1: disable th e audio bitst ream d a c under run interrupt. ? tx_ready : tx ready interrupt disable 0: no e ffect. 1: disable th e audio bitst ream dac tx ready interrupt. 31 30 29 28 27 26 25 24 - - tx_ready underrun - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 32058k avr32-01/12 731 at32uc3a 34.7.6 a udio bitstream da c interr upt clear register nam e: icr acces s type: write-only ? underru n: underr un inte rrupt clear 0: no e ffect. 1: clear th e audio bitstrea m dac underr un interrupt. ? tx_ready : tx ready interrupt clear 0: no e ffect. 1: c lea r t h e audi o bitstrea m da c tx r eady inter rupt. 31 30 29 28 27 26 25 24 - - tx_ready underrun - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 32058k avr32-01/12 732 at32uc3a 34 .7.7 a udio bitstrea m da c interr upt status register nam e: isr acces s type: read-only ? un derrun : unde rr un in te rrupt sta tus 0: no audi o bitstrea m dac underr un has occured since the last time is r was read or sinc e reset. 1: at l e ast on e audio bitstrea m dac underru n has occured since the last time is r was read or sinc e reset. ? tx_ready: tx r ead y inte rrupt status 0: no audi o bitstrea m dac tx re ady has occuredt sinc e th e las t time is r was read. 1: a t l ea st o n e audio bitstrea m da c tx r ea d y h a s occuredt since t h e las t time is r wa s read. 31 30 29 28 27 26 25 24 - - tx_ready underrun - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 32058k avr32-01/12 733 at32uc3a 34.8 frequency response figur e 34-2. frequecy response, eq-fir+comb 4 0 1 2 3 4 5 6 7 8 9 10 x 1 0 4 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 10 32058k avr32-01/12 734 at32uc3a 35. on-chip deb ug re v: 1.3.0.0 35.1 features ? debu g interface in compli ance with ieee-isto 5001- 2003 (nex us 2.0) class 2+ ? jta g ac ce s s t o al l o n -ch i p debu g func tions ? adva nced pr ogram, data, ownership , and watchpoi nt trace supported ? nanotra ce jtag-base d trace access ? auxiliary port fo r high-spe ed tra ce information ? hardwa re supp ort f or 6 p ro g ram and 2 data breakpoints ? unlimited nu mber of software brea kpoints supported ? automatic crc chec k of memo ry regions 35.2 overvi ew debuggin g on the at32 uc3a is facilitate d by a p owerful on -chip debu g (ocd) system. the user accesses th is through an external debug tool which co nnects to th e jtag port and th e aux- iliary (a ux ) port. the aux port is primarily used for trace functi ons, and a jtag-based debugge r is sufficient fo r ba sic debugging. th e debug system is b ase d on the nexu s 2. 0 standard, class 2+ , which includes: ? basic run- time contr ol ? progra m breakpoints ? dat a breakpoints ?program trace ? o wnership trace ? d ata trace in addition to the mandator y nexus debu g features , the at32u c3a implements several useful ocd f eatur es, such as: ? debug communication chann el between cpu an d jtag ? r un-tim e p c monito ri ng ? c rc checking ? nanotrace ? softwar e qu alit y assura nc e (s qa ) suppo rt the ocd feat ures are controlle d by ocd regist ers, wh ich ca n b e accessed by jtag wh en the nexus_a ccess jtag instruction is loaded. the cp u can also access ocd registers directl y usin g mtdr/mfdr instructions in a ny privileg ed mode . th e ocd registers are implemented based on th e recommendations in th e nexus 2.0 standard, and are detaile d in t he avr32uc technical reference manual. 32058k avr32-01/12 735 at32uc3a 35.3 block diagram figur e 35-1. on-chip debu g block diagram 35.4 functional description 35.4.1 jtag-bas ed debug features a debug g er ca n cont rol all ocd features by wri tin g ocd register s over th e jtag interface. ma ny o f these do not depe nd on output on t he aux port, allowin g a jtag-based debugge r to be used. a j tag-based debugger should connect to the device through a s tandar d 10-pin id c connector a s de sc ribed in th e avr32u c tech n ica l reference ma nual. on-chip debug jtag debug pc debug instruction cpu breakpoints program trace data trace ownership trace watchpoints transmit queue aux jtag internal sram s e r v ic e a c c e s s b u s memory service unit hs b bus matrix memor i es and peripherals 32058k avr32-01/12 736 at32uc3a figur e 35-2. jt ag- base d debugger 35.4.1.1 debug communicatio n channel the debug communication channel ( d cc) consists of a pair ocd regis t ers with associated handsha ke logic, accessible t o bot h cpu an d jtag. th e register s can be used t o exchange data between th e cpu and th e jt ag master , bot h runtim e as well as i n debu g mode. 35 .4.1. 2 brea kpoin ts one of the most fundamental debu g features is the abili t y to halt the cpu, to examine regi ster s and th e state of the system. this is accomp lis h ed by breakpoints, of whic h many types are available: ? u nconditiona l breakpoints ar e set by writin g ocd registers by jtag , halting t he cpu immed i ate l y. ? progra m breakpoint s halt the cpu wh en a speci fic addr ess in th e progra m is executed. ? dat a breakpoint s halt th e cpu whe n a sp ecific memory addr ess is read or written, allowing variab les t o be watched. ? softwar e breakpoints halt th e cpu when the breakpoint instruction is executed. when a b reakpoint triggers, the cpu en t ers debug mode, a nd th e d bit in t he status regist er is set. th is is a privilege d mo de with dedicated return address and return stat us registers. all privi- lege d instructions are permitted. debug mode ca n be entered as either ocd m ode, running instructions fr om jtag, or monito r mode, running instructio ns fr om progra m memory. avr32 jtag-based debu g tool pc jtag 10-pin idc 32058k avr32-01/12 737 at32uc3a 35.4.1.3 ocd mode whe n a breakpoi nt triggers , the cpu e nte rs oc d mode , an d instructions ar e fetched from the debug instruction ocd register. each time t his register is writte n by jtag, the instruction i s execu ted, allowing th e jtag to execute cpu instr uctions dire ctly. th e jtag maste r can e.g. read ou t th e register fil e by issuing m tdr instructions to th e cpu, w ritin g eac h regist er to the deb ug communication chann el ocd registers. 35.4.1.4 monito r mode s inc e t he o cd r eg ister s a re direc t ly a ccess ible by the c pu, it is po ssible to bu i ld a software- b ase d deb ugge r t h at run s on t he cp u i t sel f . se t t ing t he m onitor mo d e bi t in t h e d e v elop m ent c on tr ol regi s ter c au ses th e cpu to enter monitor mod e instead o f o cd mo d e wh en a breakpo int t riggers . m onit or mode is similar to ocd mo d e , exce p t th a t i n structi o ns ar e fetc hed fr om th e debu g exception vector in regula r progra m memo ry, instea d of issue d by jtag. 35.4.1.5 program counter monitoring normally , th e cpu woul d nee d to be halte d fo r a jtag-b as ed deb ugge r to examine th e curr ent pc val ue. however , the at 32uc3a also proves a debug progr am counte r ocd register, where the debugger can co ntinu ously read t he curren t pc without affecting the cpu. th is allows the debugger t o generat e a simp le statistic of the time sp ent in variou s area s of the code , easing code optimization. 35.4.2 memory servic e unit the memo ry serv ice uni t (msu) is a bloc k dedicated to tes t an d debu g functionalit y. it is con- trolled throug h a dedicat ed set of registers addressed through the memory_servi ce jtag com mand. 35.4.2.1 cyclic redundancy check (crc) the msu can be used t o automatically calculate th e crc of a block o f dat a in memory. the ocd w ill then read out e ac h w o rd in the sp ecified memory bloc k and re por t t he cr c3 2-va lue in an ocd register. 35.4.2.2 nanotrace the msu ad ditiona lly suppor ts nanotr ace. th is is a n avr32-specific feature, in whic h trace dat a is output to m e mory instead of t he aux port . th is allows the tr ace data t o be extracte d by jtag mem ory_access, enabling trace features fo r jtag -base d debug gers. t he use r mus t writ e msu registers to configure t he addr ess an d size of th e memory block to be use d for nano- trace. th e nanotr ace buffer can be anywh er e in the physical addre ss range , includin g internal an d extern al ram, thr oug h an ebi , if pr esen t. this area may not be used by t h e applicat ion run- nin g o n the cpu. 35.4.3 aux-base d debug features utilizing the auxiliary (aux) port gi ves a ccess to a wide range of advanced debug features. of prime impo rtan ce ar e th e tr ac e fe atu res , whic h a llow an exter nal debu gge r t o rec eive cont i nuou s information on t he program execution in t h e cpu. additionally, event in an d event out pins a llow extern al even ts t o be correlated with th e program flow. th e aux port contains a n umber of pins , as shown in table 35-1 o n pag e 738. thes e a re multi- plex ed with pio lines, a nd mu st explicitly be enabl ed by writing ocd register s before th e debug session s tarts. the aux port is m apped to tw o different location s, selectable by ocd r egisters, minimizing the chance that th e aux port will need to be shar ed wit h an application. 32058k avr32-01/12 738 at32uc3a debug tools utili z ing t he au x po r t s hou ld c onne c t to the device throug h a nexus-co mpliant mic- tor-38 con n ector, as described in the avr32uc t echnical reference manual. this connecto r includes the jtag signals and the rese t _n pin, giving f ull access to t he programming and debu g featu r es in t h e device. figur e 35-3. aux+jtag b a sed debugger 35.4.3.1 trac e operation tr ace features are enabled by wri ting oc d registers by jtag. th e ocd extracts the trace infor- mation from t he cpu, compresses th is informat ion an d format s it into variable-lengt h messages according t o th e nexu s standard . the messages are buffered in a 16 -fra me transm it queue , and ar e output on t he aux port one fram e at a time. tabl e 35-1. auxiliary port signals signal direction description mcko output tr ace dat a outp ut clock mdo[5:0] output tr ace dat a output mseo[1:0] output tr ace frame control evti_n input even t in evto_n output even t out av r 3 2 au x+ j t a g debug tool jt a g au x high speed m ictor38 t rac e buffer pc 32058k avr32-01/12 739 at32uc3a the trace featur es can b e configured t o be very selective, t o re duce th e bandwidt h on the aux port. in case the transmit queu e overflows, err or me ssages ar e produced t o indicate lo ss of data. the transmit queue modu le can optiona lly be configured to hal t t he cpu when a n overflow occurs, t o prevent the lo ss of messages , at th e expens e of longe r run-time for t he program. 35.4.3.2 program trace progra m tra c e allows the debugg e r t o cont inuously monitor t he program execut ion in the cpu. program trace message s are generate d for eve ry bra nch in the prog ram, and contai ns com- pr essed informatio n, which allows t he debugger t o correlat e th e message with t he source code t o identi fy th e branch instructio n an d target address. 35.4.3.3 data trace da ta tr ace out puts a message ever y time a spec ific loca tion is read or writt en. the message con tains informatio n abou t th e type (rea d/write) an d size of the access, as well as th e address and data of the accessed location. t he at 32uc3a contains two data trace channels, each of which are controlled by a pair of ocd r egist ers which determine th e range of addresses (or sin- gl e addres s) which shou ld prod uce data tr ace messages. 35.4.3.4 ownership trace prog ram and data tr ace oper at e on vir tua l a ddr esse s. i n case s where an opera ting syste m run s seve ral proce sse s in over lapp ing virtua l memory segments , t he owner ship t r ace feat ur e ca n be used to identify th e process switch. when the o/s activate s a proce s s, it will write the process id number to an ocd register , which produce s an ownership trace message, allowing the debug- ge r to switch c ontex t fo r the subsequent program a n d d a ta tra ce m e ss a g es. as the us e o f t hi s fea tur e de pe nds o n t h e softwar e ru nnin g on t he cpu, it ca n a ls o be use d to ex tr act other type s of information from th e system. 35.4.3.5 watchpoint messages th e breakpo i nt mo d ules n o rma lly use d to ge n era te prog ram an d d ata br eakp oints ca n a ls o b e used to generate watchpoint messages, allowing a debugger to monitor program a nd data events without halting the cpu. watchpoint s can be enabled independently of breakpoints, so a breakpoint module can optionally halt the cpu w hen the trigger condition occurs. dat a trace modules can also be confi gur ed to produce watchpoint messages instead o f re gular data trace messages. 35.4.3.6 event i n and even t out pins th e aux port also co ntai ns an event in pi n (evti_n ) an d an event out pi n (evto_n). evti_n can be used to trigger a brea kpoin t whe n an ext ernal event occurs. it can also b e used to trigger specific progra m and da t a trac e synchronization messages , allowing an ex t ernal event to b e correlated to t he program flow. when the cpu en ter s debug mode, a de bug stat us messa ge is transmitted on the trace port. all trace mess a ges can be timestam ped when they ar e received by the debu g tool. however, due to the latency of the tran s mit queue buffering, the times tam p w ill no t be 100 % a c cur a te. t o improve this, evt o_ n can toggle ever y time a m essage is ins erted in to the tran smit queue, allowing t race message s t o b e timestampe d precisely. evto_n ca n also to ggle whe n a break- point module trigger s, or when the cpu en ters debu g mode, fo r any reason. th is ca n be used to measur e precisel y when th e respective inter nal event occurs. 32058k avr32-01/12 740 at32uc3a 35.4.3 .7 software qua lity analysis (sqa) software qualit y analysis (sqa) deals with two importan t issues regardin g embedded software development. co de coverage involves i dentifying untested part s o f the embedded code, to improve test procedur es and t hus the qualit y of th e r eleased software. perf ormance analysis allow s t he d ev elope r to p re cis el y qua n tif y t he tim e spen t in va rious parts of t he code, allowing bottlenecks to be identifie d an d optimized. program trace must be used to accomplish these ta sks withou t instrumenting (altering) th e code to be ex amin ed. however, tra ditional pro gram trace cann ot reconstruct th e curre nt pc val u e w ithou t corr elatin g the tra ce info rma tio n wit h th e source code, whic h cannot b e d o ne on-the- fly. t h is l imits p rogram tr ac e to a r e lative ly sh o rt time segment , determined by t he size of the trace buffe r in t he debu g tool. the ocd syst e m in at32uc3 a exte nds progra m trac e wit h sqa capabilities, allowing the debu g tool t o reconstruct th e pc valu e on-the-fly. code coverage and performance analysis can thus be reported fo r an unlimite d executio n sequence. 32058k avr32-01/12 741 at32uc3a 36. jtag and boundary scan rev. : 2.0.0.2 36.1 features ? ieee1149 .1 compliant jtag interface ? boundary-sc an chain for board-leve l testing ? direct me mory acces s an d p r og rammi ng ca pabilities through jtag interface ? on-chip de bu g access in compliance with ieee-isto 5001-2003 (n ex us 2.0) 36.2 overvi ew figur e 36-1 on pa ge 742 sho ws h o w th e jt a g is c onne cted in an a vr3 2 de vice . t he ta p con- troller is a stat e m achine controlled by the tck a nd tm s sig nals. th e tap controller selects either the j t ag instruction registe r or one of several dat a registers as the scan chain (shif t register) between the tdi-input a nd tdo-output. the instruction register ho lds jtag instruc- tions controlling the behavior of a data regi ster. the id register , bypa ss register, a nd th e boundary-sca n chai n ar e th e data register s used for bo a rd-level te sting. th e r e set registe r ca n b e us ed to ke ep the device r eset during test or programming. the s e rvice access bus (sab) int erface contai ns a dd ress a n d d at a registe rs fo r the se rvice access bus , which giv e s access t o on- chip debug, programming, and o ther f unctions in the device. the sab offers several modes of access to th e addre ss and da ta register s, as dis- cussed in s e ctio n 36.6.4. sec tion 36.7 lists the supported jt ag instructions , with refere nces to the descri ption in this document. 32058k avr32-01/12 742 at32uc3a 36.3 block diagram figur e 36-1. jtag an d boun dar y scan access avr32 device jtag dat a registers tap controller tck tms tdo ins t ructi on re gist er i d register by- pass reset register ser vi c e ac c es s bus interface boundar y scan ch a in cpu memori es and peripherals oc d r egisters pins and anal o g blocks ins t ructi on re giste r scan enab le data register scan enable jtag tap boundary sca n enable jtag de vice jtag master tck tdi tdo ... tdi tms ram high s p eed bus me mor y s ervice unit service access bus 32058k avr32-01/12 743 at32uc3a 36.4 i /o lines description 36.5 p roduct dependencies in orde r to use this module, other parts of th e system must be configured correctl y, as described below. 36.5.1 i / o lines th e jtag interface pi ns ar e multiplexed with io lines . when t he jt ag is used the associated pins must be enabled. to enable the jtag pins tc k must be zero while reset_n has a zero to one tran s ition . t o dis ab l e the jtag pins tck must be one while reset_n has a zero to on e transition. while using th e jtag lines a ll norma l peripheral activity on thes e lin es ar e disabled. the user must make sure that no external periphera l is blocking the jtag lin es wh ile debugging. 36.6 functional description 36.6.1 jtag interface the jtag interfac e is accesse d th ro ug h th e de dicated jtag pin s show n in table 36-1 on page 743. t he tms control line navigates the tap controller, as show n in figure 36-2 on page 744. th e tap controll er mana ges th e seri al access to th e jtag instruct ion an d data registers. data is scan n ed into t he select ed instruct ion or data register on tdi, and out of the register o n tdo, in the shift- ir an d shift -dr states, respectively. the l sb is shifte d in and out first. tdo is high- z i n o ther state s than shift-ir and shift-dr. independen t of th e initia l state of t he tap controller, the test-logic-rese t stat e can always be ent ere d by holding tm s high fo r 5 tc k clock peri ods. th is se quen ce sho u ld always be applie d a t t he st art of a jtag sessi on t o bring the tap controller into a de fined st ate bef ore applying jt ag co mm ands. applyi n g a 0 o n tm s fo r 1 tck p er io d b ring s th e t a p c o ntr o ller t o t h e run- t est/i dle st ate , whi ch i s th e s tarting point fo r jtag operati ons. the device implements a 5-bi t i nstruct ion regist er (ir). a number of public jtag instruction s def ined by t h e j ta g standar d ar e supporte d, a s descr ibed i n section 36. 8, as w e ll as a number of avr32- specific privat e jt ag instructions descri bed in section 36.9. each instruc t ion selects a s pe cific data reg is ter for th e shift- dr p ath , as descr ibed for eac h instructio n. tabl e 36-1. i/o lines descripti on name description type tck t est clock in put. fully asynchronou s to system cloc k frequency. input tms t est m o de sele ct, s am p le d on r ising tck input tdi t est data in , sample d on rising tck. input tdo test dat a out, driven on falling tck. output 32058k avr32-01/12 744 at32uc3a figur e 36-2. t ap controller stat e diagram 36.6.2 ty pical sequence assuming run-test/idle is t h e presen t state, a ty pical scenario fo r using t he jtag interf ace is: 36.6.2.1 scanning in j tag instruction at t he tm s in put, apply the seque nce 1, 1, 0, 0 a t the rising edg es of tc k to enter the shift instructio n register - s hift-ir state . while in thi s state , shif t the 5 bi ts of t h e jt ag instructions into th e jtag instruction register from the tdi i nput at the rising edge of tck. the tm s input mu st be he ld low during inpu t o f the 4 lsbs i n order to remain in the shift- ir state. th e jtag inst ruction select s a particular data register as pa th between tdi an d tdo an d contro ls th e cir- cuitry s urrou ndin g the selected dat a register. appl y th e tm s s eq ue nce 1, 1, 0 to re-en t er the run - t es t / i dle sta t e. the ins tr uct ion is latched onto the paralle l ou tput from th e shift reg ister p at h i n th e up date-ir state. th e e xit-ir , pause -ir, an d exit2-ir states ar e on ly used fo r navigating t he state machine. test-logi c- r eset run -test/ idle select-dr scan select-ir scan capture-dr capture-ir shift-dr sh i ft - ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 0 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 0 0 0 0 1 32058k avr32-01/12 745 at32uc3a figur e 36-3. scanning in jtag in struction 36.6.2.2 scannin g in/ou t data at the tms input, apply th e sequence 1, 0 , 0 at the ri sing edges of tc k to ent er the shift data registe r - shift- dr state. while in th is state, upload the select ed data register (selecte d by the presen t jt ag instructio n in the jtag instructio n register) from t he tdi inpu t a t the rising edge of tck. in order to remain in th e shift- dr state , t he tm s input mu st be he ld low . while the da ta register is shifted i n from th e tdi pin, the pa rallel inputs to the data register cap tured in the capture- dr stat e is shift ed out on th e tdo pin. ap pl y th e tms sequen ce 1, 1, 0 to re-enter th e run -t e st/ id l e state . if th e sele cted dat a regis ter has a latched parallel-output, th e latching takes pl ace in the update- dr state. th e exit-dr, pause- dr, an d exit2- dr stat es are only use d for navigating t he stat e machine. as sh ow n in the state diag ram, the run -test/idle state nee d not be ente red betwe en selecting jtag instruc tio n an d usin g dat a registers. 36.6.3 boundary-scan the boundar y-scan ch ain has the capability of driving and obse r ving the logic levels on the dig- ital i/o pins, as w e ll as th e boundary between digita l an d analog logic for analog circuitry having off-chip connections. at s ystem leve l, all ics having jtag capabilitie s ar e connected serially by the tdi/tdo signals to form a long shift re gister. an ex t ernal contr oller se ts up the devices to dr ive values at their output pi ns, an d observe t he input values rece ived fr om other de vices. the controlle r compares th e received data with th e expected result . in th is way, boundary-scan pro- vides a mechanism for t esting interconnections and int egrity o f c omponen ts on p r in ted circui ts boards by usin g th e 4 tap sig n als only. the four ieee 1149.1 defined mandatory jtag i n structions idcode, by pass, sample/pre- load, and extest can be us ed for t esting the p rint ed circ uit board . i ni t ial sca nning of th e data register path will sho w th e id -code of the device, sinc e idcod e is the default jtag instruction . it may b e desirable to have th e avr3 2 device in r eset during test mode. if not reset, inpu ts to th e device ma y b e determined by th e sca n operatio ns, an d th e internal software may be in an undetermin ed stat e when exiting the test mode. entering reset, th e output s of an y port pin will ins t antly enter t he high impedance state , makin g th e hig hz i n structio n redundan t . i f neede d, the bypass instruction ca n be issued to ma ke the shortest po ssible sca n chain th rough the device. the device can be set in t he rese t st ate either by pulling th e external resetn pin low, or issuing the avr_reset ins tructio n with ap propriate setting of the reset data register. th e extest instructio n is used for sam pling external pins an d lo ading ou tput pins with data. the data from the output latch w ill be driven out on the pins as soon a s the extest instru ction is loa ded into t he jtag ir-register. therefore , t he sample/preloa d should also be used for setting initia l values to the sca n ring, to avoi d damaging th e boar d when issuing th e extest tck tap state tlr rti seldr selir capir shir ex1ir updir rti tms tdi instruction tdo impldefined 32058k avr32-01/12 746 at32uc3a instructio n for the fi rs t time . sample/preload c an also be used for taking a s n apshot of the external pins duri ng norm al operatio n of th e part. w hen us i ng t he jtag in t er fac e f or boundar y -s can, the jtag tck cl oc k is independent of the internal chip clock, whic h is not required to run. 36.6. 4 serv ice access bus a number of private instruction s are used to access service access bus (sab) resou r ces. each of these are described in d e tail in sab address map in the ser vic e a cce ss b u s chapter. the memory_sized_a ccess instruction allows a sized r ead or write to any 36 -bit address on the bus. memory_word_access is a shorthand instruction f or 32- bit accesses to any 36-bit address, while t he nexus_access instr uction is a nexus-co m pliant short hand instruct ion for accessing t h e 32-bi t ocd register s in th e 7-bit addr ess sp ace reserved for these. t hese instruc- tions requir e two passes through t he shift -dr tap stat e: on e fo r th e addr ess and control information , an d one fo r data. to incr e ase th e transfe r rate, consecut ive memo ry accesses can b e accom p lish ed by th e memory_block_access instruction, which only requires a single pass throu gh shift-dr for data transfer only. the add ress is automat ically incremente d according to th e size of th e last sab transfer. the access time to sab resources depend s on the type of resource being accessed. it is possi- ble to r ea d external memo ry through t he ebi, in wh ich ca se th e latency may be ve ry long . it is possible to abort an ongoing sab access by the ca ncel_acc ess instruction, to avoid hang- ing th e bus du e t o an extrem ely slow slave. "the access time to sab r e sources depends on the type of resource being accessed. it is possible to a b ort an ongoing sab access by the cancel_acc ess instructio n, to avo id hanging the bus due to an extremely slow slave." 36.6.4 .1 b u sy reporting as th e time taken to perfor m an acce ss ma y vary depending on syst em acti vity an d curren t chip fr equency, all t he sab access jtag instr uctions can re tu rn a busy indicator. this indic ates whethe r a delay nee ds t o be inserted , or an o perat ion ne eds to b e repeat ed in order to b e suc- cessful. if a new acc ess is r e queste d w hi l e t he sab is bu sy, th e re q uest is ignored. th e sab become s bu sy when: ? enterin g update -dr in th e addre ss ph ase of any read operation, e.g. afte r scannin g in a nexus_a ccess address wit h the read bit set. ? enterin g update -dr in t he dat a p hase of an y writ e operation, e.g. afte r scannin g in data fo r a nexus_a ccess write. ? enterin g update-dr during a mem ory_block_access. ? enterin g update-dr afte r scanning in a cou nter value fo r sync. ? enter ing update-ir af ter scanning in a memory_block_ac cess if the prev ious access wa s a rea d a n d da t a wa s scanne d afte r sc annin g th e addre ss. th e sab become s read y again when: ? a rea d or writ e operati on completes. 32058k avr32-01/12 747 at32uc3a ? a s yn c c o untdo wn co m plet ed. ? a ope ra ti on is can c ell ed by the can cel_acc ess instruction. what t o do if th e busy bi t is set: ? durin g shift-ir: th e ne w instructio n is selected, but th e previous operat ion has not yet completed and will conti n ue (u nless the ne w instru ction is cancel_access). yo u may continue shifting the same instructio n unt il the busy bit clears, or start shifting data . if shifting data, you m ust be prepared tha t the dat a shift may also report busy. ? d urin g shi ft- dr of an address: the n ew addre ss is ig nored . the sa b s ta ys i n address mode, so n o d ata must be shifted. repeat t he address until the bu sy bit clears. ? d ur ing shift-dr of read data: the read data are inva lid. the sab stays in da ta mode . repeat scanni ng until the bu sy bit clears. ? durin g shift- dr o f wri te da ta: t he writ e da ta ar e igno red . t h e sab stay s in dat a mo de. repeat scanning until the busy bi t clears. 36.6.4.2 error reporting th e service access po rt may not be able to complete all a cc e sse s a s requ es ted . th is may be because th e addr ess is invalid , the addressed area is re ad-only o r cannot handle byte/halfword accesses, or because t he chip is set in a prot ected mode where only limited accesses are allowed. th e erro r bit is update d when a n acce ss completes, a nd is cleare d whe n a ne w acce ss starts. what t o do if th e e rr or bit is set: ? during shift-ir: th e new instruction is s elected . the la st operatio n performe d usin g th e old instruct ion did not complete successfully. ? durin g shift- dr of an addr ess: th e prev ious operation failed. th e new addr ess is accepted. if th e rea d bi t is set, a read operatio n is started. ? d urin g sh ift- dr of r ead data: th e r ea d op eratio n failed, an d th e rea d dat a are inv ali d. ? durin g shift- dr of write data: the previ ous write operation failed. the ne w data are accepted an d a write operation started. th is should only occu r during bloc k writes or stream writes. no erro r ca n occur between scannin g a writ e addr ess and the following writ e data. ? while po lling with cancel_access: t he previous access wa s cancelled . it may or ma y not hav e actually comp leted. 36.6.5 memory programming the hi g h-speed bus (hsb) in t he device is mappe d as a slave on th e sab. this ena b les all hsb-mapped memori es t o be read or written through the sab usin g jtag instructions, as describe d in secti o n 36. 6.4. inter nal sram can always be dire ctly accessed. external static m emory or sdra m can be accessed if the ebi has b e en corr ectly configured to access t h is memo ry. it is also possibl e to access t h e configuration re gisters for these m odules to set up the co rrect configuratio n. simi- larly, exter nal parallel flash can be programme d by accessing the register s for the flash devic e through t he ebi. th e intern al flas h and fu ses can likewise be p rogramme d by accessin g the register s in the flash controller. when th e security fuse is set, acce ss to internal m emory is bl ocked, and the chip_er ase instruction must be used to erase th e fus e and f las h conten t s. for detail see th e sab address map section. 32058k avr32-01/12 748 at32uc3a memory can be writ ten while t he cpu is executing, which can be u t ilized for debug pu rposes. when downloading a new prog ram, t he jtag halt inst ruction should be used to fr eeze the c pu, to preven t pa r ti a ll y downloa de d c ode from bein g execute d. 36.7 jtag instruction summary the implemented jtag instructions in th e avr32 ar e show n in the tabl e below. 36 .7.1 sec urit y rest rictio ns when the security fuse in t h e flash is program med, the followin g jt ag instructions are restricted: ? nexus_access ? memory_word_access ? memory_block_access ? memory_sized_access tabl e 36-2. jtag inst ruction summary instruction opcode instruction description page 0x01 idcode sele ct th e 32-bi t id register as da ta register. 749 0x02 sam ple_prelo ad take a sn apshot of exter nal pin va lues without affe cting system operation. 749 0x03 extest sele ct boundary sca n chain as d a ta register fo r testing circuitry external to t he device. 749 0x04 in test sele ct boundary sc a n chain fo r i nt ern al t esti n g of the d e vice. 749 0x06 clamp bypass d e vice through bypa ss register, whil e drivin g ou tputs from bo und ary sc a n r e gister . 750 0x0c avr_reset apply or rem ove a static reset to the d evice 757 0x0f chip_erase eras e the device 757 0x10 nexus_access sele ct th e sab ad dr e ss an d data registers as data register fo r t h e tap. the registers ar e accessed in nexus mode. 751 0x11 memory_word_access sele ct th e sab addre ss an d data registers as data register fo r the tap. 754 0x12 memo ry _blo ck_ acc ess sele ct th e sab da ta register as d ata register fo r the tap. the address is auto-incremented. 755 0x13 cancel_access canc el an ongoing nexus or memory access. 756 0x14 memory_service sele ct th e sab ad dr e ss an d data registers as data register fo r t h e tap. th e re gisters ar e a ccessed in memory se rv ice m od e. 752 0x15 memory_sized_access sele ct th e sab ad dr e ss an d data registers as data register fo r t h e tap. 753 0x17 sync synchronization counter 757 0x1c halt halt the cpu fo r safe programming. 758 0x1f bypass b ypass this devi ce thro ugh the bypa ss register. 750 others n/a acts as by pass 32058k avr32-01/12 749 at32uc3a for description o f what memory loca ti ons remain accessible, please ref er to the sab address map. full access t o thes e instru cti ons is re-e nabl ed wh en th e security fuse is era sed by the ch ip_erase jtag instruction. note tha t t he security bi t will read as programmed and bloc k th ese instructions also i f the flash controller i s statically reset. other security me chanisms can also restrict these functions. i f such mechanisms are present they are listed in the sab address map section. 36.8 p ublic jtag instructions 36.8.1 i dcode th is instructio n selects th e 32 bit id r egister as data register. the id register consists of a ver- sion nu mber , a device number an d the manu factur er code cho s en b y je dec. this is the default instructio n afte r power-up. th e active stat es are: ? capture-dr : the st atic idcode value is la tched into th e shift register. ? shift- dr: th e idcode scan ch ain is shifted by th e tck input. 36.8.2 sample_preload jtag i nstruction for taking a snap-shot o f the input/output pins without affectin g t he system operation, and pre-loading the scan chai n without updating the dr-latch. the bou ndary-scan chain i s select ed a s dat a register. th e active stat es are: ? c aptur e- dr: d at a on th e e xterna l pins ar e sample d int o th e b o undary-sca n chain. ? shift- dr: th e boundary-scan chai n is shifted by the tck in put. 36.8.3 extest jtag instruction for selecting th e boundary-scan chain as da ta register fo r testin g circuitry ex ter nal t o th e avr32 pa ckage . t he con ten ts of t he latche d outputs of th e boun dar y-scan chai n is driven out as so on as th e jtag ir-registe r is load ed wit h th e extest instruction. th e active stat es are: ? c apture-dr: data on the external pi ns is samp led into the boundary- scan chain. ? shi ft- dr: t h e i nterna l s ca n chai n is s hift e d by the tc k inp ut. ? u pdate-dr: data from th e scan chain is ap plied to output pins. 36.8.4 i ntest this ins truct ion selects t he boundary- scan chain a s data regist er for test ing internal logic in t he device. the logi c inputs ar e determin ed by th e boundary-scan chain, and the logic outputs ar e captur ed by the boundary-sca n chain. t he dev ice output pins are driven from the boundary- scan ch ain. th e active stat es are: ? capture-dr: data from the intern al logic is sampled into th e boundary-scan chain. 32058k avr32-01/12 750 at32uc3a ? shi ft- dr: the i nterna l sca n chai n is s h ifte d b y th e tc k inp ut. ? u pdate - dr: d a t a from th e s ca n ch a in is ap plied t o inter n al lo gi c i npu ts. 36.8.5 clamp th is instructi on selects t he bypass register as da ta register. the de vice output pi ns are driven from th e bou nda r y-scan chain. th e active stat es are: ? capture-dr: lo ads a logi c ?0? into the bypa ss register. ? shift- dr: data is sca nned fr om tdi to tdo throug h th e bypass register. 36.8. 6 by pass jt ag instruct ion selecting th e 1-bit bypa ss register for data register. th e active stat es are: ? capture-dr: lo ads a logi c ?0? into the bypa ss register. ? shift- dr: data is sca nned fr om tdi to tdo throug h th e bypass register. 36.9 priva te jtag instructions 36.9.1 notation th e avr32 defines a number of privat e jtag instructions. each i nstructi on is briefl y described in tex t , wi th details fo llowing in table form. ta ble 36- 4 o n pag e 751 sh ows bit patterns to be shifted i n a format like " peb01 ". each characte r corresponds to one bit, and eight bits are group e d together for readability. the rightmo s t bit is alwa ys shifted first, and the leftmo st bit shifte d last . th e symbols us ed ar e shown in tabl e 36-3. i n man y case s, it is n ot require d t o shift all bits throug h th e da ta register. b it patter ns ar e show n usin g the fu ll width o f t he shift register, but the suggested o r required bi ts ar e emphasize d using tabl e 36-3. symb ol description sym bol de s c ri pt i on 0 c onstant low valu e - alwa ys read s as zero. 1 c onstant high value - al wa ys re ads as one. a a n a ddress bit - alwa ys scanne d with th e least significa nt bi t first b a bu sy bi t. reads as one if t h e sab was busy , or zero if it wa s not. see section 36.6.4.1 for d e t ail s o n ho w the bu sy r eport i ng w o rks. d a da t a bi t - alwa ys sca n ned with the leas t sig n ificant bit first. e an error bit. rea d s as o ne if an error occurred , or ze ro if no t. see section 36.6.4.2 for details o n ho w th e error reporting works. p the chip protecte d bit. some device s ma y be se t in a protected state where access to chip inter nals are severely restri cted. see th e documentation fo r th e sp ecific device fo r details. on d e vices witho ut this possibility, this bi t alwa ys re ads as zero. r a directi on bit. set t o o ne to re quest a re ad, se t to zero to req u est a write. s a si z e bit. the si z e enco d in g is d escribe d wh ere use d. x a do n?t car e b it. any value ca n be shifte d in, a nd outpu t da ta shou ld b e ignored. 32058k avr32-01/12 751 at32uc3a bol d t ext . i.e. gi v en t he patt ern " aaaaaaar xxxx xxx x xxxxxx x x xxxxxxx x xx" , th e s hi ft r egi st e r i s 34 bits , bu t t he t e st o r debu g un it ma y cho ose to shift on ly 8 b its " aaaaaaar ". th e followin g describes how to interpret the fi elds in t he instructio n description tables: 36.9. 2 nex u s_ac cess thi s inst ruct ion all ow s nexu s-complia nt access to o n-chi p d ebug reg iste rs thro ug h the sab. ocd r egisters are addressed by t heir register index, as list e d in the avr32 tech nical reference manual. t he 7-bit register inde x and a read/write co nt rol bit, and th e 32-bit data is accessed through t he jtag port. the da t a register is alternat ely interpret ed by t he sab as an add ress register an d a d ata regis- ter. the sab starts in addr e ss mode after the nexus_acce ss instruction is selected, an d toggles betwee n addres s and data mode ea ch ti me a data scan complete s with the busy bit cleared. starting in r un-test/idle , oc d regist ers ar e accessed in the following way: 1. select th e dr scan path. 2. scan in th e 7-bit address fo r the ocd register an d a directio n bit (1=read, 0=write). 3. go to update-d r an d re-ent er select-d r scan. 4. fo r a rea d operation, sca n out t he contents of th e addresse d register. fo r a write oper- ation, scan in th e ne w conten ts of th e register. 5. return to run-test/idle. tabl e 36-4. inst ruction description instruction description ir input value shows th e bit pattern to shift in to ir in t he shift- ir stat e in order to select this instr uctio n. the patte rn is sh o w both in bin ary an d i n hexadecima l for m for convenience. example: 10000 (0x10) ir output value sho ws th e bit pattern shifted ou t of ir in the shift - i r state wh e n t his i nstru c tio n is active. example: peb01 dr si ze sho ws the nu mber of b its in the data register cha in when this instructi on is active. example: 34 b its dr in put value sho ws wh ich bi t patter n to shift into the da ta regi ster in th e shift-dr stat e when this instr uctio n is ac tive . multip l e such li n es m a y exi s t, e. g. t o d i st i ngu ish betw een read s and writes. example: aaaaaaar xxxxxxxx xxxxxxx x xxxxxx xx xx dr o utput value sho ws the bit patter n shifted out of the da t a register in th e shift -dr st a t e w he n th is instr uctio n is ac tive . multip l e such li n es m a y exi s t, e. g. t o d i st i ngu ish betw een read s and writes. exam ple: xx xxxxxxx x xxxxxxx x xxxxxxxx xxxxxxeb 32058k avr32-01/12 752 at32uc3a for an y op eration , t he fu ll 7 bits of th e addr ess mu st be pro vided . for w rit e ope ratio ns, 32 data bit s mu st be provided, o r t he resu lt will be undefi ned. for read operat i ons, shiftin g ma y be te rmi- nate d once th e require d numbe r of bits h ave bee n acquired. 36.9.3 memory_service this inst ruct ion allows access to regist ers in an optional memory service unit . memory servic e registers are addressed by thei r register index, as list e d in t he memory serv ice documentation. th e 7-bit register in dex an d a read/write control bit, and th e 32-bit data is access ed through the jtag port. the memory service unit ma y offer featur es such as crc c alculatio n of memory, deb ug trace support, an d test features. please refe r to th e memo ry s e rvic e unit d ocumentatio n and t h e par t specific documentation for details. the da t a register is alternat ely interpret ed by t he sab as an add ress register an d a d ata regis- ter. the sab starts in addres s mode after the memory_service instruction is selected, an d toggles betwee n addres s and data mode ea ch ti me a data scan complete s with the busy bit cleared. starting in r un-test/idle, memo ry se rvice register s ar e accessed in the following way: 1. select th e dr scan path. 2. scan in th e 7 -bi t add ress fo r t h e memory se rv ice registe r a nd a d irectio n bi t (1 =r ead , 0=write). 3. go to update-d r an d re-ent er select-d r scan. 4. fo r a rea d operation, sca n out t he contents of th e addresse d register. fo r a write oper- ation, scan in th e ne w conten ts of th e register. 5. return to run-test/idle. tabl e 36-5. nexus_access details instructions details ir input value 10000 (0x10) ir output value peb01 dr si ze 34 bits dr in put value (address phase) aaaaaaar xxxxxxxx xxxxxx x x xxxxx xxx xx dr in put value (data read phase) xxxxxxx x xxxxxxx x xxxxxxxx xxxxxxxx xx dr i nput valu e (data writ e phase) dddddddd dddddddd dddddddd dddddddd xx dr output va lue (address phase) xx xxx x xxxx xx xxxxxx xxxxxxxx xxxxxxeb dr o utput val ue (data read phase) eb dddddddd dddddddd dddddddd dddddddd dr o utput val ue (data wr ite phase) xx xxxxxx xx xxxxxxx x xxxxxxx x xxxxxxeb 32058k avr32-01/12 753 at32uc3a for an y op eration , t he fu ll 7 bits of th e addr ess mu st be pro vided . for w rit e ope ratio ns, 32 data bit s mu st be provided, o r t he resu lt will be undefi ned. for read operat i ons, shiftin g ma y be te rmi- nate d once th e require d numbe r of bits h ave bee n acquired. 36.9.4 memory_sized_access this ins t ruction allows access to t he entire service access bu s data ar ea. data are accessed through a 36-bit byte index, a 2-bi t size, a dir ection bit, an d 8, 16, or 32 bits of da ta. not all uni ts mapped on th e sab bu s m a y s upport a l l si ze s o f a ccess e s , e.g . s o m e ma y only s u p por t wo r d accesses. the da t a register is alternat ely interpret ed by t he sab as an add ress register an d a d ata regis- ter. t he sab starts i n address mod e a fter the mem ory_sized_access instruction is selected, and t o ggles betwe en add ress and data mod e each time a dat a scan complet es with the bu sy bit cleared. th e size field is e ncode d as i ta ble 36-7 . tabl e 36-6. memory_service details instructions details ir input value 10100 (0x14) ir output value peb01 dr si ze 34 bits dr in put value (address phase) aaaaaaar xxxxxxxx xxxxxx x x xxxxx xxx xx dr in put value (data read phase) xxxxxxx x xxxxxxx x xxxxxxxx xxxxxxxx xx dr i nput valu e (data writ e phase) dddddddd dddddddd dddddddd dddddddd xx dr output va lue (address phase) xx xxx x xxxx xx xxxxxx xxxxxxxx xxxxxxeb dr o utput val ue (data read phase) eb dddddddd dddddddd dddddddd dddddddd dr o utput val ue (data wr ite phase) xx xxxxxx xx xxxxxxx x xxxxxxx x xxxxxxeb tabl e 36-7. size field semantics size field value acces s size data alignment 00 byte ( 8 bits) addr ess modu lo 4 : data alignment 0: dddddddd xxxxxxx x xxxxx xxx xxxxxxxx 1: xx xxxxxx dddddddd xxxxx xxx xxxxxxxx 2: xx x xxxxx xxxxxxxx dddddddd xxxxxxxx 3: xx x xxxxx xx xxxxxx xxxxxxxx dddddddd 32058k avr32-01/12 754 at32uc3a starting in ru n-test/idle, sab dat a are accessed in the following way: 1. select th e dr scan path. 2. scan i n the 36-bit addre ss of th e data t o access , a 2-bit access si ze, an d a directio n bit (1=read, 0=write). 3. go to update-d r an d re-ent er select-d r scan. 4. fo r a rea d operation, sca n out t he contents of th e addresse d area. for a w rit e opera- tion, scan in t h e ne w contents o f th e area. 5. return to run-test/idle. fo r any operation, the fu ll 3 6 bi ts of th e address mu st b e provided. for writ e operations, 32 d ata bit s mu st be provided, o r t h e resu lt will be undefi ned. for read oper ati ons, shiftin g ma y be te rmi- nate d once th e require d numbe r of bits h ave bee n acquired. 36.9.5 memory_word_access this ins t ruction allows access to t he entire service access bu s data ar ea. data are accessed throug h a 34-bit word index, a direction bit, an d 32 bits of data. th is instructio n is identi cal to memory_sized_acces s except that it always d o es wor d sized accesses. the size fi eld is implied , an d th e two lo we st a ddr ess bi ts are re moved. 01 halfwo rd (1 6 bits) addr ess modu lo 4 : data alignment 0: dddddddd dddddddd x xxxxxxx xxxxxxxx 1: not all owed 2: xx x xxxxx xxxxxxxx dddddddd dddddddd 3: not all owed 10 wo rd (3 2 bit s) addr ess modu lo 4 : data alignment 0: dddddddd dddddddd dddddddd dddddddd 1: not all owed 2: not all owed 3: not all owed 11 reserved n/a tabl e 36-8. memory_sized_a ccess details instructions details ir input value 10101 (0x15) ir output value peb01 dr si ze 39 bits dr in put value (address phase) aaaaaaa a aaaaaaa a aaaaaaaa aaaaaaaa aaaassr dr in put value (data read phase) xxxxxxx x xxxxxxx x xxxxxxxx xxxxxxxx xxxxxxx dr i nput valu e (data writ e phase) dddddddd dddddddd dddddddd dddddddd xxxxxxx dr output va lue (address phase) xxxxxxx xxxxxxxx xxxxxx x x xxxxx xxx xxxxxx eb dr output va lue (dat a read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd dr output va lue (d ata wr ite phase) xxxxxxx xxxxxxx x xxxxxxxx xxxxx xxx xxxxxxeb tabl e 36-7. size field semantics size field value acces s size data alignment 32058k avr32-01/12 755 at32uc3a note: this instruction was p revious ly known as mem ory_access, and is pr ovided fo r back- wards compatibility. the da t a register is alternat ely interpret ed by t he sab as an add ress register an d a d ata regis- ter. the sab star ts in a ddress mode after t he memory_word_access instruction is selected, and t o ggles betwe en add ress and data mod e each time a dat a scan complet es with the bu sy bit cleared. starting in ru n-test/idle, sab dat a are accessed in the following way: 1. select th e dr scan path. 2. scan in th e 34-bit addr ess o f th e data to access, a nd a directio n bit (1=read, 0=write). 3. go to update-d r an d re-ent er select-d r scan. 4. fo r a rea d operation, sca n out t he contents of th e addresse d area. for a w rit e opera- tion, scan in t h e ne w contents o f th e area. 5. return to run-test/idle. fo r any operation, the fu ll 3 4 bi ts of th e address mu st b e provided. for writ e operations, 32 d ata bit s mu st be provided, o r t h e resu lt will be undefi ned. for read oper ati ons, shiftin g ma y be te rmi- nate d once th e require d numbe r of bits h ave bee n acquired. 36.9.6 memory_block_access this instruction allows access to the entire sab data area. up to 32 bits of dat a are accessed at a time, while the addr ess is sequent ially incremented from th e pr eviously used address. i n t h is mo de , t he s a b a ddres s , si z e, and ac c es s direc tio n i s not provided w i th each access . instead, the previo us addr ess is auto-incremented depending on the specif ied size and the pre- viou s oper a tio n re pe ated . t h e address mu st be se t up in advance with mem ory_siz e_acce s s o r mem o ry _ word_a cce ss. it is allowed, but not required, t o shift data afte r shifting the address. th is instructio n is primar ily intended to spee d up larg e quantities of sequenti al wor d accesses. it is possible t o u s e it also f or byte and halfword accesses, but t he ove rhead in th is is case much larger a s 32 bits m us t st i l l be shifted for each access. t h e follo wing se quenc e sh o ul d be use d: tabl e 36-9. memory_word_ac cess details instructions details ir input value 10001 (0x11) ir output value peb01 dr si ze 35 bits dr in put value (address phase) aaaaaaa a aaaaaaa a aaaaaaaa aaaaaaaa aar dr in put value (data read phase) xxxxxxx x xxxxxxx x xxxxxxxx xxxxxxxx xxx dr i nput valu e (data writ e phase) dddddddd dddddddd dddddddd dddddddd xxx dr output va lue (address phase) xxxxxxxx xxxxxxx x xxxxxx xx xxxx xxxx xeb dr o utput val ue (data read phase) xeb dddddddd dddddddd dddddddd dddddddd dr output va lue (data wr ite phase) xxx xxxxxxx x xxxxxxx x xxxxxxx x xxxxxxeb 32058k avr32-01/12 756 at32uc3a 1. us e the memory_size_acce ss or memory_word_acces s to read or wr ite the fir st location. 2. apply memo ry_block_acc ess in the ir scan path. 3. select the dr scan path. the addres s will n o w have incremented by 1, 2, or 4 (corre- spo nding t o th e ne xt byte , halfw ord , o r wor d loc ation). 4. fo r a rea d operation, sca n out t he contents of th e next addresse d location. fo r a write operation, scan in th e ne w contents of t he ne xt addresse d location. 5. g o to upda te-d r. 6. if the block access is n ot complete, return to select-dr sca n and repeat t he access. 7. if the block access is co mplete, return to run-test/idle. for write operat i ons, 32 data bits must be provid ed, or the result will be undef in ed. for read operations , shifting may be ter m inate d onc e t h e r e quir ed num b er of bi ts ha ve been acqu ired. th e overhead using bl ock word acce ss is 4 cycles per 3 2 bi ts o f data, resulti n g in a n 88 % trans- fe r efficiency, or 2. 1 mbytes per seco nd with a 20 mhz tck frequency. 36.9.7 cancel_access if a ve ry slow memo ry location is accessed during a sab memory access, it co uld t ake a very long tim e until the bu sy bit is cleare d, an d the sab b ecome s read y fo r the next operation . the cance l_a cces s in str uc ti on p r ovides a possibility to abort an ongoing transfer and report a timeou t to th e user. when th e ca ncel_a ccess ins t ruc t ion i s se lect ed , the current a c ce s s will be t erminated as soon as possible. t here are no guarantees a bout how long t hi s w il l t a ke, a s t he ha r dwar e may not alw a y s be ab l e to can cel t h e acce ss imme d iat ely. the sab is r eady to respond to a new command w he n th e bu sy bi t cle a rs. tabl e 36-10. memory_block_access details instructions details ir input value 10010 (0x12) ir output value peb01 dr si ze 34 bits dr in put value (data read phase) xxxxxxx x xxxxxxx x xxxxxxxx xxxxxxxx xx dr i nput valu e (data writ e phase) dddddddd dddddddd dddddddd dddddddd xx dr o utput val ue (data read phase) eb dddddddd dddddddd dddddddd dddddddd dr o utput val ue (data wr ite phase) xx xxxxxx xx xxxxxxx x xxxxxxx x xxxxxxeb tabl e 36-11. cancel_acc ess details instructions details ir input value 10011 (0x13) ir output value peb01 dr si ze 1 dr in put value x dr o utput value 0 32058k avr32-01/12 757 at32uc3a 3 6.9. 8 sy nc t hi s instr uctio n all o ws externa l debuggers an d te sters t o measure th e rati o betwee n t he ext ernal jtag clock a nd t he int ernal system clock. the sy nc d at a r egi ster i s a 16 - bi t co unte r that counts d own to zero us ing the internal system clock. th e bu sy bit stay s hig h until the counter reache s zero. starting in ru n-test/idle, sync instr ucti on i s us ed i n t he f ol low in g way: 1. select th e dr scan path. 2. scan in a n 16-bit counter value. 3. go to update-d r an d re-ent er select-d r scan. 4. scan o ut the bu sy bit, an d retry unt il the bu sy bit clears. 5. calculat e an approximation to the internal cloc k spe ed usin g th e elapsed ti me and the counter value. 6. return to run-test/idle. the fu ll 16-b it counter value must be provided when starting the synch operation, or the result will be undefined. when r eading status, sh ifting may be term inated once the required number of bits have bee n acquired. 36.9.9 avr_reset th is instruction a llows a debugger or tester to dire ctly contro l separate reset domain s inside the chip. th e shift register contains one bi t for ea ch controllable reset domain . setting a bi t to one resets that doma in an d hold s it in rese t. settin g a bi t to zer o releases the rese t for that domain. see t he device specific documen ta t i o n for th e nu mbe r o f r eset d o mains, a n d wha t t h ese domains are. for an y operation, all bits must be provided or the result w ill be undefined. 36.9.10 chip_erase this instructio n allows a pr ogramm er to completely erase all nonvolatile me mories in a chip. this will also clea r any security bits t hat are set, so t he device can be accessed normally. in tabl e 36-12. sync_a ccess details instructions details ir input value 10111 (0x17) ir output value peb01 dr si ze 16 bits dr in put value ddddddd d dddddddd dr ou tput va lue xxxxxxxx xxxxxxeb tabl e 36-13. avr_re set details instructions details ir input value 01100 (0x0c) ir output value p0001 dr si ze device specific. dr in put value device specific. dr o utput value device specific. 32058k avr32-01/12 758 at32uc3a devices with out non-volatil e memori es this instruction does nothing , an d appea rs to complete immediately. the erasing of non-volatile mem o ries starts as soon as the chip_e rase instruction is selected. th e chip _erase ins tr uctio n s e lect s a 1 bit bypa ss dat a regist er. a c h ip er ase o per at ion sho u ld b e perf orm ed as: 1. scan in the ha lt inst ruction 2. scan in the va lue 1 to halt t he cpu 3. stay in run-test/idle for 10 tck cycles to let the halt comman d propagat e properly 4. scan in the chip_e r ase instruction 5. keep scanning the chip _erase instruct ion until the bu sy bit is cl eare d and the pro- tectio n bit is cleared. 6. scan in the ha lt inst ruction 7. scan in the va lue 0 to release the cpu 8. return to run-test/idle 9. stay in run-test/idle for 10 tck cycles to let the halt comman d propagat e properly. 36.9.11 halt this instruction allows a programme r to easily stop the cpu to ensure that it doe s not execute inva lid code during programming. th is instruct ion sele cts a 1-bi t hal t register . setting th is bi t to one halt s th e cpu. setting th is bit to ze ro releas es the cpu to r un normal ly. th e value shifte d ou t from the d a ta registe r is on e if the cpu is halted. the ha lt inst ruction can be used in the following way: 10. s can in the va lue 1 to halt t he cpu 11. sta y in run-test/idle for 10 tck cycles to let t he command propagate properly 12. u se an y memor y _ * i nstru ctions to p rogra m t h e device 13. scan in the ha lt instruction 14. s can in the va lue 0 to release the cpu 15. ret ur n to ru n-te st/idle tabl e 36-14. ch ip_erase details instructions details ir input value 01111 (0x0f) ir output value p0b01 w here b is the busy bit. dr size 1 b it dr in put value x dr o utput value 0 32058k avr32-01/12 759 at32uc3a 16. sta y in run-test/idle for 10 tck cycles to let t he command propagate proper ly - the devic e now runs wit h th e ne w code. tabl e 36-15. halt de t ails instructions details ir input value 11100 (0x1c) ir output value p0001 dr size 1 b it dr in put value d dr o utput value d 32058k avr32-01/12 760 at32uc3a 36.1 0 jtag data register s the following device speci f ic regist ers ca n be selec t ed as jtag scan chain dep ending on th e instructio n loaded in t h e jtag instructio n register. additional register s exist, bu t are implicitly describe d in th e functiona l description of th e relevant instructions. 36.10. 1 devic e identification register t he device identifica tion re gister contains a u nique identifier fo r each prod uct. th e register is s elec ted b y the idc od e instructi on , w hic h is th e default instruct ion afte r a jtag reset. 36.10.1.1 dev ice specific id codes th e differen t devic e configurations have differe nt jt ag id code s, as shown in table 36-16. note that if the flash c o ntroller is static ally rese t, the id co de will be undefined . 36 .10. 2 res et r e gist er the reset register is selected by the avr_reset instruction and c o ntains one bit for each reset domain in the device. s e tting ea ch bit to one w ill keep that do mai n rese t un ti l t he bit i s c lea re d. ms b lsb bit 31 28 27 12 11 1 0 devi ce id revision part number manufacturer id 1 4 b its 16 bits 1 1 bits 1 b it re vision th is is a 4 bit number identifying the revisio n of the component. re v a = 0x0, b = 0x1, etc. part number th e part number is a 16 bi t code identifying the component. manufacturer id t h e manufacturer id is a 1 1 bit cod e id entifyin g th e manufactu r er. t h e jta g manufacturer id f or a tme l is 0x01 f. tabl e 36-16. device and jtag id devic e name jtag id code ( r is the r evision number) at32uc3a0512 0xr1edc03f at32uc3a0256 0xr1edf03f at32uc3a0128 0xr1ee203f at32uc3a1512 0xr1edd03f at32uc3a1256 0xr1ee003f at32uc3a1128 0xr1ee303f lsb bit 4 3 2 1 0 devi ce id ocd app reserved reserved cpu 32058k avr32-01/12 761 at32uc3a note: thi s register i s primarily intended for compatibilit y with other avr32 de vices. certain oper- ations may no t function correc tly when part s of th e system are rese t. it is g enerally recommended to o nly write 0x 11111 o r 0x00000 t o these bits to en sure no unint ended side effects occur. 36.10. 3 boundary-sc an chain the boundar y -scan chai n has th e c a pab il it y of d rivin g a n d obse rving the logic leve ls on the dig- it al i/ o pin s, as well as driving and ob serving th e l o gic l e vels betwe en t he di gita l i/ o pi n s a n d the inter nal logic. typically, output value, ou tput enable, and input da t a are all availabl e in the boundar y scan chain. t he bou nda ry sc an chai n is descr ib ed i n th e bds l (boundar y scan description languag e) file availabl e at th e atmel we b site. 36.11 sab a ddress map the ser v ice access bus (sab ) giv es t he user access to th e inte rnal a d dress space a nd ot he r features throug h a 36 bits a ddre ss space. th e 4 m sbs id entify the slav e number , while th e 32 lsbs a re decode d within th e slave?s addres s space. th e sa b slaves are show n in tabl e 36-17. cpu cpu app h sb and pb buses ocd on-chip debug logic an d registers rserved n o effect tabl e 36-17. sab slaves, addresses and descriptions. sl ave a dd r es s [ 35 : 3 2] de scripti on unallocated 0x0 intentionally unallocated ocd 0x1 ocd registers hsb 0x4 hsb memo ry space, as seen by the cpu hsb 0x5 alternativ e mapping fo r hsb space, fo r compatibility with other av r32 devices. memory service unit 0x6 memor y serv ice unit registers reserved other unused 32058k avr32-01/12 762 at32uc3a 37. boot sequence this cha pter su mmar izes the boot sequence of the at32uc3a . the behavio ur after power-up is controlled by th e pow er manager. for specific details, re f er to sect io n 13. ?power manage r (pm)? on pa ge 53 . 37.1 start ing of clocks after power-up, the de vice will be held in a reset state by the po we r-on reset circuitr y, until th e power has st a bilized throu gho ut th e d evic e. on ce the power has stabilize d, th e de vice will use the internal rc oscill at or as clock sourc e. on s ys tem start-up, the pl ls ar e dis ab led. all clock s to a ll modul es are running. no cl ocks have a divide d freq uency, all parts of the syste m re cieves a clock with the sa me fr equen cy as the internal rc os cillator. 37.2 fet ch ing of initial instructions aft er reset has been rele as ed, the avr 32 uc cpu star ts fe tc hing in st ru cti on s f ro m the reset address , w hi c h is 0x8000_0000. this addres s poin ts to the fi rst addre ss in the intern al flas h. the code read from the internal flash is free to config u re the system to use for example the plls, to divi de the fre quency of the clock routed to some of the peripheral s, and to gate the clocks to un u sed peripherals. 32058k avr32-01/12 763 at32uc3a 38. e lectrical characteri stics 38.1 absolute maxi mum ratings* operati n g temperature. -40? c to +85 ?c *notice : stre ss es be yond thos e l ist ed und er ?absolute maximum ratin g s? may cause perm a nent dam- age to the device. this is a str e ss rating only and functiona l op erat io n of the de vi ce at thes e or other co ndit io ns beyond tho se in dic ated in the operatio nal sections of this spec ific ation is no t impl ie d. exposur e to abs ol ute maximum rati ng cond itio ns for ext end ed perio ds may affect de vice reliability. storage tempe rat ur e . -60c to +150 c volta ge on input pin with resp ect to grou nd e xce pt for pc0 0, pc01, pc02, pc03 , pc04, pc05. ......................................................... -0.3v to 5.5v volta ge on input pin with resp ect to grou nd for pc 00, pc 01, pc 02, pc 03, pc 04, pc05. .................................................................... - 0 .3 v to 3.6v maxi mum operating volta ge (vddco re, vddpll) . 1.9 5v maxi mum operating volta ge (vddio, vddin, vddana) .3.6v to t a l dc outp ut curre nt on all i/o pi n for tqfp 100 pa ckag e . 370 ma for lqgp 144 pa ckag e . 470 m a 32058k avr32-01/12 764 at32uc3a 38.2 d c characteristics the following characte ristics are applicab le to the operating temperature range: t a = -4 0c to 85c, un less othe rwise spec- ifie d a nd are certified fo r a junction temperatur e up to t j = 10 0 c. tabl e 38-1. dc chara cteristics symbol parameter condition min. typ. max units v vddcor e dc su pp ly core 1.65 1.95 v v vddpll dc supp ly pll 1.65 1.95 v v vddio dc supply periphera l i/os 3.0 3.6 v v ref an alo g refe r enc e vo lta ge 2.6 3.6 v v il inpu t low-level voltage -0.3 +0.8 v v ih inp ut high-level voltage all gpios except fo r pc00, pc01, pc02, pc03 , pc04 , pc05. 2.0 5.5v v pc 00, pc01 , pc02 , pc03 , pc04, pc05. 2.0 3.6v v v ol output l ow-level voltage i ol =-4ma fo r pa0-p a20, pb0, pb4 -pb9, pb11-pb18, pb24-pb26, pb29-pb31, px0-px39 0.4 v i ol =-8ma for pa21-p a30, pb1-pb3, pb10, p b 19-pb23, pb 27-pb28, pc0- pc5 0.4 v v oh output hig h-level voltage i oh =4ma for pa0-p a20, pb 0, pb4-pb9, pb11-pb18, pb24-pb26, pb29-pb31, px0-px39 v vddio - 0.4 v i oh =8ma for pa21-p a30, pb1-pb3, pb10, p b 19-pb23, pb 27-pb28, pc0- pc5 v vddio - 0.4 v i ol output l ow-leve l current pa0-p a20, pb0, pb4-pb9, pb11-pb18, pb24-pb26, pb29-pb31, px0-px39 -4 ma pa21-pa 30, pb1-pb3, pb10, pb19- pb23, p b 27-pb28, pc0-pc5 -8 ma i oh output hi gh-level current pa0-p a20, pb0, pb4-pb9, pb11-pb18, pb24-pb26, pb29-pb31, px0-px39 4 ma pa21-pa 30, pb1-pb3, pb10, pb19- pb23, p b 27-pb28, pc0-pc5 8 ma i leak inpu t leakag e current pull up resistors disabled 1 a c in input cap acitance tqfp100 package 7 pf lqfp144 package 7 pf r pullup pull-up re sistance all g p io and reset_n pin. 10k 15k ohm 32058k avr32-01/12 765 at32uc3a 38.3 r egulator characteristics tabl e 38-2. electr ical characteristics tabl e 38-3. decouplin g requirements 38.4 analog characteristics tabl e 38-4. electr ical characteristics tabl e 38-5. decouplin g requirement s 38.4.1 b od tabl e 38-6. bodlevel values the values in ta ble 38-6 de scr i be s t he val ues o f t he bo dl evel in the flash fgpfr register. symbol pa rameter condi ti on min. ty p. max. un its v vddin supply voltage (input) 3 3.3 3.6 v v vddout supp ly vo ltag e (o utpu t) 1.81 1. 85 1.89 v i out maximu m dc output current with v vd din = 3.3v 100 ma maximu m dc output current with v vd din = 2.7v 90 ma i scr static curren t of internal regulator low powe r mo de (stop, d eep stop or st at ic) at t a =25c 10 a symbol parameter condition typ. techno. units c in1 input reg u lator capa citor 1 1 npo nf c in2 input reg u lator capa citor 2 4.7 x7r uf c out1 outp ut regulator ca pacitor 1 470 npo pf c out2 outp ut re gulator ca pacitor 2 2.2 x 7r uf symbol parameter condition min. typ. max. units v advref ana log v o ltag e r efe r enc e (in put) 2.6 3.6 v symbol parameter condition typ. techno . units c vref1 volta ge refere nce capa citor 1 10 - nf c vref2 volta ge refere nce capa citor 2 1 - uf bodlevel value typ. typ. typ. units. 00 0000b 1.40 1.47 1.55 v 01 0111b 1.45 1.52 1.6 v 01 1111b 1. 55 1.6 1 .65 v 10 0111b 1.65 1.69 1.75 v 32058k avr32-01/12 766 at32uc3a tabl e 38-7. bod timing 38.4. 2 por tabl e 38-8. electr ical characteristic symbol parameter t est conditions typ. max. units. t bod minimum time with vddcor e < vbod to detec t po we r failu re fal l ing v ddc ore fro m 1. 8v to 1.1v 300 800 ns symbol parameter tes t conditions min. typ. max. units. v ddrr vddcor e ris e rate to ensure power-on-reset 0.01 v/ms v ssfr vddcore fall rate to e nsure po w er- on-res et 0. 01 4 00 v / ms v por+ rising threshol d voltage: voltage up to which device is kep t unde r reset by por on rising vddcore ri sing vddcore: v restart -> v por+ 1.35 1.5 1.6 v v por- fal lin g threshold voltage : voltage wh en por resets devi c e on falling vddcore falling v ddcore: 1.8v -> v por+ 1.25 1.3 1.4 v v resta rt on falling vdd core, volt age must go down to th is valu e befo r e su pp ly c an rise ag ain to ensure reset sig nal is release d at v por+ falling v ddcore: 1.8v -> v restart -0.1 0.5 v t por mini mu m tim e with v d dcore < v por- falling v ddcore: 1.8v -> 1.1v 15 us t rst time for reset signal to b e propagated to system 200 400 us 32058k avr32-01/12 767 at32uc3a 38.5 pow er consumption the va lues in table 38- 9 and table 38-10 on pag e 769 ar e measured values of power con- sumption wit h operating condition s as follows: ?v ddio = 3 .3v ?v ddcore = v ddpll = 1.8v ?t a = 2 5 c, t a = 8 5c ?i/o s ar e configured in in put, pull-up enabled. figur e 38-1. measurement setup interna l voltage regulator amp0 amp1 vddana vddio vddin vddout vddcore vddpll 32058k avr32-01/12 768 at32uc3a th ese figure s rep rese nt th e p owe r consumpt ion measure d o n th e powe r supplies. tabl e 38-9. power consumption for differen t modes mode conditions typ. unit active ty p : ta =2 5 c c pu r unning fro m flas h (1) . vddin=3.3 v. vddcore =1.8v. cpu clo cked from p l l0 at f mhz voltag e regulator is o n. xi n0 : extern al clock. (1) xin1 stop ped. xin3 2 stopped pll0 running all pe ripheral cloc ks activated. gpios o n intern al pull-up. jta g un c onn ecte d with ex t p u ll-u p. f = 12 mhz 9 ma f = 24 mhz 15 ma f = 36mhz 20 ma f = 50 m hz 28 ma f = 66 mhz 36.3 ma idle ty p : ta = 25 c c pu r unning fro m flas h (1) . vddin=3.3 v. vddcore =1.8v. cpu clo cked from p l l0 at f mhz voltag e regulator is o n. xi n0 : extern al clock. xin1 stop ped. xin3 2 stopped pll0 running all pe ripheral cloc ks activated. gpios o n intern al pull-up. j t a g unconnecte d with ex t p u ll-u p. f = 12 mhz 5 ma f = 24 mhz 10 ma f = 36mhz 14 ma f = 50 m hz 19 ma f = 66 mhz 25.5 ma frozen ty p : ta = 25 c c pu r unning fro m flas h (1) . cpu clo cked from p l l0 at f mhz voltag e regulator is o n. xi n0 : extern al clock. xin1 stop ped. xin3 2 stopped pll0 running all pe ripheral cloc ks activated. gpios o n intern al pull-up. j t a g unconnecte d with ex t p u ll-u p. f = 12 mhz 3 ma f = 24 mhz 6 ma f = 36 mhz 9 ma f = 50 mhz 13 ma f = 66 mhz 16.8 ma standby ty p : ta = 25 c c pu r unning fro m flas h (1) . cpu clo cked from p l l0 at f mhz voltag e regulator is o n. xi n0 : extern al clock. xin1 stop ped. xin3 2 stopped pll0 running all pe ripheral cloc ks activated. gpios o n intern al pull-up. j t a g unconnecte d with ex t p u ll-u p. f = 12 mhz 1 ma f = 24 mhz 2 ma f = 36 mhz 3 ma f = 50 mhz 4 ma f = 66 mhz 4.8 ma 32058k avr32-01/12 769 at32uc3a 38.6 clock characteristics th ese parameters ar e give n in the following conditions: stop ty p : ta = 25 c. cpu is in stop mode gpios o n intern al pull-up. all pe ripheral cloc ks de-activated. dm a nd dp pins conn ected to ground. xin0,xi n1 and xin2 are stop ped on am p0 47 ua on am p1 40 ua deepstop typ : ta = 2 5 c.cpu is i n deepstop mode gpios o n intern al pull-up. all pe ripheral cloc ks de-activated. dm a nd dp pins conn ected to ground. xin0,xi n1 and xin2 are stop ped on am p0 36 ua on am p1 28 ua static typ : ta = 2 5 c . cpu is in static mode gpios o n intern al pull-up. all pe ripheral cloc ks de-activated. dm a nd dp pins conn ected to ground. xin0,xi n1 and xin2 are stop ped on am p0 25 ua on am p1 14 ua 1. core freq u ency is ge nerated from xin 0 us ing the pl l so that 14 0 mhz < fpll0 < 160 mhz a nd 10 mhz < fxin0 < 1 2mhz tabl e 38-9. power consumption for differen t modes mode conditions typ. unit tabl e 38-10. power consumptio n by periphera l in activ e mode peripheral typ. unit gpio 37 a/mhz smc 10 sdramc 4 adc 18 ebi 31 intc 25 twi 14 ma cb 45 pdca 30 pwm 36 rtc 7 spi 13 ssc 13 tc 10 usart 35 usb 45 32058k avr32-01/12 770 at32uc3a ?v ddcore = 1 .8v ? ambient temperature = 2 5c 38.6.1 cpu/hsb clo ck characteristics 38.6.2 pb a clock characteristics 38.6.3 pbb clo ck characteristics 38.7 cr ystal oscillat or characteristis the following characteristics a r e applicabl e t o th e op eratin g tempera ture r ange: t a = -40c t o 85c and worst case of power supply, unle ss otherwis e specified. 38.7. 1 32 k hz osci llator ch arac te rist ics note: 1. c l is the e quiva lent load capacitance. tabl e 38-11. core clock waveform parameters s ymb ol p ar a m e t er co nd itions m in m ax uni ts 1/(t cpcpu ) cpu cl ock frequency 66 mhz t cpcpu cpu cl ock period 15,15 ns tabl e 38-12. pba clock wa veform parameters s ymb ol p ar a m e t er co nd itions m in m ax uni ts 1/(t cppba ) pba clo ck frequency 66 mhz t cppba pba clo ck period 15,15 ns tabl e 38-13. pbb clock wa veform parameters s ymb ol p ar a m e t er co nd itions m in m ax uni ts 1/(t cppbb ) pbb clo ck frequency 66 mhz t cppbb pbb clo ck period 15,15 ns tabl e 38-14. 32 k hz osc illator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crysta l oscillator frequency 32 7 68 hz c l equival ent loa d capacitance 6 12.5 pf t st star tup time c l = 6 pf (1) c l = 1 2.5pf (1) 600 1200 ms i osc cu rrent c onsumption active mode 1.8 a stand by mo de 0.1 a 32058k avr32-01/12 771 at32uc3a 38.7.2 main oscillators characteristics 38.7.3 pll cha racteristics tabl e 38-15. main oscillator chara cteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crysta l oscillator frequency 0.45 16 mhz c l1 , c l2 interna l l oad capacitance (c l1 = c l2 ) 12 pf du ty cycle 40 50 60 % t st star tup time 8 mhz 4 ms 1/(t cpxin ) x in clock frequency extern al clock 50 mhz crystal 0.45 16 mhz t chxin xin clo ck high half-period 0.4 x t cpxin 0.6 x t cpxin t clxin xin clo ck lo w half-period 0.4 x t cpxin 0. 6 x t cpxin c in xin i nput capacitance 7 pf tabl e 38-16. phase lock loo p c ha ract eri stics symbol parameter conditions min typ max unit f out output frequency 80 240 mhz f in input frequency 4 16 mhz i pll cu rrent c onsumption active mode (fout=80mhz) 250 a active mode (fout=240mhz) 600 a 32058k avr32-01/12 772 at32uc3a 38.8 a dc characteristics notes: 1. corr esponds to 13 cloc k cycles at 5 mhz: 3 cloc k cycles fo r trac k and hold ac quisition time and 10 clock cycles for c o nver s ion. 2. corr esponds to 15 cloc k cycles at 8 mh z: 5 cloc k cycles fo r t rac k and hold acqu isition time and 10 clock cycles for conversi on. note: ad vref should be connected to gn d to avoid extra consumptio n in ca se adc is no t used. tabl e 38-17. channel conversion time and ad c clock parameter conditions min typ max units adc clo ck frequency 10-bi t resoluti on mode 5 mhz adc clo ck frequency 8 -bit resolution mode 8 mhz startu p time return from i d le mode 20 s trac k and ho ld acquisition time 600 ns conversion time adc cloc k = 5 mhz 2 s conversion time adc cloc k = 8 mhz 1.25 s through put rate adc cloc k = 5 mhz 384 (1) ksps through put rate adc cloc k = 8 mhz 533 (2) ksps tabl e 38-18. extern al voltage refere nce input parameter conditions min typ max units advr ef input vo ltage range 2.6 vddana v advref avera ge current o n 13 samples with adc cl ock = 5 mhz 200 250 a current cons umption on vddana 1.25 ma tabl e 38-19. analo g inpu ts parameter min typ max units input voltage range 0 v advref input le aka ge current 1 a input cap acitance 17 pf tabl e 38-20. transfer characteristics i n 8-bit mode parameter conditions min typ max units res o lut ion 8 bit absolute accu racy f=5mhz 0.8 lsb f=8mhz 1.5 lsb integr al non-linearity f=5mhz 0.35 0.5 lsb f=8mhz 0.5 1.0 lsb differentia l non-linearity f=5mhz 0.3 0.5 lsb f=8mhz 0.5 1.0 lsb offset error f=5mhz -0.5 0.5 lsb ga in error f=5mhz -0.5 0.5 lsb 32058k avr32-01/12 773 at32uc3a tabl e 38-21. transfer characteristics i n 10-b it mode parameter conditions min typ max units res o lut ion 10 bit absolute accu racy f=5mhz 3 lsb integr al non-linearity f=5mhz 1.5 2 lsb differentia l non-linearity f=5mhz 1 2 lsb f=2.5mhz 0.6 1 lsb offset error f=5mhz -2 2 lsb gain error f=5mhz -2 2 lsb 32058k avr32-01/12 774 at32uc3a 38.9 e bi timings t hese timing s ar e g ive n f o r worst c as e pr oce ss, t = 85 ? c, vddcor e = 1.65v, vddio = 3v an d 40 p f load capacitance. note: 1. t he maximum freq u ency of the smc interface is the same as the max frequ ency fo r the hsb. note: 1. h old l e ngth = tota l cycl e dura ti on - setu p d uratio n - pu lse duration. ?hol d l ength? is fo r ?n cs rd ho ld length ? or ?nrd ho ld len gt h ?. tabl e 38-22. smc c lock signal. symbol parameter max (1) units 1/(t cpsmc ) sm c c ontroll e r c loc k fr e q uency 1/(t cpcpu ) mhz tabl e 38-23. smc re ad signal s wi th hold settin gs symbol parameter min units n rd contro ll ed (read _m ode = 1) smc 1 dat a setu p b e fo r e nr d hi gh 12 ns smc 2 data hold after n rd high 0 smc 3 nrd high to nbs0/ a0 change (1) nr d ho ld length * t cpsmc - 1.3 smc 4 nrd high to nbs1 change (1) nr d ho ld length * t cpsmc - 1.3 smc 5 nrd high to nbs2/ a1 change (1) nr d ho ld length * t cpsmc - 1.3 smc 6 nrd high to nbs3 change (1) nr d ho ld length * t cpsmc - 1.3 smc 7 nrd high to a2 - a25 change (1) nr d ho ld length * t cpsmc - 1.3 smc 8 nrd high to n c s inactive (1) (nrd hold lengt h - ncs r d hold length ) * t cpsmc - 2.3 smc 9 nrd pulse width n rd puls e length * t cpsmc - 1.4 n rd c o ntro ll ed (read _m ode = 0) smc 10 data setu p before nc s high 11.5 ns smc 11 data hold after ncs high 0 smc 12 ncs high to nbs0/a0 change (1) ncs r d hold length * t cpsmc - 2.3 smc 13 ncs high to nbs0/a0 change (1) ncs r d hold length * t cpsmc - 2.3 smc 14 ncs high to nbs2/a1 change (1) ncs r d hold length * t cpsmc - 2.3 smc 15 nc s hig h t o nbs3 ch ange (1) ncs r d hold length * t cpsmc - 2.3 smc 16 ncs high to a2 - a25 change (1) ncs rd hold length * t cpsmc - 4 smc 17 ncs high to nr d inactive (1) ncs rd hold length - n r d hold length)* t cpsmc - 1.3 smc 18 ncs pulse width ncs rd pulse length * t cpsmc - 3.6 32058k avr32-01/12 775 at32uc3a note: 1. h old le ngth = tota l cycle durati on - setu p durati on - pu lse duration . ?hol d length ? is fo r ?ncs wr ho ld le ngth? or ?nw e ho ld len gth" tabl e 38-24. smc r e ad sign als with no ho ld settings symbol parameter min units n rd contro ll ed (read _m ode = 1) smc 19 dat a s et up before nr d high 13.7 ns smc 20 data ho ld after nrd high 1 n rd contro ll ed (read _m ode = 0) smc 21 data setup before ncs high 13.3 ns smc 22 data ho ld after ncs high 0 tabl e 38-25. smc wr ite signals with ho ld settings symbol parameter min units n rd contro ll ed (read _m ode = 1) smc 23 dat a out va lid before nwe high (nwe pul s e length - 1) * t cpsmc - 0 .9 ns smc 24 data out valid after nwe high (1) nw e hold le ngth * t cpsmc - 6 smc 25 nw e high to nb s0/a0 change (1) nwe hol d lengt h * t cpsmc - 1 .9 smc 26 nw e high to nb s1 change (1) nwe hol d lengt h * t cpsmc - 1 .9 smc 29 nw e high to nb s2/a1 change (1) nwe hol d lengt h * t cpsmc - 1 .9 smc 30 nw e high to nb s3 change (1) nwe hol d lengt h * t cpsmc - 1 .9 smc 31 nw e high to a2 - a25 change (1) nwe hol d lengt h * t cpsmc - 1 .7 smc 32 nw e high to nc s inactive (1) (nwe hold length - n cs wr hold length)* t cpsmc - 2 .9 smc 33 nw e pulse width nwe pulse length * t cpsmc - 0 .9 n rd c o ntro ll ed (read _m ode = 0) smc 34 dat a out va lid before ncs high (nc s wr puls e length - 1)* t cpsmc - 4 .6 ns smc 35 data out valid after ncs high (1) ncs wr hold length * t cpsmc - 5.8 smc 36 nc s high to nw e inactive (1) (n cs w r hold leng t h - nw e ho ld le ngth )* t cpsmc - 0 .6 32058k avr32-01/12 776 at32uc3a figur e 38-2. smc signals for ncs control l ed accesses. tabl e 38-26. smc wr ite signals with n o hold settings (n w e controlled only). symbol parameter min units smc 37 nw e ris ing to a2 -a25 valid 5.4 ns smc 38 nw e ris ing to n bs0/a0 valid 5 smc 39 nw e ris ing to n bs1 change 5 smc 40 nw e ris ing to a1/n bs2 change 5 smc 41 nw e ris ing to n bs3 change 5 smc 42 nw e ris ing to ncs rising 5.1 smc 43 data out va lid before nwe rising (nwe pul s e length - 1) * t cpsmc - 1 .2 smc 44 data out valid after nwe rising 5 smc 45 nw e pulse width nwe pulse length * t cpsmc - 0 .9 nrd ncs d0 - d15 nwe a2-a25 a0/a1/nbs[3:0] smc34 smc35 smc10 smc11 smc16 smc15 smc22 smc21 smc17 smc18 smc14 smc13 smc12 smc18 smc17 smc16 smc15 smc14 smc13 smc12 smc18 smc36 smc16 smc15 smc14 smc13 smc12 32058k avr32-01/12 777 at32uc3a figur e 38-3. smc signals for nrd and nr w controlled accesses. 38.9.1 sdra m signals th ese timi ngs ar e given fo r 10 p f loa d o n sdck and 40 p f o n o the r signals. note: 1. t he maximum frequ ency of the sdramc inter face is the same as the max freq uency fo r the hsb. nrd ncs d0 - d15 nwe a2-a25 a0/a1/nbs[3:0] smc7 smc19 smc20 smc43 smc37 smc42 smc8 smc1 smc2 smc23 smc24 smc32 smc7 smc8 smc6 smc5 smc4 smc3 smc9 smc41 smc40 smc39 smc38 smc45 smc9 smc6 smc5 smc4 smc3 smc33 smc30 smc29 smc26 smc25 smc31 smc44 tabl e 38-27. sdr am clock signal. symbol parameter max (1) units 1/(t cpsdck ) s dram controlle r clock frequency 1/(t cpcpu ) mhz tabl e 38-28. sdr am clock signal. symbol parameter min units sdramc 1 sdcke high before s dck rising edge 7.4 ns sdramc 2 sdcke low after s dck rising edge 3.2 sdramc 3 sdcke low before s dck rising edge 7 sdramc 4 sdcke high after s dck rising edge 2.9 sdramc 5 sdc s low be for e sdc k risi ng e d ge 7.5 sdramc 6 sdcs h ig h aft er s dck r is in g edge 1.6 sdramc 7 ras lo w befor e sdck risi ng edge 7.2 sdramc 8 r as h ig h af ter sdck risin g edge 2.3 sdramc 9 sda10 change befor e sdck risin g edge 7.6 sdramc 10 sda10 change after sd c k ris ing edge 1.9 32058k avr32-01/12 778 at32uc3a sdramc 11 addres s chang e befor e sdck rising edge 6.2 ns sdramc 12 addres s chang e after sdck risin g edge 2.2 sdramc 13 ba nk change befor e sdck risi ng edge 6.3 sdramc 14 ban k c hange after sdc k risin g edge 2.4 sdramc 15 cas lo w befor e sdck risi ng edge 7.4 sdramc 16 c as h ig h af ter sdck risin g edge 1.9 sdramc 17 dqm change befor e sdck risi ng edge 6.4 sdramc 18 dqm change after sd c k ris ing edge 2.2 sdramc 19 d0-d 15 in setu p befor e sdck risin g edge 9 sdramc 20 d0-d15 in hold after s dck ri sing edge 0 sdramc 23 sdwe low before s d ck ris ing edge 7.6 sdramc 24 sdwe hi g h after sdck rising edge 1.8 sdramc 25 d0-d15 out va lid befor e sdck risin g edge 7.1 sdramc 26 d0-d15 out valid after sd c k ris ing edge 1.5 tabl e 38-28. sdr am clock signal. symbol parameter min units 32058k avr32-01/12 779 at32uc3a figur e 38-4. sdramc signals relative to sd ck. ras a0 - a9, a11 - a13 d0 - d15 read sdck sda10 d0 - d15 to write sdramc 1 sdcke sdramc 2 sdramc 3 sdramc 4 sdcs sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 7 sdramc 8 cas sdramc 15 sdramc 16 sdramc 15 sdramc 16 sdwe sdramc 23 sdramc 24 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 11 sdramc 12 sdramc 11 sdramc 12 sdramc 11 sdramc 12 ba0/ba1 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 17 sdramc 18 sdramc 17 sdramc 18 dqm0 - dqm3 sdramc 19 sdramc 20 sdramc 25 sdramc 26 32058k avr32-01/12 780 at32uc3a 38.10 j tag timings 38.10.1 jta g interfa ce signals note: 1 . v vddio from 3.0v t o 3.6 v , maxi mu m ext er n al capac it or = 4 0pf tabl e 38-29. jtag inte rfac e ti ming sp ecification s ymb ol pa ra m e ter cond itions m in max uni ts jtag 0 tc k lo w half-period (1) 6 ns jtag 1 tc k hi gh half-period (1) 3 ns jtag 2 tck period (1) 9 ns jtag 3 tdi, tms setup be fore tck high (1) 1 ns jtag 4 tdi, tm s hold after tck high (1) 0 ns jtag 5 td o hold time (1) 4 ns jtag 6 tc k low to tdo valid (1) 6 ns jtag 7 de vice inputs setu p time (1) ns jtag 8 de vice inputs hold time (1) ns jtag 9 de vice outp uts ho ld time (1) ns jtag 10 tck to d e vice outputs valid (1) ns 32058k avr32-01/12 781 at32uc3a figur e 38-5. jtag inte rfac e sig na ls 38.1 1 spi characteristi cs figur e 38-6. spi master mode wit h (cpol = ncp ha = 0 ) or (cpol= nc pha= 1) tck jtag 9 tms/tdi tdo device outputs jtag 5 jtag 4 jtag 3 jtag 0 jtag 1 jtag 2 jtag 10 device inputs jtag 8 jtag 7 jtag 6 spck miso mosi spi 2 spi 0 spi 1 32058k avr32-01/12 782 at32uc3a figur e 38-7. sp i maste r mode wit h (cpol= 0 a nd ncpha=1) o r (cpol= 1 an d ncph a=0) figur e 38-8. spi slav e mode wit h (cpol= 0 and ncpha=1) o r (cpo l=1 an d ncpha=0) figur e 38-9. spi slave mode with (cpol = n cph a = 0 ) o r (cpo l= nc pha= 1 ) spck miso mosi spi 5 spi 3 spi 4 spck miso mosi spi 6 spi 7 spi 8 spck miso mosi spi 9 spi 10 spi 11 32058k avr32-01/12 783 at32uc3a notes: 1. 3 .3v domain: v vddio f r o m 3 . 0v t o 3. 6v , m aximum e xterna l ca pac i tor = 4 0 p f. 2. t cpmc k : m a ster clock perio d in ns. 38.12 ma cb characteristics notes: 1. f: mck fr equen cy (mhz) 2 . v vddio fr o m 3. 0v t o 3 . 6 v , m a x i mu m e xter na l c ap aci t o r = 2 0 pf tabl e 38-30. spi timing s symbol parameter conditions min max units spi 0 miso setup time be fo re spck rises (master) 3.3v domain (1) 22 + (t cpmck )/2 (2) ns spi 1 miso hold time after spck r i se s ( m ast e r) 3.3v d om ain (1) 0 ns spi 2 spck ri sing to mosi dela y (master) 3.3v domain (1) 7 ns spi 3 miso setup time be fo re spck f alls (master) 3.3 v domain (1) 22 + (t cpmck )/2 (2) ns spi 4 miso hold time after spck falls (master) 3 .3v domain (1) 0 ns spi 5 sp ck fa lling to m osi dela y (mast er) 3. 3v domain (1) 7 ns spi 6 spck fa lling to miso dela y (slave) 3 .3v domain (1) 26.5 ns spi 7 mosi setup time be fo re spck rises (slave) 3 .3v domain (1) 0 ns spi 8 mosi hold time after spck ri ses (slave) 3 .3v domain (1) 1.5 ns spi 9 spck ri sing to miso dela y (slave) 3 .3v domain (1) 27 ns spi 10 mosi setup time be fo re spck fa lls (slave) 3.3v domain (1) 0 ns spi 11 mosi hold time after spck fall s (slav e) 3.3 v d omain (1) 1 ns tabl e 38-31. etherne t mac signals symbol parameter conditions min (ns) max (ns) emac 1 setup fo r emdi o from emdc rising lo ad: 20pf (2) emac 2 hold fo r emdio from emdc rising lo ad: 20pf (2) emac 3 emdi o t ogg ling fro m e mdc fa lling l oad : 2 0pf (2) tabl e 38-32. etherne t mac mi i specif ic signals symbol parameter conditions min (ns) max (ns) emac 4 setup fo r ecol from etxck rising load : 20pf (1) 3 emac 5 hold fo r ecol from etxck rising load : 20pf (1) 0 emac 6 setup fo r ecrs from etxck rising load : 20pf (1) 3 emac 7 hold fo r ecrs from etxck rising load : 20pf (1) 0 emac 8 etxer t oggl ing from etxck rising load : 20pf (1) 15 emac 9 etxen t oggl ing from etxck rising load : 20pf (1) 15 emac 10 etx t oggli ng from etxck rising load : 20pf (1) 15 emac 11 setup fo r erx from erxck load : 20pf (1) 1 32058k avr32-01/12 784 at32uc3a note: 1 . v vddio from 3.0v to 3.6 v , maximum external ca pacitor = 20 pf figur e 38-10. etherne t ma c mi i mo de emac 12 hold fo r erx fr om erxck l oad: 20pf (1) 1.5 emac 13 setup fo r erxer from erxck l oad: 20pf (1) 1 emac 14 hold fo r erxer from erxck l oad: 20pf (1) 0.5 emac 15 setup fo r erxd v fr om erxck l oad: 20pf (1) 1.5 emac 16 hold fo r erxd v from erxck l oad: 20pf (1) 1 tabl e 38-32. etherne t mac mi i specif ic signals symbol parameter conditions min (ns) max (ns) emdc emdio ecol ecrs etxck etxer etxen etx[3:0] er x ck erx[3:0] erxer erxdv emac 3 emac 1 emac 2 emac 4 emac 5 emac 6 emac 7 emac 8 emac 9 emac 10 emac 11 emac 12 emac 13 emac 14 emac 15 emac 16 32058k avr32-01/12 785 at32uc3a figur e 38-11. etherne t mac rmii mode 38.13 flash characteristics the following table gives t he device maximum operat ing frequency depend ing on the field fws o f the fl ash fsr register. this fi el d define s the number of wait states required to access the flas h memory. tabl e 38-33. etherne t mac rmii specif ic signals sym bol pa rame t er mi n (n s) ma x (ns) emac 21 etxen togg ling from e refck rising 7 14.5 emac 22 etx togg l ing from erefck rising 7 14.7 emac 23 setup fo r erx from erefck 1.5 emac 24 hold fo r erx from erefck 0 emac 25 setu p f o r erxer fr o m erefck 1 .5 emac 26 hold fo r erxe r from erefck 0 emac 27 se tup fo r ecrsdv f ro m e r efck 1.5 emac 28 hold fo r ecrs dv fro m erefck 0 erefck etxen etx[1:0] erx[1:0] erxer ecrsdv emac 21 emac 22 emac 23 emac 24 emac 25 emac 26 emac 27 emac 28 tabl e 38-34. flash wai t states fws r ead oper at ions maximu m oper at ing f r equen c y (mhz) 0 1 cycle 33 1 2 cyc les 66 32058k avr32-01/12 786 at32uc3a tabl e 38-35. programming time temper ature operat ing range part page programm ing time (ms) chip era s e time (ms) industrial 4 4 au tomoti ve 16 16 32058k avr32-01/12 787 at32uc3a 39. me chani ca l cha ra ct eristi cs 39.1 thermal considerations 39.1.1 thermal data ta ble 39-1 summarizes the ther mal resistanc e dat a dependin g on th e package. 39.1.2 junction temperature th e average chip-junction temperature, t j , in c ca n be obtained from the following: 1. 2. where: ? ja = package therma l resistance, junction-to-ambient (c/w), provided in ta ble 39-1 on page 787. ? jc = packag e therma l resistance, junction-to-ca se ther mal resist ance (c/ w), prov ided in ta ble 39- 1 o n pa ge 787. ? h eat si nk = co olin g device therma l resistanc e (c/w), provided in t h e de vice datasheet. ?p d = d e vice power consumptio n (w) estimate d fro m data provid ed in the section ?power consumption ? o n p age 767. ?t a = am bient temperature (c). from the first equ ati on, the user can derive the estimated lifetime of the chip and deci d e if a cooling de vice is necessar y or not . if a cooling devic e is t o be fi tted on th e chip , the se cond equation shou ld be used to compute th e resulting average chip-junction temperature t j in c. tabl e 39-1. thermal resi stance data symbol parameter condition package typ unit ja junction-to-ambi ent thermal resistance still air tqfp100 43.4 ?c/w jc ju nction-to-case ther mal resistance tqfp100 5.5 ja junction-to-ambi ent thermal resistance still air lqfp144 39.8 ?c/w jc ju nction-to-case ther mal resistance lqfp144 8.9 t j t a p d j a ( ) + = t j t a p ( d ( heatsink jc )) + + = 32058k avr32-01/12 788 at32uc3a 39.2 package drawings figur e 39-1. tqfp-100 package drawing tabl e 39-2. device an d packa ge maximu m weight 500 mg tabl e 39-3. package characteristics moisture sens itivit y level j dec j-std0-20d - msl 3 tabl e 39-4. package reference jedec d raw ing reference ms-026 jesd97 classification e3 32058k avr32-01/12 789 at32uc3a figur e 39-2. lqf p-14 4 packag e d rawing tabl e 39-5. device an d packa ge maximu m weight 1300 mg tabl e 39-6. package characteristics moisture sens itivit y level j dec j-std0-20d - msl 3 tabl e 39-7. package reference jedec d raw ing reference ms-026 jesd97 classification e3 32058k avr32-01/12 790 at32uc3a figur e 39-3. ffbga-1 44 p acka ge d r awing tabl e 39-8. device an d packa ge maximu m weight 1300 mg tabl e 39-9. package characteristics moisture sens itivit y level msl3 tabl e 39-10. package reference jedec d raw ing reference ms-026 jesd97 classification e3 32058k avr32-01/12 791 at32uc3a 39.3 s oldering profile ta ble 39-11 gives t h e recommende d solderin g profile from j-std-20. note: i t is recommende d to ap ply a soldering temper ature hi gher than 250c. a maxim um o f thre e refl ow passes is allo wed pe r component. tabl e 39-11. soldering profile pr ofile feature green package average ramp -up rate (217 c to peak) 3c/sec preheat te mperature 175c 25c min. 1 50 c , max. 20 0 c time m aintain ed abov e 217c 60-1 50 sec time within 5? c of actual peak temperature 30 sec peak temper ature range 260 c ramp-dow n rate 6 c/sec time 2 5? c to pea k temp erature max . 8 m i n ut es 32058k avr32-01/12 792 at32uc3a 40. ordering information 40.1 automotive quality grade the at32uc3a have been developed and manufactured according to the most stringent requirements of the international standard iso-ts-16949. this data sheet will contain limit val- ues extracted from the results of extensive characterization (temperature and voltage). the quality and reliability of the at32uc3a is verified during regular product qualification as per aec-q100 grade 3. as indicated in the ordering information paragraph, the product is available in only one tempera- ture grade t: -40c / + 85c. table 40-1. ordering information device ordering code package conditioning temperature operating range at32uc3a0512 at32uc3a0512-alut 144 lqfp tray industrial (-40 ? c to 85 ?c) at32uc3a0512-alur 144 lqfp reel industrial (-40 ? c to 85 ?c) at32uc3a0512-altra 144 lqfp reel automotive (-40 ? c to 85 ?c) at32uc3a0512-altta 144 lqfp tray automotive (-40 ? c to 85 ?c) at32uc3a0512-ctut 144 ffbga tray industrial (-40 ? c to 85 ?c) at32uc3a0512-ctur 144 ffbga reel industrial (-40 ? c to 85 ?c) at32uc3a0256 at32uc3a0256-alut 144 lqfp tray industrial (-40 ? c to 85 ?c) at32uc3a0256-alur 144 lqfp reel industrial (-40 ? c to 85 ?c) at32uc3a0256-ctut 144 ffbga tray industrial (-40 ? c to 85 ?c) at32uc3a0256-ctur 144 ffbga reel industrial (-40 ? c to 85 ?c) at32uc3a0128 at32uc3a0128-alut 144 lqfp tray industrial (-40 ? c to 85 ?c) at32uc3a0128-alur 144 lqfp reel industrial (-40 ? c to 85 ?c) at32uc3a0128-ctut 144 ffbga tray industrial (-40 ? c to 85 ?c) at32uc3a0128-ctur 144 ffbga reel industrial (-40 ? c to 85 ?c) at32uc3a1512 at32uc3a1512-aut 100 tqfp tray industrial (-40 ? c to 85 ?c) at32uc3a1512-aur 100 tqfp reel industrial (-40 ? c to 85 ?c) at32uc3a1256 at32uc3a1256-aut 100 tqfp tray industrial (-40 ? c to 85 ?c) at32uc3a1256-aur 100 tqfp reel industrial (-40 ? c to 85 ?c) at32uc3a1128 at32uc3a1128-aut 100 tqfp tray industrial (-40 ? c to 85 ? c) a t32uc3a1128-aur 100 tqfp reel industrial (-40 ? c to 85 ?c) 32058k avr32-01/12 793 at32uc3a 41. errata all industrial parts labelled with -ues (engineering samples) are revision e parts. all automotive parts labelled with at32uc3a0512-altra or at32uc3a0512-altta are revi - sion k parts. 41.1 rev. k , l, m 41.1.1 pwm 1. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 41.1.2 adc 1. sleep mode activation needs additional a to d conversion if the adc sleep mode is activated when the adc is idle the adc will not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 41.1.3 spi 1. spi slave / pdca transfer: no tx underrun flag there is no tx underrun flag available, therefore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 2. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1. 32058k avr32-01/12 794 at32uc3a 3. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck. fix/workaround when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 4. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxready will now behave as expected. 5. spi disable does not work in slave mode fix/workaround read the last received data then perform a software reset. 41.1.4 power manager 1. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and enabled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod level and is lower than vddcore max and disable the bod. 41.1.5 pdca 1. wrong pdca behavior when using two pdca channels with the same pid. fix/workaround the same pid should not be assigned to more than one channel. 41.1.6 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the register twi rhr must be read. 41.1.7 usart 1. iso7816 info register us_ner cannot be read the ner register always returns zero. fix/workaround none 41.1.8 processor and architecture 1. ldm instruction with pc in the register list and without ++ increments rp 32058k avr32-01/12 795 at32uc3a for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 41.1. 9 f lashc 1. reading from on-chip flash may fail after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands). after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands), the following flash read access may return corrupted data. this erratum does not affect write operations to regular flash memory. fix/workaround the flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands) must be issued from internal ram. after the write operation, perform a dummy flash page write operation (flashc wp). content and location of this page is not important and filling the write buffer with all one (ffh) will leave the current flash content unchanged. it is then safe to read and fetch code from the flash. 32058k avr32-01/12 796 at32uc3a 41.2 rev. j 41.2.1 pwm 1. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 41.2.2 adc 1. sleep mode activation needs additional a to d conversion if the adc sleep mode is activated when the adc is idle the adc will not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 41.2.3 spi 1. spi slave / pdca transfer: no tx underrun flag there is no tx underrun flag available, therefore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 2. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1. 3. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck. fix/workaround 32058k avr32-01/12 797 at32uc3a when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 4. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxready will now behave as expected. 5. spi disable does not work in slave mode fix/workaround read the last received data then perform a software reset. 41.2.4 power manager 1. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and enabled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod level and is lower than vddcore max and disable the bod. 41.2.5 pdca 1. wrong pdca behavior when using two pdca channels with the same pid. fix/workaround the same pid should not be assigned to more than one channel. 41.2.6 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the register twi rhr must be read. 41.2.7 sdramc 1. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram. 41.2.8 gpio 1. pa29 (twi sda) and pa30 (twi scl) gpio vih (input high voltage) is 3.6v max instead of 5v tolerant the following gpios are not 5v tolerant : pa29 and pa30. fix/workaround 32058k avr32-01/12 798 at32uc3a none. 41.2.9 usart 1. iso7816 info register us_ner cannot be read the ner register always returns zero. fix/workaround none 41.2.10 processor and architecture 1. ldm instruction with pc in the register list and without ++ increments rp for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 2. rete instruction does not clear sreg[l] from interrupts. the rete instruction clears sreg[l] as expected from exceptions. fix/workaround when using the stcond instruction, clear sreg[l] in the stacked value of sr before returning from interrupts with rete. 3. exceptions when system stack is protected by mpu rets behaves incorrectly when mpu is enabled and mpu is configured so that system stack is not readable in unprivileged mode. fix/woraround workaround 1: make system stack readable in unprivileged mode, or workaround 2: return from supervisor mode using rete instead of rets. this requires : 1. changing the mode bits from 001b to 110b before issuing the instruction. updating the mode bits to the desired value must be done using a single mt- sr instruction so it is done atomically. even if this step is described in general as not safe in the uc technical reference guide, it is safe in this very specific case. 2. execute the rete instruction. 1. reading from on-chip flash may fail after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands). after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands), the following flash read access may return corrupted data. this erratum does not affect write operations to regular flash memory. fix/workaround the flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands) must be issued from internal ram. after the write operation, perform a dummy flash page write operation (flashc wp). content and location of this page is not important and filling the write buffer with all one (ffh) will leave the current flash content unchanged. it is then safe to read and fetch code from the flash. 41. 2 . 11 f lashc 32058k avr32-01/12 799 at32uc3a 41.3 rev. i 41.3.1 pwm 1. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 41.3.2 adc 1. sleep mode activation needs additional a to d conversion if the adc sleep mode is activated when the adc is idle the adc will not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 41.3.3 spi 1. spi slave / pdca transfer: no tx underrun flag there is no tx underrun flag available, therefore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 2. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1. 3. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck. fix/workaround 32058k avr32-01/12 800 at32uc3a when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 4. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxready will now behave as expected. 5. spi disable does not work in slave mode fix/workaround read the last received data then perform a software reset. 41.3.4 power manager 1. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and enabled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod level and is lower than vddcore max and disable the bod. 41.3.5 flashc 1. on at32uc3a0512 and at32uc3a1512, corrupted read in flash after flashc wp, ep, ea, wup, eup commands may happen - after a flashc write page (wp) or erase page (ep) command applied to a page in a given half of the flash (first or last 256 kb of flash), reading (data read or code fetch) the other half of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc erase all (ea) command, reading (data read or code fetch) the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc write user page (wup) or erase user page (eup) command, reading (data read or code fetch) the second half (last 256 kb) of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. fix/workaround flashc wp, ep, ea, wup, eup commands: these commands must be issued from ram or through the ebi. after these commands, read twice one flash page initialized to 00h in each half part of the flash. 41.3.6 pdca 1. wrong pdca behavior when using two pdca channels with the same pid. 32058k avr32-01/12 801 at32uc3a workaround/fix the same pid should not be assigned to more than one channel. 41.3.7 gpio 1. some gpio vih (input high voltage) are 3.6v max instead of 5v tolerant only 11 gpios remain 5v tolerant (vihmax=5v):pb01, pb02, pb03, pb10, pb19, pb20, pb21, pb22, pb23, pb27, pb28 . workaround/fix none. 41.3.8 usart 1. iso7816 info register us_ner cannot be read the ner register always returns zero. fix/workaround none. 41.3.9 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the register twi rhr must be read. 41.3.10 sdramc 1. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram. 41.3.11 processor and architecture 1. ldm instruction with pc in the register list and without ++ increments rp for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 2. rete instruction does not clear sreg[l] from interrupts. the rete instruction clears sreg[l] as expected from exceptions. fix/workaround when using the stcond instruction, clear sreg[l] in the stacked value of sr before returning from interrupts with rete. 3. exceptions when system stack is protected by mpu rets behaves incorrectly when mpu is enabled and mpu is configured so that system stack is not readable in unprivileged mode. fix/woraround workaround 1: make system stack readable in unprivileged mode, or workaround 2: return from supervisor mode using rete instead of rets. this requires : 1. changing the mode bits from 001b to 110b before issuing the instruction. updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically. even if this step is described in general as not safe in the uc technical reference guide, it is safe in this very 32058k avr32-01/12 802 at32uc3a specific case. 2. execute the rete instruction. 1. reading from on-chip flash may fail after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands). after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands), the following flash read access may return corrupted data. this erratum does not affect write operations to regular flash memory. fix/workaround the flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands) must be issued from internal ram. after the write operation, perform a dummy flash page write operation (flashc wp). content and location of this page is not important and filling the write buffer with all one (ffh) will leave the current flash content unchanged. it is then safe to read and fetch code from the flash. 41. 3 . 12 f lashc 32058k avr32-01/12 803 at32uc3a 41.4 rev. h 41.4.1 pwm 1. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 41.4.2 adc 1. sleep mode activation needs additional a to d conversion if the adc sleep mode is activated when the adc is idle the adc will not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 41.4.3 spi 1. spi slave / pdca transfer: no tx underrun flag there is no tx underrun flag available, therefore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 2. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1 3. spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset. 32058k avr32-01/12 804 at32uc3a 4. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck. fix/workaround when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 5. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxready will now behave as expected. 6. spi disable does not work in slave mode fix/workaround read the last received data then perform a software reset. 41.4.4 power manager 1. wrong reset causes when bod is activated setting the bod enable fuse will cause the reset cause register to list bod reset as the reset source even though the part was reset by another source. fix/workaround do not set the bod enable fuse, but activate the bod as soon as your program starts. 2. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and enabled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod level and is lower than vddcore max and disable the bod. 41.4.5 flashc 1. on at32uc3a0512 and at32uc3a1512, corrupted read in flash after flashc wp, ep, ea, wup, eup commands may happen - after a flashc write page (wp) or erase page (ep) command applied to a page in a given half of the flash (first or last 256 kb of flash), reading (data read or code fetch) the other half of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc erase all (ea) command, reading (data read or code fetch) the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc write user page (wup) or erase user page (eup) command, reading 32058k avr32-01/12 805 at32uc3a (data read or code fetch) the second half (last 256 kb) of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. fix/workaround flashc wp, ep, ea, wup, eup commands: these commands must be issued from ram or through the ebi. after these commands, read twice one flash page initialized to 00h in each half part of the flash. 41.4.6 pdca 1. wrong pdca behavior when using two pdca channels with the same pid. workaround/fix the same pid should not be assigned to more than one channel. 41.4.7 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the register twi rhr must be read. 41.4.8 sdramc 1. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram. 41.4.9 gpio 1. some gpio vih (input high voltage) are 3.6v max instead of 5v tolerant only 11 gpios remain 5v tolerant (vihmax=5v):pb01, pb02, pb03, pb10, pb19, pb20, pb21, pb22, pb23, pb27, pb28 . workaround/fix none. 41.4.10 usart 1. iso7816 info register us_ner cannot be read the ner register always returns zero. fix/workaround none. 41.4.11 processor and architecture 1. ldm instruction with pc in the register list and without ++ increments rp for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 2. rete instruction does not clear sreg[l] from interrupts. the rete instruction clears sreg[l] as expected from exceptions. fix/workaround when using the stcond instruction, clear sreg[l] in the stacked value of sr before returning from interrupts with rete. 3. exceptions when system stack is protected by mpu 32058k avr32-01/12 806 at32uc3a rets behaves incorrectly when mpu is enabled and mpu is configured so that system stack is not readable in unprivileged mode. fix/woraround workaround 1: make system stack readable in unprivileged mode, or workaround 2: return from supervisor mode using rete instead of rets. this requires : 1. changing the mode bits from 001b to 110b before issuing the instruction. updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically. even if this step is described in general as not safe in the uc technical reference guide, it is safe in this very specific case. 2. execute the rete instruction. 1. reading from on-chip flash may fail after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands). after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands), the following flash read access may return corrupted data. this erratum does not affect write operations to regular flash memory. fix/workaround the flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands) must be issued from internal ram. after the write operation, perform a dummy flash page write operation (flashc wp). content and location of this page is not important and filling the write buffer with all one (ffh) will leave the current flash content unchanged. it is then safe to read and fetch code from the flash. 41. 4 . 12 f lashc 32058k avr32-01/12 807 at32uc3a 41.5 rev. e 41.5.1 spi 1. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1. 2. spi slave / pdca transfer: no tx underrun flag there is no tx underrun flag available, therefore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 3. spi bad serial clock generation on 2nd chip select when scbr=1, cpol=1 and cncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn?t equal to 1, and cpol=1 and cpha=0, then an additional pulse will be generated on sck. fix/workaround when multiple cs are in use, if one of the baudrate equals to 1, the other must also equal 1 if cpol=1 and cpha=0. 4. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxready will now behave as expected. 5. spi csnaat bit 2 in register csr0...csr3 is not available. fix/workaround do not use this bit. 6. spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset. 7. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck. 32058k avr32-01/12 808 at32uc3a fix/workaround when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 41.5.2 pwm 1. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 2. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 4. pwm channel status may be wrong if disabled before a period has elapsed before a pwm period has elapsed, the read channel status may be wrong. the chidx-bit for a pwm channel in the pwm enable register will read '1' for one full pwm period even if the channel was disabled before the period elapsed. it will then read '0' as expected. fix/workaround reading the pwm channel status of a disabled channel is only correct after a pwm period has elapsed. 41.5.3 ssc 1. ssc does not trigger rf when data is low the ssc cannot transmit or receive data when cks = ckdiv and cko = none, in tcmr or rcmr respectively. fix/workaround set cko to a value that is not "none" and bypass the output of the tk/rk pin with the pio. 2. ssc data is not sent unless clock is set as output the ssc cannot transmit or receive data when cks = ckdiv and cko = none, in tcmr or rcmr respectively. fix/workaround set cko to a value that is not "none" and bypass the output of the tk/rk pin with the pio. 32058k avr32-01/12 809 at32uc3a 41.5.4 usb 1. usb no end of host reset signaled upon disconnection in host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the uhcon.reset bit may not been cleared by the hardware at the end of the reset. fix/workaround a software workaround consists in testing (by polling or interrupt) the disconnection (uhint.ddisci == 1) while waiting for the end of reset (uhcon.reset == 0) to avoid being stuck. 2. usbfsm and uhaddr1/2/3 registers are not available. do not use usbfsm register. fix/workaround do not use usbfsm register and use hcon[6:0] field instead for all the pipes. 41.5.5 processor and architecture 1. incorrect processor id the processor id reads 0x01 and not 0x02 as it should. fix/workaround none. 2. bus error should be masked in debug mode if a bus error occurs during debug mode, the processor will not respond to debug com- mands through the dinst register. fix/workaround a reset of the device will make the cpu respond to debug commands again. 3. read modify write (rmw) instructions on data outside the internal ram does not work. read modify write (rmw) instructions on data outside the internal ram does not work. fix/workaround do not perform rmw instructions on data outside the internal ram. 4. crc calculation of a locked device will calculate crc for 512 kb of flash memory, even though the part has less flash. fix/workaround the flash address space is wrapping, so it is possible to use the crc value by calculating crc of the flash content concatenated with itself n times. where n is 512 kb/flash size. 5. need two nops instruction after instructions masking interrupts the instructions following in the pipeline the instruction masking the interrupt through sr may behave abnormally. fix/workaround place two nops instructions after each ssrf or mtsr instruction setting ixm or gm in sr. 32058k avr32-01/12 810 at32uc3a 6. cpu cycle counter does not reset the count system register on compare match. the device revision e does not reset the count system register on compare match. in this revision, the count register is clocked by the cpu clock, so when the cpu clock stops, so does incrementing of count . fix/workaround none. 7. memory protection unit (mpu) is non functional. fix/workaround do not use the mpu. 8. the following alternate gpio function c are not available in reve macb-wol on gpio9 (pa09), macb-wol on gpio18 (pa18), usb-usb_id on gpio21 (pa21), usb-usb_vbof on gpio22 (pa22), and all function b and c on gpio70 to gpio101 (px00 to px39). fix/workaround do not use these alternate b and c functions on the listed gpio pins. 9. clock connection table on rev e here is the table of rev e figure 41-1. timer/counter clock connections on reve 10. local bus fast gpio not available in reve. fix/workaround do not use on this silicon revision. 11. spurious interrupt may corrupt core sr mode to exception if the rules listed in the chapter `masking interrupt requests in peripheral modules' of the avr32uc technical reference manual are not followed, a spurious interrupt may occur. an interrupt context will be pushed onto the stack while the core sr mode will indicate an exception. a rete instruction would then corrupt the stack.. fix/workaround follow the rules of the avr32uc technical reference manual. to increase software robustness, if an exception mode is detected at the beginning of an interrupt handler, change the stack interrupt context to an exception context and issue a rete instruction. source name connection internal timer_clock1 32 khz oscillator timer_clock2 pba clock / 4 timer_clock3 pba clock / 8 timer_clock4 pba clock / 16 timer_clock5 pba clock / 32 external xc0 xc1 xc2 32058k avr32-01/12 811 at32uc3a 12. cpu cannot operate on a divided slow clock (internal rc oscillator) fix/workaround do not run the cpu on a divided slow clock. 13. ldm instruction with pc in the register list and without ++ increments rp for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 14. rete instruction does not clear sreg[l] from interrupts. the rete instruction clears sreg[l] as expected from exceptions. fix/workaround when using the stcond instruction, clear sreg[l] in the stacked value of sr before returning from interrupts with rete. 15. exceptions when system stack is protected by mpu rets behaves incorrectly when mpu is enabled and mpu is configured so that system stack is not readable in unprivileged mode. fix/woraround workaround 1: make system stack readable in unprivileged mode, or workaround 2: return from supervisor mode using rete instead of rets. this requires : 1. changing the mode bits from 001b to 110b before issuing the instruction. updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically. even if this step is described in general as not safe in the uc technical reference guide, it is safe in this very specific case. 2. execute the rete instruction. 41.5.6 sdramc 1. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram. 2. sdram sdcke rise at the same time as sdck while exiting self-refresh mode sdcke rise at the same time as sdck while exiting self-refresh mode. fix/workaround none. 41.5.7 usart 1. usart manchester encoder not working manchester encoding/decoding is not working. fix/workaround do not use manchester encoding. 32058k avr32-01/12 812 at32uc3a 2. usart rxbreak problem when no timeguard in asynchronous mode the rxbreak flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. fix/workaround if the nbstop is 1, timeguard should be different from 0. 3. usart handshaking: 2 characters sent / cts rises when tx if cts switches from 0 to 1 during the tx of a character, if the holding register is not empty, the txholding is also transmitted. fix/workaround none. 4. usart pdc and timeguard not supported in manchester manchester encoding/decoding is not working. fix/workaround do not use manchester encoding. 5. usart spi mode is non functional on this revision. fix/workaround do not use the usart spi mode. 6. dcd is active high instead of low. in modem mode the dcd signal is assumed to be active high by the usart, butshould have been active low. fix/workaround add an external inverter to the dcd line. 7. iso7816 info register us_ner cannot be read the ner register always returns zero. fix/workaround none. 41.5.8 power manager 1. voltage regulator input and output is connected to vddio and vddcore inside the device the voltage regulator input and output is connected to vddio and vddcore respectively inside the device. fix/workaround do not supply vddcore externally, as this supply will work in paralell with the regulator. 2. wrong reset causes when bod is activated setting the bod enable fuse will cause the reset cause register to list bod reset as the reset source even though the part was reset by another source. fix/workaround do not set the bod enable fuse, but activate the bod as soon as your program starts. 3. pll0/1 lock control does not work lock control does not work for pll0 and pll1. 32058k avr32-01/12 813 at32uc3a fix/workaround in pll0/1 control register, the bit 7 should be set in order to prevent unexpected behaviour. 4. peripheral bus a maximum frequency is 33mhz instead of 66mhz. fix/workaround do not set pba frequency higher than 33 mhz. 5. pcx pins go low in stop mode in sleep mode stop all pcx pins will be controlled by gpio module instead of oscillators. this can cause drive contention on the xinx in worst case. fix/workaround before entering stop mode set all pcx pins to input and gpio controlled. 6. on some rare parts, the maximum hsb and cpu speed is 50mhz instead of 66mhz. fix/workaround do not set the hsb/cpu speed higher than 50mhz when the firmware generate exceptions. 7. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and enabled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod level and is lower than vddcore max and disable the bod. 8. system timer mask (bit 16) of the pm cpumask register is not available. fix/workaround do not use this bit. 41.5.9 hmatrix 1. hmatrix fixed priority arbitration does not work fixed priority arbitration does not work. fix/workaround use round-robin arbitration instead. 41.5.10 adc 1. adc possible miss on drdy when disabling a channel the adc does not work properly when more than one channel is enabled. fix/workaround do not use the adc with more than one channel enabled at a time. 2. adc ovre flag sometimes not reset on status register read the ovre flag does not clear properly if read simultaneously to an end of conversion. fix/workaround none. 3. sleep mode activation needs additional a to d conversion 32058k avr32-01/12 814 at32uc3a if the adc sleep mode is activated when the adc is idle the adc will not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 41.5.11 abdac 1. audio bitstream dac is not functional. fix/workaround do not use the abdac on reve. 41.5.12 flashc 1. the address of flash general purpose fuse register low (fgpfrlo) is 0xfffe140c on reve instead of 0xfffe1410. fix/workaround none. 2. the command quick page read user page(qprup) is not functional. fix/workaround none. 3. pagen semantic field for program gp fuse byte is writedata[7:0], byteaddress[1:0] on revision e instead of writedata[7:0], byteaddress[2:0]. fix/workaround none. 4. on at32uc3a0512 and at32uc3a1512, corrupted read in flash after flashc wp, ep, ea, wup, eup commands may happen - after a flashc write page (wp) or erase page (ep) command applied to a page in a given half of the flash (first or last 256 kb of flash), reading (data read or code fetch) the other half of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc erase all (ea) command, reading (data read or code fetch) the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc write user page (wup) or erase user page (eup) command, reading (data read or code fetch) the second half (last 256 kb) of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. fix/workaround flashc wp, ep, ea, wup, eup commands: these commands must be issued from ram or through the ebi. after these commands, read twice one flash page initialized to 00h in each half part of the flash. 41.5.13 rtc 1. writes to control (ctrl), top (top) and value (val) in the rtc are discarded if the rtc peripheral bus clock (pba) is divided by a factor of four or more relative to the hsb clock. fix/workaround do not write to the rtc registers using the peripheral bus clock (pba) divided by a factor of four or more relative to the hsb clock. 32058k avr32-01/12 815 at32uc3a 2. the rtc clken bit (bit number 16) of ctrl register is not available. fix/workaround do not use the clken bit of the rtc on rev e . 41.5.14 ocd 1. stalled memory access instruction writeback fails if followed by a hw breakpoint. consider the following assembly code sequence: a b if a hardware breakpoint is placed on instruction b, and instruction a is a memory access instruction, register file updates from instruction a can be discarded. fix/workaround do not place hardware breakpoints, use software breakpoints instead. alternatively, place a hardware breakpoint on the instruction before the memory access instruction and then single step over the memory access instruction. 41.5.15 pdca 1. wrong pdca behavior when using two pdca channels with the same pid. workaround/fix the same pid should not be assigned to more than one channel. 41.5.16 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the register twi rhr must be read. 1. reading from on-chip flash may fail after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands). after a flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands), the following flash read access may return corrupted data. this erratum does not affect write operations to regular flash memory. fix/workaround the flash fuse write operation (flashc lp, up, wgpb, egpb, ssb, pgpfb, eagpf commands) must be issued from internal ram. after the write operation, perform a dummy flash page write operation (flashc wp). content and location of this page is not important and filling the write buffer with all one (ffh) will leave the current flash content unchanged. it is then safe to read and fetch code from the flash. 41. 5 . 17 f lashc 32058k avr32-01/12 816 at32uc3a 42. datasheet revision history please note that the referring page numbers in this section are referred to this document. the referring revision in this section are referring to the document revision. 42. 2 rev. i ? 11/09 42. 3 rev. h ? 03/09 42. 4 rev. g ? 01/09 42. 5 rev. f ? 08/08 1. remove ordering code for automotive engineering samples 2. replace old automotive odering codes at32uc3a0512-altr (revision i) by at32uc3a0512-altra (revision k). replace old automotive odering codes at32uc3a0512-altt (revision i) by at32uc3a0512-altta (revision k). 1. update ?errata? on page 779 . 2. update eletrical characteristic in ?dc characteristics? on page 2 . 3. add bga144 package information. 1. update ?errata? on page 779 . 2. update gpio eletrical characteristic in ?dc characteristics? on page 2 . 1. add revision j to ?errata? on page 779 . 2. update dmips number in ?features? on page 1 . 42.1 rev. k ? 01 / 12 1. 2. u pdate errata section 32058k avr32-01/12 817 at32uc3a 42. 6 rev. e ? 04/08 42. 7 rev. d ? 04/08 42. 8 rev. c ? 10/07 42. 9 rev. b ? 10/07 42. 10 rev. a ? 03/07 1. open drain mode removed from ?general-purpose input/output controller (gpio)? on page 151 . 1. updated ?signal description list? on page 8 . removed rxdn and txdn from usart section. 2. updated ?errata? on page 779 . rev g replaced by rev h. 1. updated ?signal description list? on page 8 . removed rxdn and txdn from usart section. 2. updated ?errata? on page 779 . rev g replaced by rev h. 1. updated ?features? on page 1 . 2. update ?blockdiagram? on page 4 with local bus. 3. updated ?peripherals? on page 34 with local bus. 4. add spi feature in ?universial synchronous/asynchronous receiver/transmitter (usart)? on page 315 . 5. updated ?usb on-the-go interface (usbb)? on page 517 . 6. updated ?jtag and boundary scan? on page 750 with programming procedure . 7. add description for silicon rev g. 1. initial revision. 32058k avr32-01/12 i at32uc3a ta ble of contents 1 descr iption . ............................................................................................. 3 2 c onfiguration summary . ........................................................................ 4 3 abbre viations . ......................................................................................... 4 4 b lockdiagram . ......................................................................................... 5 4.1processo r an d architecture . ....................................................................................... 6 5 s ignals description . ................................................................................ 8 6 p ower considerations . ......................................................................... 13 6.1power supplies . ....................................................................................................... 13 6.2voltage regulator . ................................................................................................... 14 6.3analog-to-digital converte r (a.d.c ) reference . . ...................................................... 15 7 p ackage and pinout . ............................................................................. 16 8 i /o line considerations . ....................................................................... 20 8.1j tag pins . ................................................................................................................ 20 8.2reset_n pin . ......................................................................................................... 20 8.3twi pins . ................................................................................................................. 20 8.4gpio pins . ............................................................................................................... 20 9 p rocessor and architecture . ................................................................ 21 9.1avr32 architecture . ................................................................................................ 21 9.2the avr32uc cp u . ............................................................................................... 21 9.3programming mode l . ............................................................................................... 25 9.4exceptions an d interrupts . ....................................................................................... 29 10 me mo ries . .............................................................................................. 33 10.1embedd ed memories . ........................................................................................... 33 10.2physica l memory map . .......................................................................................... 33 10.3bus matrix connection s . ........................................................................................ 34 11 fuses settings . ...................................................................................... 36 1 1.1fl as h gen eral purpos e fuse reg iste r (fgpfr lo) . ............................................. 36 11.2default fu se value . ............................................................................................... 37 12 peripherals . ............................................................................................ 38 12.1periphera l address map . ....................................................................................... 38 12.2cpu loca l bus mapping . ...................................................................................... 39 32058k avr32-01/12 ii at32uc3a 12.3interrup t request sign al map . ............................................................................... 41 12.4clock connections . ................................................................................................ 43 12.5nexu s ocd aux p ort connections . ....................................................................... 44 12.6pdc handshake signals . ....................................................................................... 44 12.7periphera l multiplexin g on i/o lines . ...................................................................... 45 1 2.8oscillat o r pi n ou t . .................................................................................................... 48 12.9usart configuration . ........................................................................................... 48 12.10gpi o . ................................................................................................................... 49 12.11peripheral overview . ............................................................................................ 49 13 power manager (pm) . ............................................................................ 53 13.1featur es . ................................................................................................................ 53 13.2descriptio n . ............................................................................................................ 53 13.3blo ck diagram . ...................................................................................................... 54 13.4product dependencie s . ......................................................................................... 55 13.5functional description . .......................................................................................... 55 13.6user interface . ....................................................................................................... 66 14 real time counter (rtc) . ..................................................................... 86 14.1featur es . ................................................................................................................ 86 14.2descriptio n . ............................................................................................................ 86 14.3blo ck diagram . ...................................................................................................... 87 14.4product dependencie s . ......................................................................................... 87 14.5functional description . .......................................................................................... 87 14.6user interface . ....................................................................................................... 89 15 watchdog timer (wdt) . ....................................................................... 94 15.1featur es . ................................................................................................................ 94 15.2descriptio n . ............................................................................................................ 94 15.3blo ck diagram . ...................................................................................................... 94 15.4product dependencie s . ......................................................................................... 94 15.5functional description . .......................................................................................... 95 15.6user interface . ....................................................................................................... 96 16 interrupt controller (intc) . .................................................................. 99 16.1descriptio n . ............................................................................................................ 99 16.2blo ck diagram . ...................................................................................................... 99 16.3operation . .............................................................................................................. 99 16.4user interface . ..................................................................................................... 101 32058k avr32-01/12 iii at32uc3a 17 external inte rr upts controller (eic) . .................................................. 105 17.1featur es . ............................................................................................................. 105 17.2descriptio n . .......................................................................................................... 105 17.3blo ck diagram . .................................................................................................... 106 17.4product dependencie s . ....................................................................................... 106 17.5functional description . ........................................................................................ 107 17.6user interface . ..................................................................................................... 109 1 8 flash controller (flash c) . ................................................................ 115 18.1featur es . ............................................................................................................. 115 18.2descriptio n . .......................................................................................................... 115 18.3product dependencies . ........................................................................................ 115 18.4functional descriptio n . ......................................................................................... 116 18.5flas h commands . ................................................................................................ 118 18.6general-purpose fus e bits . .................................................................................. 120 18.7security bi t . .......................................................................................................... 122 18.8user interface . ..................................................................................................... 123 19 hsb bus matrix (hmatrix) . .............................................................. 132 19.1 feat ures . ............................................................................................................. 132 19.2descriptio n . .......................................................................................................... 132 19.3memory mapping . ................................................................................................ 132 19.4spec ial bus grantin g mechanism . ...................................................................... 132 19.5arbitratio n . ........................................................................................................... 133 19.6slav e an d master assignatio n . ............................................................................ 135 19.7user interface . ..................................................................................................... 136 20 external bus interface (e b i) . .............................................................. 145 20.1featur es . ............................................................................................................. 145 20.2descriptio n . .......................................................................................................... 145 20.3blo ck diagram . .................................................................................................... 146 20.4i/ o lines descriptio n . .......................................................................................... 147 20.5application exampl e . ........................................................................................... 148 20.6product dependencie s . ....................................................................................... 151 20.7functional description . ........................................................................................ 151 21 peripheral dma controller (pdca) . ................................................... 153 21.1featur es . ............................................................................................................. 153 21.2overview . ............................................................................................................. 153 32058k avr32-01/12 ii 32058?avr32? 11 /09 at32uc3a 12.3interrupt request signal map ................................................................................41 12.4clock connections .................................................................................................43 12.5nexus ocd aux port connections ........................................................................44 12.6pdc handshake signals ........................................................................................44 12.7peripheral multiplexing on i/o lines .......................................................................45 12.8oscillator pinout ....................................................................................................48 12.9usart configuration ............................................................................................48 12.10gpio ....................................................................................................................4 9 12.11peripheral overview .............................................................................................49 13 power manager (pm) ........... ........................................................ ........... 53 13.1features ................................................................................................................53 13.2description .............................................................................................................53 13.3block diagram .......................................................................................................54 13.4product dependencies ..........................................................................................55 13.5functional description ...........................................................................................55 13.6user interface ........................................................................................................66 14 real time counter (rtc) .... ........................................................ ........... 86 14.1features ................................................................................................................86 14.2description .............................................................................................................86 14.3block diagram .......................................................................................................87 14.4product dependencies ..........................................................................................87 14.5functional description ...........................................................................................87 14.6user interface ........................................................................................................89 15 watchdog timer (wdt) ......... ........................................................ ........ 94 15.1features ................................................................................................................94 15.2description .............................................................................................................94 15.3block diagram .......................................................................................................94 15.4product dependencies ..........................................................................................94 15.5functional description ...........................................................................................95 15.6user interface ........................................................................................................96 16 interrupt controller (intc) ............... .......................................... ........... 99 16.1description .............................................................................................................99 16.2block diagram .......................................................................................................99 16.3operation ...............................................................................................................99 16.4user interface ......................................................................................................101 v at32uc3a 25.1 feat ures . ............................................................................................................. 259 25.2overview . ............................................................................................................. 259 25.3blo ck diagram . .................................................................................................... 260 25.4application blo ck diagram . .................................................................................. 260 25.5i/ o lines descriptio n . .......................................................................................... 261 25.6product dependencie s . ....................................................................................... 261 25.7functional description . ........................................................................................ 261 25.8ssc application examples . ................................................................................. 273 25.9user interface . ..................................................................................................... 275 26 universal synchronous / asynchronous receiver/trans mitter (usart) 299 26.1featur es . ............................................................................................................. 299 26.2overview . ............................................................................................................. 299 26.3blo ck diagram . .................................................................................................... 300 26.4application blo ck diagram . .................................................................................. 301 26.5i/ o lines descriptio n . ......................................................................................... 302 26.6product dependencie s . ....................................................................................... 303 26.7functional description . ........................................................................................ 304 2 6.8unive rsa l synchronous/a synchron ou s rece iver/transmitter (usart) user interf ace 339 27 static memor y contro ller (smc) . ....................................................... 366 27.1 feat ures . ............................................................................................................. 366 27.2overview . ............................................................................................................. 366 27.3blo ck diagram . .................................................................................................... 367 27.4i/ o lines descriptio n . .......................................................................................... 367 27.5product dependencie s . ....................................................................................... 368 27.6functionnal description . ...................................................................................... 368 27.7user interface . ..................................................................................................... 403 28 sdram controller (sdramc) . ........................................................... 410 28.1featur es . ............................................................................................................. 410 28.2descriptio n . .......................................................................................................... 410 28.3blo ck diagram . .................................................................................................... 411 28.4i/ o lines descriptio n . .......................................................................................... 411 28.5application exampl e . ........................................................................................... 412 28.6product dependencie s . ....................................................................................... 415 28.7functional description . ........................................................................................ 417 28.8sdram controller user interfac e . ...................................................................... 424 32058k avr32-01/12 vi at32uc3a 29 ethernet mac (macb) . ....................................................................... 437 29.1featur es . ............................................................................................................. 437 29.2descriptio n . .......................................................................................................... 437 29.3blo ck diagram . .................................................................................................... 438 29.4product dependencie s . ....................................................................................... 438 29.5functional description . ........................................................................................ 439 29.6programming interfac e . ....................................................................................... 451 29.7ethernet ma c (macb) user interfac e . ................................................................ 454 3 0 usb on-the-go int e rface (usbb) . .................................................... 497 30.1featur es . ............................................................................................................. 497 30.2descriptio n . .......................................................................................................... 497 30.3blo ck diagram . .................................................................................................... 499 30.4application blo ck diagram . .................................................................................. 500 30.5i/ o lines descriptio n . .......................................................................................... 501 30.6product dependencie s . ....................................................................................... 502 30.7functional description . ........................................................................................ 503 30.8usb user interface . ............................................................................................. 530 31 ti me r/counter (tc) . ............................................................................ 639 31.1featur es . ............................................................................................................. 639 31.2descriptio n . .......................................................................................................... 639 31.3blo ck diagram . .................................................................................................... 640 31.4pin name list . ..................................................................................................... 641 31.5product dependencie s . ....................................................................................... 641 31.6functional description . ........................................................................................ 641 31.7timer counter (tc) user interface . ..................................................................... 654 32 pulse width modulation con t roller (pwm) . ...................................... 673 32.1featur es . ............................................................................................................. 673 32.2descriptio n . .......................................................................................................... 673 32.3blo ck diagram . .................................................................................................... 674 32.4i/ o lines descriptio n . .......................................................................................... 674 32.5product dependencie s . ....................................................................................... 675 32.6functional description . ........................................................................................ 676 32.7pulse widt h modulatio n (pwm ) controller user interface . ................................. 684 33 analog-to-digital converter (adc) . ................................................... 699 33.1featur es . ............................................................................................................. 699 32058k avr32-01/12 vii at32uc3a 33.2overview . ............................................................................................................. 699 33.3blo ck diagram . .................................................................................................... 700 33.4i/ o lines descriptio n . .......................................................................................... 700 33.5product dependencie s . ....................................................................................... 700 33.6functional description . ........................................................................................ 702 33.7user interface . ..................................................................................................... 707 34 audio bitstream dac (abdac) . ........................................................ 721 34.1featur es . ............................................................................................................. 721 34.2descriptio n . .......................................................................................................... 721 34.3blo ck diagram . .................................................................................................... 722 34.4pin name list . ..................................................................................................... 722 34.5product dependencie s . ....................................................................................... 722 34.6functional description . ........................................................................................ 723 34.7audio bitstream dac user interface . .................................................................. 725 34.8frequency response . ......................................................................................... 733 35 on-chip debug . ................................................................................... 734 35.1featur es . ............................................................................................................. 734 35.2overview . ............................................................................................................. 734 35.3blo ck diagram . ..................................................................................................... 735 35.4functional descriptio n . ......................................................................................... 735 36 jtag and boundary scan . ................................................................. 741 36.1featur es . ............................................................................................................. 741 36.2overview . ............................................................................................................. 741 36.3blo ck diagram . ..................................................................................................... 742 36.4i/ o lines descriptio n . .......................................................................................... 743 36.5product dependencie s . ....................................................................................... 743 36.6functional descriptio n . ......................................................................................... 743 36.7jta g instruction summary . ................................................................................ 748 36.8public jtag instructions . .................................................................................... 749 36.9private jtag instructions . ................................................................................... 750 36.10jtag data registers . ........................................................................................ 760 36.11sab addre ss map . ............................................................................................. 761 37 boot sequence . ................................................................................... 762 37.1st arting of clocks . ................................................................................................. 762 37.2fetchin g of initial instructions . ............................................................................. 762 32058k avr32-01/12 viii at32uc3a 38 electrical characteristics . .................................................................. 763 38.1absolute maximu m rating s* . .............................................................................. 763 38.2dc characteris tics . .............................................................................................. 764 38.3regulato r characteristic s . .................................................................................... 765 38.4analog characteristics . ........................................................................................ 765 38.5powe r consumption . ........................................................................................... 767 38.6clock characterist ics . .......................................................................................... 769 38.7cryst al oscillato r characterist is . ......................................................................... 770 38.8adc characteristics . ........................................................................................... 772 38.9ebi timings . ........................................................................................................ 774 38.10jtag timings . ................................................................................................... 780 38.11 spi characteristic s . ........................................................................................... 781 38.12macb characteristics . ...................................................................................... 783 38.13flash characteristics . ........................................................................................ 785 39 mechanical characteristics . ............................................................... 787 39.1thermal considerations . ..................................................................................... 787 39.2package drawings . .............................................................................................. 788 39.3soldering prof ile . ................................................................................................. 791 40 ordering information . ......................................................................... 792 40.1automotive quality grade . .................................................................................. 792 41 errata . ................................................................................................... 793 41.1rev. k . .................................................................................................................. 793 41.2rev. j . .................................................................................................................. 796 41.3rev. i . .................................................................................................................. 799 41.4rev. h . .................................................................................................................. 803 41.5rev. e . .................................................................................................................. 807 42 datasheet revision history . ............................................................... 816 42.1rev. k ? 01/12 . .................................................................................................... 816 42.2rev . g ? 0 1/09 . ................................................................................................... 816 42.3rev. f ? 08/08 . .................................................................................................... 816 42.4rev. e ? 04/08 . .................................................................................................... 816 42.5rev. d ? 04/08 . .................................................................................................... 816 42.6rev. c ? 10/07 . .................................................................................................... 817 42.7rev. b ? 10/07 . .................................................................................................... 817 42.8rev. a ? 03/07 . .................................................................................................... 817 32058k avr32-01/12 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 16f, shin osaki kangyo bldg. 1-6-4 osaka shinagawa-ku tokyo 104-0032 japan tel : (+81) 3-6417-0300 fax : (+81) 3-6417-0370 ? 201 2 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? and others are registered trademarks or trademarks of atmel corpor ation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life. 32058k - avr32-01/12 |
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